1 /* $NetBSD: amdgpu_dcn21_resource.c,v 1.4 2021/12/19 11:59:31 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 * Copyright 2019 Raptor Engineering, LLC
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Authors: AMD
26 *
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn21_resource.c,v 1.4 2021/12/19 11:59:31 riastradh Exp $");
31
32 #include <linux/slab.h>
33
34 #include "dm_services.h"
35 #include "dc.h"
36
37 #include "dcn21_init.h"
38
39 #include "resource.h"
40 #include "include/irq_service_interface.h"
41 #include "dcn20/dcn20_resource.h"
42
43 #include "clk_mgr.h"
44 #include "dcn10/dcn10_hubp.h"
45 #include "dcn10/dcn10_ipp.h"
46 #include "dcn20/dcn20_hubbub.h"
47 #include "dcn20/dcn20_mpc.h"
48 #include "dcn20/dcn20_hubp.h"
49 #include "dcn21_hubp.h"
50 #include "irq/dcn21/irq_service_dcn21.h"
51 #include "dcn20/dcn20_dpp.h"
52 #include "dcn20/dcn20_optc.h"
53 #include "dcn21/dcn21_hwseq.h"
54 #include "dce110/dce110_hw_sequencer.h"
55 #include "dcn20/dcn20_opp.h"
56 #include "dcn20/dcn20_dsc.h"
57 #include "dcn21/dcn21_link_encoder.h"
58 #include "dcn20/dcn20_stream_encoder.h"
59 #include "dce/dce_clock_source.h"
60 #include "dce/dce_audio.h"
61 #include "dce/dce_hwseq.h"
62 #include "virtual/virtual_stream_encoder.h"
63 #include "dce110/dce110_resource.h"
64 #include "dml/display_mode_vba.h"
65 #include "dcn20/dcn20_dccg.h"
66 #include "dcn21_hubbub.h"
67 #include "dcn10/dcn10_resource.h"
68 #include "dce110/dce110_resource.h"
69
70 #include "dcn20/dcn20_dwb.h"
71 #include "dcn20/dcn20_mmhubbub.h"
72 #include "dpcs/dpcs_2_1_0_offset.h"
73 #include "dpcs/dpcs_2_1_0_sh_mask.h"
74
75 #include "renoir_ip_offset.h"
76 #include "dcn/dcn_2_1_0_offset.h"
77 #include "dcn/dcn_2_1_0_sh_mask.h"
78
79 #include "nbio/nbio_7_0_offset.h"
80
81 #include "mmhub/mmhub_2_0_0_offset.h"
82 #include "mmhub/mmhub_2_0_0_sh_mask.h"
83
84 #include "reg_helper.h"
85 #include "dce/dce_abm.h"
86 #include "dce/dce_dmcu.h"
87 #include "dce/dce_aux.h"
88 #include "dce/dce_i2c.h"
89 #include "dcn21_resource.h"
90 #include "vm_helper.h"
91 #include "dcn20/dcn20_vmid.h"
92 #include "../dce/dmub_psr.h"
93
94 #define SOC_BOUNDING_BOX_VALID false
95 #define DC_LOGGER_INIT(logger)
96
97
98 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
99 .odm_capable = 1,
100 .gpuvm_enable = 1,
101 .hostvm_enable = 1,
102 .gpuvm_max_page_table_levels = 1,
103 .hostvm_max_page_table_levels = 4,
104 .hostvm_cached_page_table_levels = 2,
105 .num_dsc = 3,
106 .rob_buffer_size_kbytes = 168,
107 .det_buffer_size_kbytes = 164,
108 .dpte_buffer_size_in_pte_reqs_luma = 44,
109 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
110 .dpp_output_buffer_pixels = 2560,
111 .opp_output_buffer_lines = 1,
112 .pixel_chunk_size_kbytes = 8,
113 .pte_enable = 1,
114 .max_page_table_levels = 4,
115 .pte_chunk_size_kbytes = 2,
116 .meta_chunk_size_kbytes = 2,
117 .writeback_chunk_size_kbytes = 2,
118 .line_buffer_size_bits = 789504,
119 .is_line_buffer_bpp_fixed = 0,
120 .line_buffer_fixed_bpp = 0,
121 .dcc_supported = true,
122 .max_line_buffer_lines = 12,
123 .writeback_luma_buffer_size_kbytes = 12,
124 .writeback_chroma_buffer_size_kbytes = 8,
125 .writeback_chroma_line_buffer_width_pixels = 4,
126 .writeback_max_hscl_ratio = 1,
127 .writeback_max_vscl_ratio = 1,
128 .writeback_min_hscl_ratio = 1,
129 .writeback_min_vscl_ratio = 1,
130 .writeback_max_hscl_taps = 12,
131 .writeback_max_vscl_taps = 12,
132 .writeback_line_buffer_luma_buffer_size = 0,
133 .writeback_line_buffer_chroma_buffer_size = 14643,
134 .cursor_buffer_size = 8,
135 .cursor_chunk_size = 2,
136 .max_num_otg = 4,
137 .max_num_dpp = 4,
138 .max_num_wb = 1,
139 .max_dchub_pscl_bw_pix_per_clk = 4,
140 .max_pscl_lb_bw_pix_per_clk = 2,
141 .max_lb_vscl_bw_pix_per_clk = 4,
142 .max_vscl_hscl_bw_pix_per_clk = 4,
143 .max_hscl_ratio = 4,
144 .max_vscl_ratio = 4,
145 .hscl_mults = 4,
146 .vscl_mults = 4,
147 .max_hscl_taps = 8,
148 .max_vscl_taps = 8,
149 .dispclk_ramp_margin_percent = 1,
150 .underscan_factor = 1.10,
151 .min_vblank_lines = 32, //
152 .dppclk_delay_subtotal = 77, //
153 .dppclk_delay_scl_lb_only = 16,
154 .dppclk_delay_scl = 50,
155 .dppclk_delay_cnvc_formatter = 8,
156 .dppclk_delay_cnvc_cursor = 6,
157 .dispclk_delay_subtotal = 87, //
158 .dcfclk_cstate_latency = 10, // SRExitTime
159 .max_inter_dcn_tile_repeaters = 8,
160
161 .xfc_supported = false,
162 .xfc_fill_bw_overhead_percent = 10.0,
163 .xfc_fill_constant_bytes = 0,
164 .ptoi_supported = 0
165 };
166
167 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
168 .clock_limits = {
169 {
170 .state = 0,
171 .dcfclk_mhz = 304.0,
172 .fabricclk_mhz = 600.0,
173 .dispclk_mhz = 618.0,
174 .dppclk_mhz = 440.0,
175 .phyclk_mhz = 600.0,
176 .socclk_mhz = 278.0,
177 .dscclk_mhz = 205.67,
178 .dram_speed_mts = 1600.0,
179 },
180 {
181 .state = 1,
182 .dcfclk_mhz = 304.0,
183 .fabricclk_mhz = 600.0,
184 .dispclk_mhz = 618.0,
185 .dppclk_mhz = 618.0,
186 .phyclk_mhz = 600.0,
187 .socclk_mhz = 278.0,
188 .dscclk_mhz = 205.67,
189 .dram_speed_mts = 1600.0,
190 },
191 {
192 .state = 2,
193 .dcfclk_mhz = 608.0,
194 .fabricclk_mhz = 1066.0,
195 .dispclk_mhz = 888.0,
196 .dppclk_mhz = 888.0,
197 .phyclk_mhz = 810.0,
198 .socclk_mhz = 278.0,
199 .dscclk_mhz = 287.67,
200 .dram_speed_mts = 2133.0,
201 },
202 {
203 .state = 3,
204 .dcfclk_mhz = 676.0,
205 .fabricclk_mhz = 1600.0,
206 .dispclk_mhz = 1015.0,
207 .dppclk_mhz = 1015.0,
208 .phyclk_mhz = 810.0,
209 .socclk_mhz = 715.0,
210 .dscclk_mhz = 318.334,
211 .dram_speed_mts = 4266.0,
212 },
213 {
214 .state = 4,
215 .dcfclk_mhz = 810.0,
216 .fabricclk_mhz = 1600.0,
217 .dispclk_mhz = 1395.0,
218 .dppclk_mhz = 1285.0,
219 .phyclk_mhz = 1325.0,
220 .socclk_mhz = 953.0,
221 .dscclk_mhz = 489.0,
222 .dram_speed_mts = 4266.0,
223 },
224 /*Extra state, no dispclk ramping*/
225 {
226 .state = 5,
227 .dcfclk_mhz = 810.0,
228 .fabricclk_mhz = 1600.0,
229 .dispclk_mhz = 1395.0,
230 .dppclk_mhz = 1285.0,
231 .phyclk_mhz = 1325.0,
232 .socclk_mhz = 953.0,
233 .dscclk_mhz = 489.0,
234 .dram_speed_mts = 4266.0,
235 },
236
237 },
238
239 .sr_exit_time_us = 12.5,
240 .sr_enter_plus_exit_time_us = 17.0,
241 .urgent_latency_us = 4.0,
242 .urgent_latency_pixel_data_only_us = 4.0,
243 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
244 .urgent_latency_vm_data_only_us = 4.0,
245 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
246 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
247 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
248 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
249 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
250 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
251 .max_avg_sdp_bw_use_normal_percent = 60.0,
252 .max_avg_dram_bw_use_normal_percent = 100.0,
253 .writeback_latency_us = 12.0,
254 .max_request_size_bytes = 256,
255 .dram_channel_width_bytes = 4,
256 .fabric_datapath_to_dcn_data_return_bytes = 32,
257 .dcn_downspread_percent = 0.5,
258 .downspread_percent = 0.5,
259 .dram_page_open_time_ns = 50.0,
260 .dram_rw_turnaround_time_ns = 17.5,
261 .dram_return_buffer_per_channel_bytes = 8192,
262 .round_trip_ping_latency_dcfclk_cycles = 128,
263 .urgent_out_of_order_return_per_channel_bytes = 4096,
264 .channel_interleave_bytes = 256,
265 .num_banks = 8,
266 .num_chans = 4,
267 .vmm_page_size_bytes = 4096,
268 .dram_clock_change_latency_us = 23.84,
269 .return_bus_width_bytes = 64,
270 .dispclk_dppclk_vco_speed_mhz = 3600,
271 .xfc_bus_transport_time_us = 4,
272 .xfc_xbuf_latency_tolerance_us = 4,
273 .use_urgent_burst_bw = 1,
274 .num_states = 5
275 };
276
277 #ifndef MAX
278 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
279 #endif
280 #ifndef MIN
281 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
282 #endif
283
284 /* begin *********************
285 * macros to expend register list macro defined in HW object header file */
286
287 /* DCN */
288 /* TODO awful hack. fixup dcn20_dwb.h */
289 #undef BASE_INNER
290 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
291
292 #define BASE(seg) BASE_INNER(seg)
293
294 #define SR(reg_name)\
295 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
296 mm ## reg_name
297
298 #define SRI(reg_name, block, id)\
299 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
300 mm ## block ## id ## _ ## reg_name
301
302 #define SRIR(var_name, reg_name, block, id)\
303 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
304 mm ## block ## id ## _ ## reg_name
305
306 #define SRII(reg_name, block, id)\
307 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
308 mm ## block ## id ## _ ## reg_name
309
310 #define DCCG_SRII(reg_name, block, id)\
311 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
312 mm ## block ## id ## _ ## reg_name
313
314 /* NBIO */
315 #define NBIO_BASE_INNER(seg) \
316 NBIF0_BASE__INST0_SEG ## seg
317
318 #define NBIO_BASE(seg) \
319 NBIO_BASE_INNER(seg)
320
321 #define NBIO_SR(reg_name)\
322 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
323 mm ## reg_name
324
325 /* MMHUB */
326 #define MMHUB_BASE_INNER(seg) \
327 MMHUB_BASE__INST0_SEG ## seg
328
329 #define MMHUB_BASE(seg) \
330 MMHUB_BASE_INNER(seg)
331
332 #define MMHUB_SR(reg_name)\
333 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
334 mmMM ## reg_name
335
336 #define clk_src_regs(index, pllid)\
337 [index] = {\
338 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
339 }
340
341 static const struct dce110_clk_src_regs clk_src_regs[] = {
342 clk_src_regs(0, A),
343 clk_src_regs(1, B),
344 clk_src_regs(2, C),
345 clk_src_regs(3, D),
346 clk_src_regs(4, E),
347 };
348
349 static const struct dce110_clk_src_shift cs_shift = {
350 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
351 };
352
353 static const struct dce110_clk_src_mask cs_mask = {
354 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
355 };
356
357 static const struct bios_registers bios_regs = {
358 NBIO_SR(BIOS_SCRATCH_3),
359 NBIO_SR(BIOS_SCRATCH_6)
360 };
361
362 static const struct dce_dmcu_registers dmcu_regs = {
363 DMCU_DCN20_REG_LIST()
364 };
365
366 static const struct dce_dmcu_shift dmcu_shift = {
367 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
368 };
369
370 static const struct dce_dmcu_mask dmcu_mask = {
371 DMCU_MASK_SH_LIST_DCN10(_MASK)
372 };
373
374 static const struct dce_abm_registers abm_regs = {
375 ABM_DCN20_REG_LIST()
376 };
377
378 static const struct dce_abm_shift abm_shift = {
379 ABM_MASK_SH_LIST_DCN20(__SHIFT)
380 };
381
382 static const struct dce_abm_mask abm_mask = {
383 ABM_MASK_SH_LIST_DCN20(_MASK)
384 };
385
386 #define audio_regs(id)\
387 [id] = {\
388 AUD_COMMON_REG_LIST(id)\
389 }
390
391 static const struct dce_audio_registers audio_regs[] = {
392 audio_regs(0),
393 audio_regs(1),
394 audio_regs(2),
395 audio_regs(3),
396 audio_regs(4),
397 audio_regs(5),
398 };
399
400 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
401 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
402 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
403 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
404
405 static const struct dce_audio_shift audio_shift = {
406 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
407 };
408
409 static const struct dce_audio_mask audio_mask = {
410 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
411 };
412
413 static const struct dccg_registers dccg_regs = {
414 DCCG_COMMON_REG_LIST_DCN_BASE()
415 };
416
417 static const struct dccg_shift dccg_shift = {
418 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
419 };
420
421 static const struct dccg_mask dccg_mask = {
422 DCCG_MASK_SH_LIST_DCN2(_MASK)
423 };
424
425 #define opp_regs(id)\
426 [id] = {\
427 OPP_REG_LIST_DCN20(id),\
428 }
429
430 static const struct dcn20_opp_registers opp_regs[] = {
431 opp_regs(0),
432 opp_regs(1),
433 opp_regs(2),
434 opp_regs(3),
435 opp_regs(4),
436 opp_regs(5),
437 };
438
439 static const struct dcn20_opp_shift opp_shift = {
440 OPP_MASK_SH_LIST_DCN20(__SHIFT)
441 };
442
443 static const struct dcn20_opp_mask opp_mask = {
444 OPP_MASK_SH_LIST_DCN20(_MASK)
445 };
446
447 #define tg_regs(id)\
448 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
449
450 static const struct dcn_optc_registers tg_regs[] = {
451 tg_regs(0),
452 tg_regs(1),
453 tg_regs(2),
454 tg_regs(3)
455 };
456
457 static const struct dcn_optc_shift tg_shift = {
458 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
459 };
460
461 static const struct dcn_optc_mask tg_mask = {
462 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
463 };
464
465 static const struct dcn20_mpc_registers mpc_regs = {
466 MPC_REG_LIST_DCN2_0(0),
467 MPC_REG_LIST_DCN2_0(1),
468 MPC_REG_LIST_DCN2_0(2),
469 MPC_REG_LIST_DCN2_0(3),
470 MPC_REG_LIST_DCN2_0(4),
471 MPC_REG_LIST_DCN2_0(5),
472 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
473 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
474 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
475 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
476 MPC_DBG_REG_LIST_DCN2_0()
477 };
478
479 static const struct dcn20_mpc_shift mpc_shift = {
480 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
481 MPC_DEBUG_REG_LIST_SH_DCN20
482 };
483
484 static const struct dcn20_mpc_mask mpc_mask = {
485 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
486 MPC_DEBUG_REG_LIST_MASK_DCN20
487 };
488
489 #define hubp_regs(id)\
490 [id] = {\
491 HUBP_REG_LIST_DCN21(id)\
492 }
493
494 static const struct dcn_hubp2_registers hubp_regs[] = {
495 hubp_regs(0),
496 hubp_regs(1),
497 hubp_regs(2),
498 hubp_regs(3)
499 };
500
501 static const struct dcn_hubp2_shift hubp_shift = {
502 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
503 };
504
505 static const struct dcn_hubp2_mask hubp_mask = {
506 HUBP_MASK_SH_LIST_DCN21(_MASK)
507 };
508
509 static const struct dcn_hubbub_registers hubbub_reg = {
510 HUBBUB_REG_LIST_DCN21()
511 };
512
513 static const struct dcn_hubbub_shift hubbub_shift = {
514 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
515 };
516
517 static const struct dcn_hubbub_mask hubbub_mask = {
518 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
519 };
520
521
522 #define vmid_regs(id)\
523 [id] = {\
524 DCN20_VMID_REG_LIST(id)\
525 }
526
527 static const struct dcn_vmid_registers vmid_regs[] = {
528 vmid_regs(0),
529 vmid_regs(1),
530 vmid_regs(2),
531 vmid_regs(3),
532 vmid_regs(4),
533 vmid_regs(5),
534 vmid_regs(6),
535 vmid_regs(7),
536 vmid_regs(8),
537 vmid_regs(9),
538 vmid_regs(10),
539 vmid_regs(11),
540 vmid_regs(12),
541 vmid_regs(13),
542 vmid_regs(14),
543 vmid_regs(15)
544 };
545
546 static const struct dcn20_vmid_shift vmid_shifts = {
547 DCN20_VMID_MASK_SH_LIST(__SHIFT)
548 };
549
550 static const struct dcn20_vmid_mask vmid_masks = {
551 DCN20_VMID_MASK_SH_LIST(_MASK)
552 };
553
554 #define dsc_regsDCN20(id)\
555 [id] = {\
556 DSC_REG_LIST_DCN20(id)\
557 }
558
559 static const struct dcn20_dsc_registers dsc_regs[] = {
560 dsc_regsDCN20(0),
561 dsc_regsDCN20(1),
562 dsc_regsDCN20(2),
563 dsc_regsDCN20(3),
564 dsc_regsDCN20(4),
565 dsc_regsDCN20(5)
566 };
567
568 static const struct dcn20_dsc_shift dsc_shift = {
569 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
570 };
571
572 static const struct dcn20_dsc_mask dsc_mask = {
573 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
574 };
575
576 #define ipp_regs(id)\
577 [id] = {\
578 IPP_REG_LIST_DCN20(id),\
579 }
580
581 static const struct dcn10_ipp_registers ipp_regs[] = {
582 ipp_regs(0),
583 ipp_regs(1),
584 ipp_regs(2),
585 ipp_regs(3),
586 };
587
588 static const struct dcn10_ipp_shift ipp_shift = {
589 IPP_MASK_SH_LIST_DCN20(__SHIFT)
590 };
591
592 static const struct dcn10_ipp_mask ipp_mask = {
593 IPP_MASK_SH_LIST_DCN20(_MASK),
594 };
595
596 #define opp_regs(id)\
597 [id] = {\
598 OPP_REG_LIST_DCN20(id),\
599 }
600
601
602 #define aux_engine_regs(id)\
603 [id] = {\
604 AUX_COMMON_REG_LIST0(id), \
605 .AUXN_IMPCAL = 0, \
606 .AUXP_IMPCAL = 0, \
607 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
608 }
609
610 static const struct dce110_aux_registers aux_engine_regs[] = {
611 aux_engine_regs(0),
612 aux_engine_regs(1),
613 aux_engine_regs(2),
614 aux_engine_regs(3),
615 aux_engine_regs(4),
616 };
617
618 #define tf_regs(id)\
619 [id] = {\
620 TF_REG_LIST_DCN20(id),\
621 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
622 }
623
624 static const struct dcn2_dpp_registers tf_regs[] = {
625 tf_regs(0),
626 tf_regs(1),
627 tf_regs(2),
628 tf_regs(3),
629 };
630
631 static const struct dcn2_dpp_shift tf_shift = {
632 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
633 TF_DEBUG_REG_LIST_SH_DCN20
634 };
635
636 static const struct dcn2_dpp_mask tf_mask = {
637 TF_REG_LIST_SH_MASK_DCN20(_MASK),
638 TF_DEBUG_REG_LIST_MASK_DCN20
639 };
640
641 #define stream_enc_regs(id)\
642 [id] = {\
643 SE_DCN2_REG_LIST(id)\
644 }
645
646 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
647 stream_enc_regs(0),
648 stream_enc_regs(1),
649 stream_enc_regs(2),
650 stream_enc_regs(3),
651 stream_enc_regs(4),
652 };
653
654 static const struct dce110_aux_registers_shift aux_shift = {
655 DCN_AUX_MASK_SH_LIST(__SHIFT)
656 };
657
658 static const struct dce110_aux_registers_mask aux_mask = {
659 DCN_AUX_MASK_SH_LIST(_MASK)
660 };
661
662 static const struct dcn10_stream_encoder_shift se_shift = {
663 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
664 };
665
666 static const struct dcn10_stream_encoder_mask se_mask = {
667 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
668 };
669
670 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
671
672 static int dcn21_populate_dml_pipes_from_context(
673 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
674
dcn21_ipp_create(struct dc_context * ctx,uint32_t inst)675 static struct input_pixel_processor *dcn21_ipp_create(
676 struct dc_context *ctx, uint32_t inst)
677 {
678 struct dcn10_ipp *ipp =
679 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
680
681 if (!ipp) {
682 BREAK_TO_DEBUGGER();
683 return NULL;
684 }
685
686 dcn20_ipp_construct(ipp, ctx, inst,
687 &ipp_regs[inst], &ipp_shift, &ipp_mask);
688 return &ipp->base;
689 }
690
dcn21_dpp_create(struct dc_context * ctx,uint32_t inst)691 static struct dpp *dcn21_dpp_create(
692 struct dc_context *ctx,
693 uint32_t inst)
694 {
695 struct dcn20_dpp *dpp =
696 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
697
698 if (!dpp)
699 return NULL;
700
701 if (dpp2_construct(dpp, ctx, inst,
702 &tf_regs[inst], &tf_shift, &tf_mask))
703 return &dpp->base;
704
705 BREAK_TO_DEBUGGER();
706 kfree(dpp);
707 return NULL;
708 }
709
dcn21_aux_engine_create(struct dc_context * ctx,uint32_t inst)710 static struct dce_aux *dcn21_aux_engine_create(
711 struct dc_context *ctx,
712 uint32_t inst)
713 {
714 struct aux_engine_dce110 *aux_engine =
715 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
716
717 if (!aux_engine)
718 return NULL;
719
720 dce110_aux_engine_construct(aux_engine, ctx, inst,
721 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
722 &aux_engine_regs[inst],
723 &aux_mask,
724 &aux_shift,
725 ctx->dc->caps.extended_aux_timeout_support);
726
727 return &aux_engine->base;
728 }
729
730 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
731
732 static const struct dce_i2c_registers i2c_hw_regs[] = {
733 i2c_inst_regs(1),
734 i2c_inst_regs(2),
735 i2c_inst_regs(3),
736 i2c_inst_regs(4),
737 i2c_inst_regs(5),
738 };
739
740 static const struct dce_i2c_shift i2c_shifts = {
741 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
742 };
743
744 static const struct dce_i2c_mask i2c_masks = {
745 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
746 };
747
dcn21_i2c_hw_create(struct dc_context * ctx,uint32_t inst)748 struct dce_i2c_hw *dcn21_i2c_hw_create(
749 struct dc_context *ctx,
750 uint32_t inst)
751 {
752 struct dce_i2c_hw *dce_i2c_hw =
753 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
754
755 if (!dce_i2c_hw)
756 return NULL;
757
758 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
759 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
760
761 return dce_i2c_hw;
762 }
763
764 static const struct resource_caps res_cap_rn = {
765 .num_timing_generator = 4,
766 .num_opp = 4,
767 .num_video_plane = 4,
768 .num_audio = 4, // 4 audio endpoints. 4 audio streams
769 .num_stream_encoder = 5,
770 .num_pll = 5, // maybe 3 because the last two used for USB-c
771 .num_dwb = 1,
772 .num_ddc = 5,
773 .num_vmid = 1,
774 .num_dsc = 3,
775 };
776
777 #ifdef DIAGS_BUILD
778 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
779 .num_timing_generator = 4,
780 .num_opp = 4,
781 .num_video_plane = 4,
782 .num_audio = 7,
783 .num_stream_encoder = 4,
784 .num_pll = 4,
785 .num_dwb = 1,
786 .num_ddc = 4,
787 .num_dsc = 0,
788 };
789
790 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
791 .num_timing_generator = 2,
792 .num_opp = 2,
793 .num_video_plane = 2,
794 .num_audio = 7,
795 .num_stream_encoder = 2,
796 .num_pll = 4,
797 .num_dwb = 1,
798 .num_ddc = 4,
799 .num_dsc = 2,
800 };
801 #endif
802
803 static const struct dc_plane_cap plane_cap = {
804 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
805 .blends_with_above = true,
806 .blends_with_below = true,
807 .per_pixel_alpha = true,
808
809 .pixel_format_support = {
810 .argb8888 = true,
811 .nv12 = true,
812 .fp16 = true
813 },
814
815 .max_upscale_factor = {
816 .argb8888 = 16000,
817 .nv12 = 16000,
818 .fp16 = 16000
819 },
820
821 .max_downscale_factor = {
822 .argb8888 = 250,
823 .nv12 = 250,
824 .fp16 = 250
825 }
826 };
827
828 static const struct dc_debug_options debug_defaults_drv = {
829 .disable_dmcu = true,
830 .force_abm_enable = false,
831 .timing_trace = false,
832 .clock_trace = true,
833 .disable_pplib_clock_request = true,
834 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
835 .force_single_disp_pipe_split = false,
836 .disable_dcc = DCC_ENABLE,
837 .vsr_support = true,
838 .performance_trace = false,
839 .max_downscale_src_width = 4096,
840 .disable_pplib_wm_range = false,
841 .scl_reset_length10 = true,
842 .sanity_checks = true,
843 .disable_48mhz_pwrdwn = false,
844 .nv12_iflip_vm_wa = true,
845 .usbc_combo_phy_reset_wa = true
846 };
847
848 static const struct dc_debug_options debug_defaults_diags = {
849 .disable_dmcu = true,
850 .force_abm_enable = false,
851 .timing_trace = true,
852 .clock_trace = true,
853 .disable_dpp_power_gate = true,
854 .disable_hubp_power_gate = true,
855 .disable_clock_gate = true,
856 .disable_pplib_clock_request = true,
857 .disable_pplib_wm_range = true,
858 .disable_stutter = true,
859 .disable_48mhz_pwrdwn = true,
860 };
861
862 enum dcn20_clk_src_array_id {
863 DCN20_CLK_SRC_PLL0,
864 DCN20_CLK_SRC_PLL1,
865 DCN20_CLK_SRC_PLL2,
866 DCN20_CLK_SRC_TOTAL_DCN21
867 };
868
dcn21_resource_destruct(struct dcn21_resource_pool * pool)869 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
870 {
871 unsigned int i;
872
873 for (i = 0; i < pool->base.stream_enc_count; i++) {
874 if (pool->base.stream_enc[i] != NULL) {
875 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
876 pool->base.stream_enc[i] = NULL;
877 }
878 }
879
880 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
881 if (pool->base.dscs[i] != NULL)
882 dcn20_dsc_destroy(&pool->base.dscs[i]);
883 }
884
885 if (pool->base.mpc != NULL) {
886 kfree(TO_DCN20_MPC(pool->base.mpc));
887 pool->base.mpc = NULL;
888 }
889 if (pool->base.hubbub != NULL) {
890 kfree(pool->base.hubbub);
891 pool->base.hubbub = NULL;
892 }
893 for (i = 0; i < pool->base.pipe_count; i++) {
894 if (pool->base.dpps[i] != NULL)
895 dcn20_dpp_destroy(&pool->base.dpps[i]);
896
897 if (pool->base.ipps[i] != NULL)
898 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
899
900 if (pool->base.hubps[i] != NULL) {
901 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
902 pool->base.hubps[i] = NULL;
903 }
904
905 if (pool->base.irqs != NULL) {
906 dal_irq_service_destroy(&pool->base.irqs);
907 }
908 }
909
910 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
911 if (pool->base.engines[i] != NULL)
912 dce110_engine_destroy(&pool->base.engines[i]);
913 if (pool->base.hw_i2cs[i] != NULL) {
914 kfree(pool->base.hw_i2cs[i]);
915 pool->base.hw_i2cs[i] = NULL;
916 }
917 if (pool->base.sw_i2cs[i] != NULL) {
918 kfree(pool->base.sw_i2cs[i]);
919 pool->base.sw_i2cs[i] = NULL;
920 }
921 }
922
923 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
924 if (pool->base.opps[i] != NULL)
925 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
926 }
927
928 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
929 if (pool->base.timing_generators[i] != NULL) {
930 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
931 pool->base.timing_generators[i] = NULL;
932 }
933 }
934
935 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
936 if (pool->base.dwbc[i] != NULL) {
937 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
938 pool->base.dwbc[i] = NULL;
939 }
940 if (pool->base.mcif_wb[i] != NULL) {
941 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
942 pool->base.mcif_wb[i] = NULL;
943 }
944 }
945
946 for (i = 0; i < pool->base.audio_count; i++) {
947 if (pool->base.audios[i])
948 dce_aud_destroy(&pool->base.audios[i]);
949 }
950
951 for (i = 0; i < pool->base.clk_src_count; i++) {
952 if (pool->base.clock_sources[i] != NULL) {
953 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
954 pool->base.clock_sources[i] = NULL;
955 }
956 }
957
958 if (pool->base.dp_clock_source != NULL) {
959 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
960 pool->base.dp_clock_source = NULL;
961 }
962
963
964 if (pool->base.abm != NULL)
965 dce_abm_destroy(&pool->base.abm);
966
967 if (pool->base.dmcu != NULL)
968 dce_dmcu_destroy(&pool->base.dmcu);
969
970 if (pool->base.dccg != NULL)
971 dcn_dccg_destroy(&pool->base.dccg);
972
973 if (pool->base.pp_smu != NULL)
974 dcn21_pp_smu_destroy(&pool->base.pp_smu);
975 }
976
977
calculate_wm_set_for_vlevel(int vlevel,struct wm_range_table_entry * table_entry,struct dcn_watermarks * wm_set,struct display_mode_lib * dml,display_e2e_pipe_params_st * pipes,int pipe_cnt)978 static void calculate_wm_set_for_vlevel(
979 int vlevel,
980 struct wm_range_table_entry *table_entry,
981 struct dcn_watermarks *wm_set,
982 struct display_mode_lib *dml,
983 display_e2e_pipe_params_st *pipes,
984 int pipe_cnt)
985 {
986 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
987
988 ASSERT(vlevel < dml->soc.num_states);
989 /* only pipe 0 is read for voltage and dcf/soc clocks */
990 pipes[0].clks_cfg.voltage = vlevel;
991 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
992 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
993
994 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
995 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
996 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
997
998 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
999 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1000 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1001 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1002 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1003 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1004 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1005 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1006 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1007
1008 }
1009
patch_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb)1010 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1011 {
1012 int i;
1013
1014 DC_FP_START();
1015
1016 if (dc->bb_overrides.sr_exit_time_ns) {
1017 for (i = 0; i < WM_SET_COUNT; i++) {
1018 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1019 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1020 }
1021 }
1022
1023 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1024 for (i = 0; i < WM_SET_COUNT; i++) {
1025 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1026 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1027 }
1028 }
1029
1030 if (dc->bb_overrides.urgent_latency_ns) {
1031 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1032 }
1033
1034 if (dc->bb_overrides.dram_clock_change_latency_ns) {
1035 for (i = 0; i < WM_SET_COUNT; i++) {
1036 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1037 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1038 }
1039 }
1040
1041 DC_FP_END();
1042 }
1043
dcn21_calculate_wm(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * out_pipe_cnt,int * pipe_split_from,int vlevel_req)1044 void dcn21_calculate_wm(
1045 struct dc *dc, struct dc_state *context,
1046 display_e2e_pipe_params_st *pipes,
1047 int *out_pipe_cnt,
1048 int *pipe_split_from,
1049 int vlevel_req)
1050 {
1051 int pipe_cnt, i, pipe_idx;
1052 int vlevel, vlevel_max;
1053 struct wm_range_table_entry *table_entry;
1054 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1055
1056 ASSERT(bw_params);
1057
1058 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1059
1060 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1061 if (!context->res_ctx.pipe_ctx[i].stream)
1062 continue;
1063
1064 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1065 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1066
1067 if (pipe_split_from[i] < 0) {
1068 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1069 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1070 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1071 pipes[pipe_cnt].pipe.dest.odm_combine =
1072 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1073 else
1074 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1075 pipe_idx++;
1076 } else {
1077 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1078 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1079 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1080 pipes[pipe_cnt].pipe.dest.odm_combine =
1081 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1082 else
1083 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1084 }
1085 pipe_cnt++;
1086 }
1087
1088 if (pipe_cnt != pipe_idx) {
1089 if (dc->res_pool->funcs->populate_dml_pipes)
1090 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1091 context, pipes);
1092 else
1093 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1094 context, pipes);
1095 }
1096
1097 *out_pipe_cnt = pipe_cnt;
1098
1099 vlevel_max = bw_params->clk_table.num_entries - 1;
1100
1101
1102 /* WM Set D */
1103 table_entry = &bw_params->wm_table.entries[WM_D];
1104 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1105 vlevel = 0;
1106 else
1107 vlevel = vlevel_max;
1108 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1109 &context->bw_ctx.dml, pipes, pipe_cnt);
1110 /* WM Set C */
1111 table_entry = &bw_params->wm_table.entries[WM_C];
1112 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1113 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1114 &context->bw_ctx.dml, pipes, pipe_cnt);
1115 /* WM Set B */
1116 table_entry = &bw_params->wm_table.entries[WM_B];
1117 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1118 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1119 &context->bw_ctx.dml, pipes, pipe_cnt);
1120
1121 /* WM Set A */
1122 table_entry = &bw_params->wm_table.entries[WM_A];
1123 vlevel = MIN(vlevel_req, vlevel_max);
1124 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1125 &context->bw_ctx.dml, pipes, pipe_cnt);
1126 }
1127
1128
dcn21_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1129 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1130 bool fast_validate)
1131 {
1132 bool out = false;
1133
1134 BW_VAL_TRACE_SETUP();
1135
1136 int vlevel = 0;
1137 int pipe_split_from[MAX_PIPES];
1138 int pipe_cnt = 0;
1139 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1140 DC_LOGGER_INIT(dc->ctx->logger);
1141
1142 BW_VAL_TRACE_COUNT();
1143
1144 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1145
1146 if (pipe_cnt == 0)
1147 goto validate_out;
1148
1149 if (!out)
1150 goto validate_fail;
1151
1152 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1153
1154 if (fast_validate) {
1155 BW_VAL_TRACE_SKIP(fast);
1156 goto validate_out;
1157 }
1158
1159 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1160 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1161
1162 BW_VAL_TRACE_END_WATERMARKS();
1163
1164 goto validate_out;
1165
1166 validate_fail:
1167 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1168 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1169
1170 BW_VAL_TRACE_SKIP(fail);
1171 out = false;
1172
1173 validate_out:
1174 kfree(pipes);
1175
1176 BW_VAL_TRACE_FINISH();
1177
1178 return out;
1179 }
dcn21_destroy_resource_pool(struct resource_pool ** pool)1180 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1181 {
1182 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1183
1184 dcn21_resource_destruct(dcn21_pool);
1185 kfree(dcn21_pool);
1186 *pool = NULL;
1187 }
1188
dcn21_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1189 static struct clock_source *dcn21_clock_source_create(
1190 struct dc_context *ctx,
1191 struct dc_bios *bios,
1192 enum clock_source_id id,
1193 const struct dce110_clk_src_regs *regs,
1194 bool dp_clk_src)
1195 {
1196 struct dce110_clk_src *clk_src =
1197 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1198
1199 if (!clk_src)
1200 return NULL;
1201
1202 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1203 regs, &cs_shift, &cs_mask)) {
1204 clk_src->base.dp_clk_src = dp_clk_src;
1205 return &clk_src->base;
1206 }
1207
1208 BREAK_TO_DEBUGGER();
1209 return NULL;
1210 }
1211
dcn21_hubp_create(struct dc_context * ctx,uint32_t inst)1212 static struct hubp *dcn21_hubp_create(
1213 struct dc_context *ctx,
1214 uint32_t inst)
1215 {
1216 struct dcn21_hubp *hubp21 =
1217 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1218
1219 if (!hubp21)
1220 return NULL;
1221
1222 if (hubp21_construct(hubp21, ctx, inst,
1223 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1224 return &hubp21->base;
1225
1226 BREAK_TO_DEBUGGER();
1227 kfree(hubp21);
1228 return NULL;
1229 }
1230
dcn21_hubbub_create(struct dc_context * ctx)1231 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1232 {
1233 int i;
1234
1235 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1236 GFP_KERNEL);
1237
1238 if (!hubbub)
1239 return NULL;
1240
1241 hubbub21_construct(hubbub, ctx,
1242 &hubbub_reg,
1243 &hubbub_shift,
1244 &hubbub_mask);
1245
1246 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1247 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1248
1249 vmid->ctx = ctx;
1250
1251 vmid->regs = &vmid_regs[i];
1252 vmid->shifts = &vmid_shifts;
1253 vmid->masks = &vmid_masks;
1254 }
1255
1256 return &hubbub->base;
1257 }
1258
dcn21_opp_create(struct dc_context * ctx,uint32_t inst)1259 struct output_pixel_processor *dcn21_opp_create(
1260 struct dc_context *ctx, uint32_t inst)
1261 {
1262 struct dcn20_opp *opp =
1263 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1264
1265 if (!opp) {
1266 BREAK_TO_DEBUGGER();
1267 return NULL;
1268 }
1269
1270 dcn20_opp_construct(opp, ctx, inst,
1271 &opp_regs[inst], &opp_shift, &opp_mask);
1272 return &opp->base;
1273 }
1274
dcn21_timing_generator_create(struct dc_context * ctx,uint32_t instance)1275 struct timing_generator *dcn21_timing_generator_create(
1276 struct dc_context *ctx,
1277 uint32_t instance)
1278 {
1279 struct optc *tgn10 =
1280 kzalloc(sizeof(struct optc), GFP_KERNEL);
1281
1282 if (!tgn10)
1283 return NULL;
1284
1285 tgn10->base.inst = instance;
1286 tgn10->base.ctx = ctx;
1287
1288 tgn10->tg_regs = &tg_regs[instance];
1289 tgn10->tg_shift = &tg_shift;
1290 tgn10->tg_mask = &tg_mask;
1291
1292 dcn20_timing_generator_init(tgn10);
1293
1294 return &tgn10->base;
1295 }
1296
dcn21_mpc_create(struct dc_context * ctx)1297 struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1298 {
1299 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1300 GFP_KERNEL);
1301
1302 if (!mpc20)
1303 return NULL;
1304
1305 dcn20_mpc_construct(mpc20, ctx,
1306 &mpc_regs,
1307 &mpc_shift,
1308 &mpc_mask,
1309 6);
1310
1311 return &mpc20->base;
1312 }
1313
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1314 static void read_dce_straps(
1315 struct dc_context *ctx,
1316 struct resource_straps *straps)
1317 {
1318 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1319 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1320
1321 }
1322
1323
dcn21_dsc_create(struct dc_context * ctx,uint32_t inst)1324 struct display_stream_compressor *dcn21_dsc_create(
1325 struct dc_context *ctx, uint32_t inst)
1326 {
1327 struct dcn20_dsc *dsc =
1328 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1329
1330 if (!dsc) {
1331 BREAK_TO_DEBUGGER();
1332 return NULL;
1333 }
1334
1335 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1336 return &dsc->base;
1337 }
1338
update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1339 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1340 {
1341 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1342 struct clk_limit_table *clk_table = &bw_params->clk_table;
1343 int i;
1344
1345 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1346 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1347 dcn2_1_soc.num_chans = bw_params->num_channels;
1348
1349 for (i = 0; i < clk_table->num_entries; i++) {
1350
1351 dcn2_1_soc.clock_limits[i].state = i;
1352 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1353 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1354 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1355 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1356 }
1357 dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - 1];
1358 dcn2_1_soc.num_states = i;
1359
1360 // diags does not retrieve proper values from SMU, do not update DML instance for diags
1361 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment))
1362 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1363 }
1364
1365 /* Temporary Place holder until we can get them from fuse */
1366 static struct dpm_clocks dummy_clocks = {
1367 .DcfClocks = {
1368 {.Freq = 400, .Vol = 1},
1369 {.Freq = 483, .Vol = 1},
1370 {.Freq = 602, .Vol = 1},
1371 {.Freq = 738, .Vol = 1} },
1372 .SocClocks = {
1373 {.Freq = 300, .Vol = 1},
1374 {.Freq = 400, .Vol = 1},
1375 {.Freq = 400, .Vol = 1},
1376 {.Freq = 400, .Vol = 1} },
1377 .FClocks = {
1378 {.Freq = 400, .Vol = 1},
1379 {.Freq = 800, .Vol = 1},
1380 {.Freq = 1067, .Vol = 1},
1381 {.Freq = 1600, .Vol = 1} },
1382 .MemClocks = {
1383 {.Freq = 800, .Vol = 1},
1384 {.Freq = 1600, .Vol = 1},
1385 {.Freq = 1067, .Vol = 1},
1386 {.Freq = 1600, .Vol = 1} },
1387
1388 };
1389
dummy_set_wm_ranges(struct pp_smu * pp,struct pp_smu_wm_range_sets * ranges)1390 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
1391 struct pp_smu_wm_range_sets *ranges)
1392 {
1393 return PP_SMU_RESULT_OK;
1394 }
1395
dummy_get_dpm_clock_table(struct pp_smu * pp,struct dpm_clocks * clock_table)1396 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
1397 struct dpm_clocks *clock_table)
1398 {
1399 *clock_table = dummy_clocks;
1400 return PP_SMU_RESULT_OK;
1401 }
1402
dcn21_pp_smu_create(struct dc_context * ctx)1403 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1404 {
1405 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1406
1407 if (!pp_smu)
1408 return pp_smu;
1409
1410 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
1411 pp_smu->ctx.ver = PP_SMU_VER_RN;
1412 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1413 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1414 } else {
1415
1416 dm_pp_get_funcs(ctx, pp_smu);
1417
1418 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1419 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1420 }
1421
1422 return pp_smu;
1423 }
1424
dcn21_pp_smu_destroy(struct pp_smu_funcs ** pp_smu)1425 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1426 {
1427 if (pp_smu && *pp_smu) {
1428 kfree(*pp_smu);
1429 *pp_smu = NULL;
1430 }
1431 }
1432
dcn21_create_audio(struct dc_context * ctx,unsigned int inst)1433 static struct audio *dcn21_create_audio(
1434 struct dc_context *ctx, unsigned int inst)
1435 {
1436 return dce_audio_create(ctx, inst,
1437 &audio_regs[inst], &audio_shift, &audio_mask);
1438 }
1439
1440 static struct dc_cap_funcs cap_funcs = {
1441 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1442 };
1443
dcn21_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1444 struct stream_encoder *dcn21_stream_encoder_create(
1445 enum engine_id eng_id,
1446 struct dc_context *ctx)
1447 {
1448 struct dcn10_stream_encoder *enc1 =
1449 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1450
1451 if (!enc1)
1452 return NULL;
1453
1454 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1455 &stream_enc_regs[eng_id],
1456 &se_shift, &se_mask);
1457
1458 return &enc1->base;
1459 }
1460
1461 static const struct dce_hwseq_registers hwseq_reg = {
1462 HWSEQ_DCN21_REG_LIST()
1463 };
1464
1465 static const struct dce_hwseq_shift hwseq_shift = {
1466 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1467 };
1468
1469 static const struct dce_hwseq_mask hwseq_mask = {
1470 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1471 };
1472
dcn21_hwseq_create(struct dc_context * ctx)1473 static struct dce_hwseq *dcn21_hwseq_create(
1474 struct dc_context *ctx)
1475 {
1476 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1477
1478 if (hws) {
1479 hws->ctx = ctx;
1480 hws->regs = &hwseq_reg;
1481 hws->shifts = &hwseq_shift;
1482 hws->masks = &hwseq_mask;
1483 hws->wa.DEGVIDCN21 = true;
1484 }
1485 return hws;
1486 }
1487
1488 static const struct resource_create_funcs res_create_funcs = {
1489 .read_dce_straps = read_dce_straps,
1490 .create_audio = dcn21_create_audio,
1491 .create_stream_encoder = dcn21_stream_encoder_create,
1492 .create_hwseq = dcn21_hwseq_create,
1493 };
1494
1495 static const struct resource_create_funcs res_create_maximus_funcs = {
1496 .read_dce_straps = NULL,
1497 .create_audio = NULL,
1498 .create_stream_encoder = NULL,
1499 .create_hwseq = dcn21_hwseq_create,
1500 };
1501
1502 static const struct encoder_feature_support link_enc_feature = {
1503 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1504 .max_hdmi_pixel_clock = 600000,
1505 .hdmi_ycbcr420_supported = true,
1506 .dp_ycbcr420_supported = true,
1507 .flags.bits.IS_HBR2_CAPABLE = true,
1508 .flags.bits.IS_HBR3_CAPABLE = true,
1509 .flags.bits.IS_TPS3_CAPABLE = true,
1510 .flags.bits.IS_TPS4_CAPABLE = true
1511 };
1512
1513
1514 #define link_regs(id, phyid)\
1515 [id] = {\
1516 LE_DCN2_REG_LIST(id), \
1517 UNIPHY_DCN2_REG_LIST(phyid), \
1518 DPCS_DCN21_REG_LIST(id), \
1519 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1520 }
1521
1522 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1523 link_regs(0, A),
1524 link_regs(1, B),
1525 link_regs(2, C),
1526 link_regs(3, D),
1527 link_regs(4, E),
1528 };
1529
1530 #define aux_regs(id)\
1531 [id] = {\
1532 DCN2_AUX_REG_LIST(id)\
1533 }
1534
1535 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1536 aux_regs(0),
1537 aux_regs(1),
1538 aux_regs(2),
1539 aux_regs(3),
1540 aux_regs(4)
1541 };
1542
1543 #define hpd_regs(id)\
1544 [id] = {\
1545 HPD_REG_LIST(id)\
1546 }
1547
1548 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1549 hpd_regs(0),
1550 hpd_regs(1),
1551 hpd_regs(2),
1552 hpd_regs(3),
1553 hpd_regs(4)
1554 };
1555
1556 static const struct dcn10_link_enc_shift le_shift = {
1557 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1558 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1559 };
1560
1561 static const struct dcn10_link_enc_mask le_mask = {
1562 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1563 DPCS_DCN21_MASK_SH_LIST(_MASK)
1564 };
1565
map_transmitter_id_to_phy_instance(enum transmitter transmitter)1566 static int map_transmitter_id_to_phy_instance(
1567 enum transmitter transmitter)
1568 {
1569 switch (transmitter) {
1570 case TRANSMITTER_UNIPHY_A:
1571 return 0;
1572 break;
1573 case TRANSMITTER_UNIPHY_B:
1574 return 1;
1575 break;
1576 case TRANSMITTER_UNIPHY_C:
1577 return 2;
1578 break;
1579 case TRANSMITTER_UNIPHY_D:
1580 return 3;
1581 break;
1582 case TRANSMITTER_UNIPHY_E:
1583 return 4;
1584 break;
1585 default:
1586 ASSERT(0);
1587 return 0;
1588 }
1589 }
1590
dcn21_link_encoder_create(const struct encoder_init_data * enc_init_data)1591 static struct link_encoder *dcn21_link_encoder_create(
1592 const struct encoder_init_data *enc_init_data)
1593 {
1594 struct dcn21_link_encoder *enc21 =
1595 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1596 int link_regs_id;
1597
1598 if (!enc21)
1599 return NULL;
1600
1601 link_regs_id =
1602 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1603
1604 dcn21_link_encoder_construct(enc21,
1605 enc_init_data,
1606 &link_enc_feature,
1607 &link_enc_regs[link_regs_id],
1608 &link_enc_aux_regs[enc_init_data->channel - 1],
1609 &link_enc_hpd_regs[enc_init_data->hpd_source],
1610 &le_shift,
1611 &le_mask);
1612
1613 return &enc21->enc10.base;
1614 }
1615 #define CTX ctx
1616
1617 #define REG(reg_name) \
1618 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1619
read_pipe_fuses(struct dc_context * ctx)1620 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1621 {
1622 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1623 /* RV1 support max 4 pipes */
1624 value = value & 0xf;
1625 return value;
1626 }
1627
dcn21_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes)1628 static int dcn21_populate_dml_pipes_from_context(
1629 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
1630 {
1631 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
1632 int i;
1633 struct resource_context *res_ctx = &context->res_ctx;
1634
1635 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1636
1637 if (!res_ctx->pipe_ctx[i].stream)
1638 continue;
1639
1640 pipes[i].pipe.src.hostvm = 1;
1641 pipes[i].pipe.src.gpuvm = 1;
1642 }
1643
1644 return pipe_cnt;
1645 }
1646
1647 static struct resource_funcs dcn21_res_pool_funcs = {
1648 .destroy = dcn21_destroy_resource_pool,
1649 .link_enc_create = dcn21_link_encoder_create,
1650 .validate_bandwidth = dcn21_validate_bandwidth,
1651 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1652 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1653 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1654 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1655 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1656 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
1657 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1658 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1659 .update_bw_bounding_box = update_bw_bounding_box
1660 };
1661
dcn21_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn21_resource_pool * pool)1662 static bool dcn21_resource_construct(
1663 uint8_t num_virtual_links,
1664 struct dc *dc,
1665 struct dcn21_resource_pool *pool)
1666 {
1667 int i, j;
1668 struct dc_context *ctx = dc->ctx;
1669 struct irq_service_init_data init_data;
1670 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1671 uint32_t num_pipes;
1672
1673 ctx->dc_bios->regs = &bios_regs;
1674
1675 pool->base.res_cap = &res_cap_rn;
1676 #ifdef DIAGS_BUILD
1677 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1678 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1679 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1680 #endif
1681
1682 pool->base.funcs = &dcn21_res_pool_funcs;
1683
1684 /*************************************************
1685 * Resource + asic cap harcoding *
1686 *************************************************/
1687 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1688
1689 /* max pipe num for ASIC before check pipe fuses */
1690 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1691
1692 dc->caps.max_downscale_ratio = 200;
1693 dc->caps.i2c_speed_in_khz = 100;
1694 dc->caps.max_cursor_size = 256;
1695 dc->caps.dmdata_alloc_size = 2048;
1696 dc->caps.hw_3d_lut = true;
1697
1698 dc->caps.max_slave_planes = 1;
1699 dc->caps.post_blend_color_processing = true;
1700 dc->caps.force_dp_tps4_for_cp2520 = true;
1701 dc->caps.extended_aux_timeout_support = true;
1702 dc->caps.dmcub_support = true;
1703
1704 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1705 dc->debug = debug_defaults_drv;
1706 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1707 pool->base.pipe_count = 4;
1708 dc->debug = debug_defaults_diags;
1709 } else
1710 dc->debug = debug_defaults_diags;
1711
1712 // Init the vm_helper
1713 if (dc->vm_helper)
1714 vm_helper_init(dc->vm_helper, 16);
1715
1716 /*************************************************
1717 * Create resources *
1718 *************************************************/
1719
1720 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1721 dcn21_clock_source_create(ctx, ctx->dc_bios,
1722 CLOCK_SOURCE_COMBO_PHY_PLL0,
1723 &clk_src_regs[0], false);
1724 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1725 dcn21_clock_source_create(ctx, ctx->dc_bios,
1726 CLOCK_SOURCE_COMBO_PHY_PLL1,
1727 &clk_src_regs[1], false);
1728 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1729 dcn21_clock_source_create(ctx, ctx->dc_bios,
1730 CLOCK_SOURCE_COMBO_PHY_PLL2,
1731 &clk_src_regs[2], false);
1732
1733 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1734
1735 /* todo: not reuse phy_pll registers */
1736 pool->base.dp_clock_source =
1737 dcn21_clock_source_create(ctx, ctx->dc_bios,
1738 CLOCK_SOURCE_ID_DP_DTO,
1739 &clk_src_regs[0], true);
1740
1741 for (i = 0; i < pool->base.clk_src_count; i++) {
1742 if (pool->base.clock_sources[i] == NULL) {
1743 dm_error("DC: failed to create clock sources!\n");
1744 BREAK_TO_DEBUGGER();
1745 goto create_fail;
1746 }
1747 }
1748
1749 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1750 if (pool->base.dccg == NULL) {
1751 dm_error("DC: failed to create dccg!\n");
1752 BREAK_TO_DEBUGGER();
1753 goto create_fail;
1754 }
1755
1756 pool->base.dmcu = dcn21_dmcu_create(ctx,
1757 &dmcu_regs,
1758 &dmcu_shift,
1759 &dmcu_mask);
1760 if (pool->base.dmcu == NULL) {
1761 dm_error("DC: failed to create dmcu!\n");
1762 BREAK_TO_DEBUGGER();
1763 goto create_fail;
1764 }
1765
1766 // Leave as NULL to not affect current dmcu psr programming sequence
1767 // Will be uncommented when functionality is confirmed to be working
1768 pool->base.psr = NULL;
1769
1770 pool->base.abm = dce_abm_create(ctx,
1771 &abm_regs,
1772 &abm_shift,
1773 &abm_mask);
1774 if (pool->base.abm == NULL) {
1775 dm_error("DC: failed to create abm!\n");
1776 BREAK_TO_DEBUGGER();
1777 goto create_fail;
1778 }
1779
1780 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1781
1782 num_pipes = dcn2_1_ip.max_num_dpp;
1783
1784 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1785 if (pipe_fuses & 1 << i)
1786 num_pipes--;
1787 dcn2_1_ip.max_num_dpp = num_pipes;
1788 dcn2_1_ip.max_num_otg = num_pipes;
1789
1790 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1791
1792 init_data.ctx = dc->ctx;
1793 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1794 if (!pool->base.irqs)
1795 goto create_fail;
1796
1797 j = 0;
1798 /* mem input -> ipp -> dpp -> opp -> TG */
1799 for (i = 0; i < pool->base.pipe_count; i++) {
1800 /* if pipe is disabled, skip instance of HW pipe,
1801 * i.e, skip ASIC register instance
1802 */
1803 if ((pipe_fuses & (1 << i)) != 0)
1804 continue;
1805
1806 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1807 if (pool->base.hubps[j] == NULL) {
1808 BREAK_TO_DEBUGGER();
1809 dm_error(
1810 "DC: failed to create memory input!\n");
1811 goto create_fail;
1812 }
1813
1814 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1815 if (pool->base.ipps[j] == NULL) {
1816 BREAK_TO_DEBUGGER();
1817 dm_error(
1818 "DC: failed to create input pixel processor!\n");
1819 goto create_fail;
1820 }
1821
1822 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1823 if (pool->base.dpps[j] == NULL) {
1824 BREAK_TO_DEBUGGER();
1825 dm_error(
1826 "DC: failed to create dpps!\n");
1827 goto create_fail;
1828 }
1829
1830 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1831 if (pool->base.opps[j] == NULL) {
1832 BREAK_TO_DEBUGGER();
1833 dm_error(
1834 "DC: failed to create output pixel processor!\n");
1835 goto create_fail;
1836 }
1837
1838 pool->base.timing_generators[j] = dcn21_timing_generator_create(
1839 ctx, i);
1840 if (pool->base.timing_generators[j] == NULL) {
1841 BREAK_TO_DEBUGGER();
1842 dm_error("DC: failed to create tg!\n");
1843 goto create_fail;
1844 }
1845 j++;
1846 }
1847
1848 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1849 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1850 if (pool->base.engines[i] == NULL) {
1851 BREAK_TO_DEBUGGER();
1852 dm_error(
1853 "DC:failed to create aux engine!!\n");
1854 goto create_fail;
1855 }
1856 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1857 if (pool->base.hw_i2cs[i] == NULL) {
1858 BREAK_TO_DEBUGGER();
1859 dm_error(
1860 "DC:failed to create hw i2c!!\n");
1861 goto create_fail;
1862 }
1863 pool->base.sw_i2cs[i] = NULL;
1864 }
1865
1866 pool->base.timing_generator_count = j;
1867 pool->base.pipe_count = j;
1868 pool->base.mpcc_count = j;
1869
1870 pool->base.mpc = dcn21_mpc_create(ctx);
1871 if (pool->base.mpc == NULL) {
1872 BREAK_TO_DEBUGGER();
1873 dm_error("DC: failed to create mpc!\n");
1874 goto create_fail;
1875 }
1876
1877 pool->base.hubbub = dcn21_hubbub_create(ctx);
1878 if (pool->base.hubbub == NULL) {
1879 BREAK_TO_DEBUGGER();
1880 dm_error("DC: failed to create hubbub!\n");
1881 goto create_fail;
1882 }
1883
1884 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1885 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1886 if (pool->base.dscs[i] == NULL) {
1887 BREAK_TO_DEBUGGER();
1888 dm_error("DC: failed to create display stream compressor %d!\n", i);
1889 goto create_fail;
1890 }
1891 }
1892
1893 if (!dcn20_dwbc_create(ctx, &pool->base)) {
1894 BREAK_TO_DEBUGGER();
1895 dm_error("DC: failed to create dwbc!\n");
1896 goto create_fail;
1897 }
1898 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1899 BREAK_TO_DEBUGGER();
1900 dm_error("DC: failed to create mcif_wb!\n");
1901 goto create_fail;
1902 }
1903
1904 if (!resource_construct(num_virtual_links, dc, &pool->base,
1905 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1906 &res_create_funcs : &res_create_maximus_funcs)))
1907 goto create_fail;
1908
1909 dcn21_hw_sequencer_construct(dc);
1910
1911 dc->caps.max_planes = pool->base.pipe_count;
1912
1913 for (i = 0; i < dc->caps.max_planes; ++i)
1914 dc->caps.planes[i] = plane_cap;
1915
1916 dc->cap_funcs = cap_funcs;
1917
1918 return true;
1919
1920 create_fail:
1921
1922 dcn21_resource_destruct(pool);
1923
1924 return false;
1925 }
1926
dcn21_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1927 struct resource_pool *dcn21_create_resource_pool(
1928 const struct dc_init_data *init_data,
1929 struct dc *dc)
1930 {
1931 struct dcn21_resource_pool *pool =
1932 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
1933
1934 if (!pool)
1935 return NULL;
1936
1937 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
1938 return &pool->base;
1939
1940 BREAK_TO_DEBUGGER();
1941 kfree(pool);
1942 return NULL;
1943 }
1944