1 /* $NetBSD: amdgpu_dcn20_vmid.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn20_vmid.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $");
30
31 #include <linux/delay.h>
32
33 #include "dcn20_vmid.h"
34 #include "reg_helper.h"
35
36 #define REG(reg)\
37 vmid->regs->reg
38
39 #define CTX \
40 vmid->ctx
41
42 #undef FN
43 #define FN(reg_name, field_name) \
44 vmid->shifts->field_name, vmid->masks->field_name
45
dcn20_wait_for_vmid_ready(struct dcn20_vmid * vmid)46 static void dcn20_wait_for_vmid_ready(struct dcn20_vmid *vmid)
47 {
48 /* According the hardware spec, we need to poll for the lowest
49 * bit of PAGE_TABLE_BASE_ADDR_LO32 = 1 any time a GPUVM
50 * context is updated. We can't use REG_WAIT here since we
51 * don't have a seperate field to wait on.
52 *
53 * TODO: Confirm timeout / poll interval with hardware team
54 */
55
56 int max_times = 10000;
57 int delay_us = 5;
58 int i;
59
60 for (i = 0; i < max_times; ++i) {
61 uint32_t entry_lo32;
62
63 REG_GET(PAGE_TABLE_BASE_ADDR_LO32,
64 VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32,
65 &entry_lo32);
66
67 if (entry_lo32 & 0x1)
68 return;
69
70 udelay(delay_us);
71 }
72
73 /* VM setup timed out */
74 DC_LOG_WARNING("Timeout while waiting for GPUVM context update\n");
75 ASSERT(0);
76 }
77
dcn20_vmid_setup(struct dcn20_vmid * vmid,const struct dcn_vmid_page_table_config * config)78 void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config)
79 {
80 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0,
81 VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, (config->page_table_start_addr >> 32) & 0xF);
82 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0,
83 VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, config->page_table_start_addr & 0xFFFFFFFF);
84
85 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0,
86 VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, (config->page_table_end_addr >> 32) & 0xF);
87 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0,
88 VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, config->page_table_end_addr & 0xFFFFFFFF);
89
90 REG_SET_2(CNTL, 0,
91 VM_CONTEXT0_PAGE_TABLE_DEPTH, config->depth,
92 VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, config->block_size);
93
94 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0,
95 VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, (config->page_table_base_addr >> 32) & 0xFFFFFFFF);
96 /* Note: per hardware spec PAGE_TABLE_BASE_ADDR_LO32 must be programmed last in sequence */
97 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0,
98 VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, config->page_table_base_addr & 0xFFFFFFFF);
99
100 dcn20_wait_for_vmid_ready(vmid);
101 }
102