1 /* $NetBSD: amdgpu_athub_v2_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_athub_v2_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
28
29 #include "amdgpu.h"
30 #include "athub_v2_0.h"
31
32 #include "athub/athub_2_0_0_offset.h"
33 #include "athub/athub_2_0_0_sh_mask.h"
34 #include "athub/athub_2_0_0_default.h"
35 #include "navi10_enum.h"
36
37 #include "soc15_common.h"
38
39 static void
athub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)40 athub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
41 bool enable)
42 {
43 uint32_t def, data;
44
45 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
46
47 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
48 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
49 else
50 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
51
52 if (def != data)
53 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
54 }
55
56 static void
athub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)57 athub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
58 bool enable)
59 {
60 uint32_t def, data;
61
62 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
63
64 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
65 (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
66 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
67 else
68 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
69
70 if (def != data)
71 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
72 }
73
athub_v2_0_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)74 int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
75 enum amd_clockgating_state state)
76 {
77 if (amdgpu_sriov_vf(adev))
78 return 0;
79
80 switch (adev->asic_type) {
81 case CHIP_NAVI10:
82 case CHIP_NAVI14:
83 case CHIP_NAVI12:
84 athub_v2_0_update_medium_grain_clock_gating(adev,
85 state == AMD_CG_STATE_GATE);
86 athub_v2_0_update_medium_grain_light_sleep(adev,
87 state == AMD_CG_STATE_GATE);
88 break;
89 default:
90 break;
91 }
92
93 return 0;
94 }
95
athub_v2_0_get_clockgating(struct amdgpu_device * adev,u32 * flags)96 void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
97 {
98 int data;
99
100 /* AMD_CG_SUPPORT_ATHUB_MGCG */
101 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
102 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
103 *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
104
105 /* AMD_CG_SUPPORT_ATHUB_LS */
106 if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
107 *flags |= AMD_CG_SUPPORT_ATHUB_LS;
108 }
109