1 /* $NetBSD: sioreg.h,v 1.3 2021/06/25 13:32:39 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 BBN Corporation. 5 * BBN Systems and Technologies Division 6 * 10 Moulton Street 7 * Cambridge, Ma. 02138 8 * 617-873-3000 9 * 10 * Permission to use, copy, modify, distribute, and sell this software and its 11 * documentation for any purpose is hereby granted without fee, provided that 12 * the above copyright notice and this permission appear in all copies and in 13 * supporting documentation, and that the name of BBN Corporation not be used 14 * in advertising or publicity pertaining to distribution of the software 15 * without specific, written prior permission. BBN makes no representations 16 * about the suitability of this software for any purposes. It is provided 17 * "AS IS" without express or implied warranties. 18 */ 19 20 /* 21 * Intel 82378 System I/O (SIO) Chip 22 * 23 * Taken from the Intel "Peripheral Components" manual, 1995 Edition. 24 */ 25 26 27 /* 28 * Device-specific PCI Configuration Registers 29 */ 30 31 /* 32 * PCI Control Registers 33 */ 34 #define SIO_PCIREG_PCICON 0x40 /* PCI Control */ 35 #define SIO_PCIREG_PAC 0x41 /* PCI Arbiter Control */ 36 #define SIO_PCIREG_PAPC 0x42 /* PCI Arbiter Priority Control */ 37 #define SIO_PCIREG_ARBPRIX 0x43 /* PCI Arbiter Priority Control Ext. */ 38 39 /* 40 * Memory Chip Select Registers 41 */ 42 #define SIO_PCIREG_MEMCSCON 0x44 /* MEMCS# Control */ 43 #define SIO_PCIREG_MEMCSBOH 0x45 /* MEMCS# Bottom of Hole */ 44 #define SIO_PCIREG_MEMCSTOH 0x46 /* MEMCS# Top of Hole */ 45 #define SIO_PCIREG_MEMCSTOM 0x47 /* MEMCS# Top of Memory */ 46 47 #define SIO_PCIREG_MAR1 0x54 /* MEMCS# Attribute 1 */ 48 #define SIO_PCIREG_MAR2 0x55 /* MEMCS# Attribute 2 */ 49 #define SIO_PCIREG_MAR3 0x56 /* MEMCS# Attribute 3 */ 50 #define SIO_PCIREG_DMASGRB 0x57 /* DMA Scatter/Gather Rel. Base Addr. */ 51 52 /* 53 * ISA Address Decoder Registers 54 */ 55 #define SIO_PCIREG_IADCON 0x48 /* ISA Address Decoder Control */ 56 #define SIO_PCIREG_IADRBE 0x49 /* ISA Addr. Decoder ROM Block Enable */ 57 #define SIO_PCIREG_IADBOH 0x4A /* ISA Addr. Decoder Bottom of Hole */ 58 #define SIO_PCIREG_IADTOH 0x4B /* ISA Addr. Decoder Top of Hole */ 59 60 /* 61 * Clocks and Timers 62 */ 63 #define SIO_PCIREG_ICRT 0x4C /* ISA Controller Recovery Timer */ 64 #define SIO_PCIREG_ICD 0x4D /* ISA Clock Divisor */ 65 66 #define SIO_PCIREG_ 0x80 /* BIOS Timer Base Address */ 67 68 #define SIO_PCIREG_CTLTMRL 0xAC /* Clock Throttle STPCLK# Low Timer */ 69 #define SIO_PCIREG_CTLTMRH 0xAE /* Clock Throttle STPCLK# High Timer */ 70 71 /* 72 * Miscellaneous 73 */ 74 #define SIO_PCIREG_UBCSA 0x4E /* Utility Bus Chip Select A */ 75 #define SIO_PCIREG_UBCSB 0x4F /* Utility Bus Chip Select B */ 76 77 /* 78 * PIRQ# Route Control 79 */ 80 #define SIO_PCIREG_PIRQ0 0x60 /* PIRQ0 Route Control */ 81 #define SIO_PCIREG_PIRQ1 0x61 /* PIRQ1 Route Control */ 82 #define SIO_PCIREG_PIRQ2 0x62 /* PIRQ2 Route Control */ 83 #define SIO_PCIREG_PIRQ3 0x63 /* PIRQ3 Route Control */ 84 #define SIO_PCIREG_PIRQ_RTCTRL SIO_PCIREG_PIRQ0 85 86 /* extract the PIRQx field from 32-bit reg */ 87 #define PIRQ_RTCTRL_PIRQx(r, p) (((r) >> ((p) * 8)) & 0xff) 88 89 /* bits within each PIRQx field */ 90 #define PIRQ_RTCTRL_NOT_ROUTED __BIT(7) /* 0 == interrupt routed */ 91 #define PIRQ_RTCTRL_IRQ __BITS(0,3) /* PIRQ routed to this ISA IRQ */ 92 93 /* 94 * System Management Interrupt (SMI) 95 */ 96 #define SIO_PCIREG_SMICNTL 0xA0 /* SMI Control */ 97 #define SIO_PCIREG_SMIEN 0xA2 /* SMI Enable */ 98 #define SIO_PCIREG_SEE 0xA4 /* System Event Enable */ 99 #define SIO_PCIREG_FTMR 0xA8 /* Fast Off Timer */ 100 #define SIO_PCIREG_SMIREQ 0xAA /* SMI Request */ 101 102 103 /* 104 * Non-Configuration Registers 105 */ 106 107 /* 108 * Control 109 */ 110 #define SIO_REG_RSTUB 0x060 /* Reset UBus */ 111 #define SIO_REG_NMICTRL 0x061 /* NMI Status and Control */ 112 #define SIO_REG_CMOSRAM 0x070 /* CMOS RAM Address and NMI Mask */ 113 #define SIO_REG_NMIMASK 0x070 /* CMOS RAM Address and NMI Mask */ 114 #define SIO_REG_PORT92 0x092 /* Port 92 */ 115 #define SIO_REG_CPERR 0x0F0 /* Coprocessor Error */ 116 117 /* 118 * Interrupt 119 */ 120 #define SIO_REG_ICU1 0x020 /* Intr. Controller #1 Control */ 121 #define SIO_REG_ICU1MASK 0x021 /* Intr. Controller #1 Mask */ 122 #define SIO_REG_ICU2 0x0A0 /* Intr. Controller #2 Control */ 123 #define SIO_REG_ICU2MASK 0x0A1 /* Intr. Controller #2 Mask */ 124 #define SIO_REG_ICU1ELC 0x4D0 /* #1's Edge/Level Control */ 125 #define SIO_REG_ICU2ELC 0x4D1 /* #2's Edge/Level Control */ 126 #define SIO_ICUSIZE 16 /* I/O Port Sizes */ 127 128 /* 129 * Timer 130 */ 131 /* XXX need Timer definitions */ 132 133 /* 134 * DMA 135 */ 136 /* XXX need DMA definitions */ 137