1 /* $NetBSD: aereg.h,v 1.3 2021/08/02 12:56:23 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _MIPS_ATHEROS_DEV_AEREG_H_ 34 #define _MIPS_ATHEROS_DEV_AEREG_H_ 35 36 /* 37 * This device is much like a standard Tulip Ethernet chip, but it is 38 * an on-chip core on the AR5312 processors. It differs in having two 39 * register windows, and the details of some of the contents of those 40 * registers. It has about 80% in common to a typical tulip. 41 */ 42 43 /* 44 * Buffer descriptor. Must be 4-byte aligned. 45 * 46 * Note for receive descriptors, the byte count fields must 47 * be a multiple of 4. 48 */ 49 struct ae_desc { 50 volatile u_int32_t ad_status; /* Status */ 51 volatile u_int32_t ad_ctl; /* Control and Byte Counts */ 52 volatile u_int32_t ad_bufaddr1; /* Buffer Address 1 */ 53 volatile u_int32_t ad_bufaddr2; /* Buffer Address 2 */ 54 }; 55 56 /* 57 * Descriptor Status bits common to transmit and receive. 58 */ 59 #define ADSTAT_OWN 0x80000000 /* Tulip owns descriptor */ 60 #define ADSTAT_ES 0x00008000 /* Error Summary */ 61 62 /* 63 * Descriptor Status bits for Receive Descriptor. 64 */ 65 #define ADSTAT_Rx_FF 0x40000000 /* Filtering Fail */ 66 #define ADSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ 67 #define ADSTAT_Rx_DE 0x00004000 /* Descriptor Error */ 68 #define ADSTAT_Rx_LE 0x00001000 /* Length Error */ 69 #define ADSTAT_Rx_RF 0x00000800 /* Runt Frame */ 70 #define ADSTAT_Rx_MF 0x00000400 /* Multicast Frame */ 71 #define ADSTAT_Rx_FS 0x00000200 /* First Descriptor */ 72 #define ADSTAT_Rx_LS 0x00000100 /* Last Descriptor */ 73 #define ADSTAT_Rx_TL 0x00000080 /* Frame Too Long */ 74 #define ADSTAT_Rx_CS 0x00000040 /* Collision Seen */ 75 #define ADSTAT_Rx_RT 0x00000020 /* Frame Type */ 76 #define ADSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ 77 #define ADSTAT_Rx_RE 0x00000008 /* Report on MII Error */ 78 #define ADSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ 79 #define ADSTAT_Rx_CE 0x00000002 /* CRC Error */ 80 #define ADSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ 81 82 #define ADSTAT_Rx_LENGTH(x) (((x) & ADSTAT_Rx_FL) >> 16) 83 84 /* 85 * Descriptor Status bits for Transmit Descriptor. 86 */ 87 #define ADSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ 88 #define ADSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ 89 #define ADSTAT_Tx_NC 0x00000400 /* No Carrier */ 90 #define ADSTAT_Tx_LC 0x00000200 /* Late Collision */ 91 #define ADSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ 92 #define ADSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ 93 #define ADSTAT_Tx_CC 0x00000078 /* Collision Count */ 94 #define ADSTAT_Tx_ED 0x00000004 /* Excessive Deferral */ 95 #define ADSTAT_Tx_UF 0x00000002 /* Underflow Error */ 96 #define ADSTAT_Tx_DE 0x00000001 /* Deferred */ 97 98 #define ADSTAT_Tx_COLLISIONS(x) (((x) & ADSTAT_Tx_CC) >> 3) 99 100 /* 101 * Descriptor Control bits common to transmit and receive. 102 */ 103 #define ADCTL_SIZE1 0x000007ff /* Size of buffer 1 */ 104 #define ADCTL_SIZE1_SHIFT 0 105 106 #define ADCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ 107 #define ADCTL_SIZE2_SHIFT 11 108 109 #define ADCTL_ER 0x02000000 /* End of Ring */ 110 #define ADCTL_CH 0x01000000 /* Second Address Chained */ 111 112 /* 113 * Descriptor Control bits for Transmit Descriptor. 114 */ 115 #define ADCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ 116 #define ADCTL_Tx_LS 0x40000000 /* Last Segment */ 117 #define ADCTL_Tx_FS 0x20000000 /* First Segment */ 118 #define ADCTL_Tx_AC 0x04000000 /* Add CRC Disable */ 119 #define ADCTL_Tx_DPD 0x00800000 /* Disabled Padding */ 120 121 /* 122 * Control registers. 123 */ 124 125 /* these are registers only found on this part */ 126 #define CSR_MACCTL 0x0000 /* mac control */ 127 #define CSR_MACHI 0x0004 128 #define CSR_MACLO 0x0008 129 #define CSR_HTHI 0x000C /* multicast table high */ 130 #define CSR_HTLO 0x0010 /* multicast table low */ 131 #define CSR_MIIADDR 0x0014 /* mii address */ 132 #define CSR_MIIDATA 0x0018 /* mii data */ 133 #define CSR_FLOWC 0x001C /* flow control */ 134 #define CSR_VL1 0x0020 /* vlan 1 tag */ 135 136 /* these are more or less normal Tulip registers */ 137 #define CSR_BUSMODE 0x1000 /* bus mode */ 138 #define CSR_TXPOLL 0x1004 /* tx poll demand */ 139 #define CSR_RXPOLL 0x1008 /* rx poll demand */ 140 #define CSR_RXLIST 0x100C /* rx base descriptor address */ 141 #define CSR_TXLIST 0x1010 /* tx base descriptor address */ 142 #define CSR_STATUS 0x1014 /* (interrupt) status */ 143 #define CSR_OPMODE 0x1018 /* operation mode */ 144 #define CSR_INTEN 0x101C /* interrupt enable */ 145 #define CSR_MISSED 0x1020 /* missed frame counter */ 146 #define CSR_HTBA 0x1050 /* host tx buffer address (ro) */ 147 #define CSR_HRBA 0x1054 /* host rx buffer address (ro) */ 148 149 /* CSR_MACCTL - Mac Control */ 150 #define MACCTL_RE 0x00000004 /* rx enable */ 151 #define MACCTL_TE 0x00000008 /* tx enable */ 152 #define MACCTL_DC 0x00000020 /* deferral check */ 153 #define MACCTL_PSTR 0x00000100 /* automatic pad strip */ 154 #define MACCTL_DTRY 0x00000400 /* disable retry */ 155 #define MACCTL_DBF 0x00000800 /* disable broadcast frames */ 156 #define MACCTL_LCC 0x00001000 /* late collision control */ 157 #define MACCTL_HASH 0x00002000 /* hash filtering enable */ 158 #define MACCTL_HO 0x00008000 /* disable perfect filtering */ 159 #define MACCTL_PB 0x00010000 /* pass bad frames */ 160 #define MACCTL_IF 0x00020000 /* inverse filtering */ 161 #define MACCTL_PR 0x00040000 /* promiscuous mode */ 162 #define MACCTL_PM 0x00080000 /* pass all multicast */ 163 #define MACCTL_FDX 0x00100000 /* full duplex mode */ 164 #define MACCTL_LOOP 0x00600000 /* loopback mask */ 165 #define MACCTL_LOOP_INT 0x00200000 /* internal loopback */ 166 #define MACCTL_LOOP_EXT 0x00400000 /* external loopback */ 167 #define MACCTL_LOOP_NONE 0x00000000 168 #define MACCTL_DRO 0x00800000 /* disable receive own */ 169 #define MACCTL_PS 0x08000000 /* port select, 0 = mii */ 170 #define MACCTL_HBD 0x10000000 /* heartbeat disable */ 171 #define MACCTL_BLE 0x40000000 /* mac big endian */ 172 #define MACCTL_RA 0x80000000 /* receive all packets */ 173 174 /* CSR_MIIADDR - MII Address */ 175 #define MIIADDR_BUSY 0x00000001 /* mii busy */ 176 #define MIIADDR_WRITE 0x00000002 /* mii write */ 177 #define MIIADDR_REG_MASK 0x000007C0 /* mii register */ 178 #define MIIADDR_REG_SHIFT 6 179 #define MIIADDR_PHY_MASK 0x0000F800 /* mii phy */ 180 #define MIIADDR_PHY_SHIFT 11 181 182 #define MIIADDR_GETREG(x) (((x) & MIIADDR_REG) >> 6) 183 #define MIIADDR_PUTREG(x) (((x) << 6) & MIIADR_REG) 184 #define MIIADDR_GETPHY(x) (((x) & MIIADDR_PHY) >> 11) 185 #define MIIADDR_PUTPHY(x) (((x) << 6) & MIIADR_PHY) 186 187 /* CSR_FLOWC - Flow Control */ 188 #define FLOWC_FCB 0x00000001 /* flow control busy */ 189 #define FLOWC_FCE 0x00000002 /* flow control enable */ 190 #define FLOWC_PCF 0x00000004 /* pass control frames */ 191 #define FLOWC_PT 0xffff0000 /* pause time */ 192 193 /* CSR_BUSMODE - Bus Mode */ 194 #define BUSMODE_SWR 0x00000001 /* software reset */ 195 #define BUSMODE_BAR 0x00000002 /* bus arbitration */ 196 #define BUSMODE_DSL 0x0000007c /* descriptor skip length */ 197 #define BUSMODE_BLE 0x00000080 /* data buf endian */ 198 /* programmable burst length */ 199 #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ 200 #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ 201 #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ 202 #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ 203 #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ 204 #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ 205 #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ 206 #define BUSMODE_DBO 0x00100000 /* descriptor endian */ 207 #define BUSMODE_ALIGN_16B 0x01000000 /* force oddhw rx buf align */ 208 209 /* CSR_TXPOLL - Transmit Poll Demand */ 210 #define TXPOLL_TPD 0x00000001 /* transmit poll demand */ 211 212 213 /* CSR_RXPOLL - Receive Poll Demand */ 214 #define RXPOLL_RPD 0x00000001 /* receive poll demand */ 215 216 /* CSR_STATUS - Status */ 217 #define STATUS_TI 0x00000001 /* transmit interrupt */ 218 #define STATUS_TPS 0x00000002 /* transmit process stopped */ 219 #define STATUS_TU 0x00000004 /* transmit buffer unavail */ 220 #define STATUS_TJT 0x00000008 /* transmit jabber timeout */ 221 #define STATUS_UNF 0x00000020 /* transmit underflow */ 222 #define STATUS_RI 0x00000040 /* receive interrupt */ 223 #define STATUS_RU 0x00000080 /* receive buffer unavail */ 224 #define STATUS_RPS 0x00000100 /* receive process stopped */ 225 #define STATUS_ETI 0x00000400 /* early transmit interrupt */ 226 #define STATUS_SE 0x00002000 /* system error */ 227 #define STATUS_ER 0x00004000 /* early receive (21041) */ 228 #define STATUS_AIS 0x00008000 /* abnormal intr summary */ 229 #define STATUS_NIS 0x00010000 /* normal interrupt summary */ 230 #define STATUS_RS 0x000e0000 /* receive process state */ 231 #define STATUS_RS_STOPPED 0x00000000 /* Stopped */ 232 #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive 233 descriptor */ 234 #define STATUS_RS_CHECK 0x00040000 /* Running - check for end 235 of receive */ 236 #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ 237 #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ 238 #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive 239 descriptor */ 240 #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current 241 frame from FIFO */ 242 #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current 243 frame from FIFO into 244 buffer */ 245 #define STATUS_TS 0x00700000 /* transmit process state */ 246 #define STATUS_TS_STOPPED 0x00000000 /* Stopped */ 247 #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit 248 descriptor */ 249 #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end 250 of transmission */ 251 #define STATUS_TS_READING 0x00300000 /* Running - read buffer from 252 memory and queue into 253 FIFO */ 254 #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ 255 #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit 256 descriptor */ 257 #define STATUS_TX_ABORT 0x00800000 /* Transmit bus abort */ 258 #define STATUS_RX_ABORT 0x01000000 /* Transmit bus abort */ 259 260 /* CSR_OPMODE - Operation Mode */ 261 #define OPMODE_SR 0x00000002 /* start receive */ 262 #define OPMODE_OSF 0x00000004 /* operate on second frame */ 263 #define OPMODE_ST 0x00002000 /* start transmitter */ 264 #define OPMODE_TR 0x0000c000 /* threshold control */ 265 #define OPMODE_TR_32 0x00000000 /* 32 words */ 266 #define OPMODE_TR_64 0x00004000 /* 64 words */ 267 #define OPMODE_TR_128 0x00008000 /* 128 words */ 268 #define OPMODE_TR_256 0x0000c000 /* 256 words */ 269 #define OPMODE_SF 0x00200000 /* store and forward mode */ 270 271 /* CSR_INTEN - Interrupt Enable */ 272 /* See bits for CSR_STATUS -- Status */ 273 274 275 /* CSR_MISSED - Missed Frames */ 276 #define MISSED_MFC 0xffff0000 /* missed packet count */ 277 #define MISSED_FOC 0x0000ffff /* fifo overflow counter */ 278 279 #define MISSED_GETMFC(x) ((x) & MISSED_MFC) 280 #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 16) 281 282 #endif /* _MIPS_ATHEROS_DEV_AEREG_H_ */ 283