1 /* $NetBSD: adm5120_intr.c,v 1.9 2021/01/04 18:11:26 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or
8 * without modification, are permitted provided that the following
9 * conditions are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above
13 * copyright notice, this list of conditions and the following
14 * disclaimer in the documentation and/or other materials provided
15 * with the distribution.
16 * 3. The names of the authors may not be used to endorse or promote
17 * products derived from this software without specific prior
18 * written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
31 * OF SUCH DAMAGE.
32 */
33 /*-
34 * Copyright (c) 2001 The NetBSD Foundation, Inc.
35 * All rights reserved.
36 *
37 * This code is derived from software contributed to The NetBSD Foundation
38 * by Jason R. Thorpe.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in the
47 * documentation and/or other materials provided with the distribution.
48 *
49 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
50 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
59 * POSSIBILITY OF SUCH DAMAGE.
60 */
61
62 /*
63 * Platform-specific interrupt support for the Alchemy Semiconductor Pb1000.
64 *
65 * The Alchemy Semiconductor Pb1000's interrupts are wired to two internal
66 * interrupt controllers.
67 */
68
69 #include <sys/cdefs.h>
70 __KERNEL_RCSID(0, "$NetBSD: adm5120_intr.c,v 1.9 2021/01/04 18:11:26 thorpej Exp $");
71
72 #include "opt_ddb.h"
73 #define __INTR_PRIVATE
74
75 #include <sys/param.h>
76 #include <sys/intr.h>
77 #include <sys/kmem.h>
78
79 #include <mips/locore.h>
80 #include <mips/adm5120/include/adm5120reg.h>
81 #include <mips/adm5120/include/adm5120var.h>
82
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
85
86 /*
87 * This is a mask of bits to clear in the SR when we go to a
88 * given hardware interrupt priority level.
89 */
90 static const struct ipl_sr_map adm5120_ipl_sr_map = {
91 .sr_bits = {
92 [IPL_NONE] = 0,
93 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
94 [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
95 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
96 [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
97 [IPL_VM] = MIPS_SOFT_INT_MASK|MIPS_INT_MASK_0,
98 [IPL_SCHED] = MIPS_INT_MASK,
99 [IPL_HIGH] = MIPS_INT_MASK,
100 },
101 };
102
103 #define NIRQS 32
104 const char * const adm5120_intrnames[NIRQS] = {
105 "timer", /* 0 */
106 "uart0", /* 1 */
107 "uart1", /* 2 */
108 "usb", /* 3 */
109 "intx0/gpio2", /* 4 */
110 "intx1/gpio4", /* 5 */
111 "pci0", /* 6 */
112 "pci1", /* 7 */
113 "pci2", /* 8 */
114 "switch",/* 9 */
115 "res10", /* 10 */
116 "res11", /* 11 */
117 "res12", /* 12 */
118 "res13", /* 13 */
119 "res14", /* 14 */
120 "res15", /* 15 */
121 "res16", /* 16 */
122 "res17", /* 17 */
123 "res18", /* 18 */
124 "res19", /* 19 */
125 "res20", /* 20 */
126 "res21", /* 21 */
127 "res22", /* 22 */
128 "res23", /* 23 */
129 "res24", /* 24 */
130 "res25", /* 25 */
131 "res26", /* 26 */
132 "res27", /* 27 */
133 "res28", /* 28 */
134 "res29", /* 29 */
135 "res30", /* 30 */
136 "res31", /* 31 */
137 };
138
139 struct adm5120_intrhead {
140 struct evcnt intr_count;
141 int intr_refcnt;
142 };
143 struct adm5120_intrhead adm5120_intrtab[NIRQS];
144
145
146 #define NINTRS 2 /* MIPS INT0 - INT1 */
147 struct adm5120_cpuintr {
148 LIST_HEAD(, evbmips_intrhand) cintr_list;
149 struct evcnt cintr_count;
150 };
151 struct adm5120_cpuintr adm5120_cpuintrs[NINTRS];
152
153 const char * const adm5120_cpuintrnames[NINTRS] = {
154 "int 0 (irq)",
155 "int 1 (fiq)",
156 };
157
158 #define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o)))
159 #define REG_WRITE(o,v) (REG_READ(o)) = (v)
160
161 void
evbmips_intr_init(void)162 evbmips_intr_init(void)
163 {
164 ipl_sr_map = adm5120_ipl_sr_map;
165
166 for (size_t i = 0; i < NINTRS; i++) {
167 LIST_INIT(&adm5120_cpuintrs[i].cintr_list);
168 evcnt_attach_dynamic(&adm5120_cpuintrs[i].cintr_count,
169 EVCNT_TYPE_INTR, NULL, "mips", adm5120_cpuintrnames[i]);
170 }
171
172 for (size_t i = 0; i < NIRQS; i++) {
173 /* XXX steering - use an irqmap array? */
174
175 adm5120_intrtab[i].intr_refcnt = 0;
176 evcnt_attach_dynamic(&adm5120_intrtab[i].intr_count,
177 EVCNT_TYPE_INTR, NULL, "adm5120", adm5120_intrnames[i]);
178 }
179
180 /* disable all interrupts */
181 REG_WRITE(ICU_DISABLE_REG, ICU_INT_MASK);
182 }
183
184 void *
adm5120_intr_establish(int irq,int priority,int (* func)(void *),void * arg)185 adm5120_intr_establish(int irq, int priority, int (*func)(void *), void *arg)
186 {
187 struct evbmips_intrhand *ih;
188 uint32_t irqmask;
189 int cpu_int, s;
190
191 if (irq < 0 || irq >= NIRQS)
192 panic("adm5120_intr_establish: bogus IRQ %d", irq);
193
194 ih = kmem_alloc(sizeof(*ih), KM_SLEEP);
195 ih->ih_func = func;
196 ih->ih_arg = arg;
197 ih->ih_irq = irq;
198
199 s = splhigh();
200
201 /*
202 * First, link it into the tables.
203 * XXX do we want a separate list (really, should only be one item, not
204 * a list anyway) per irq, not per CPU interrupt?
205 */
206
207 cpu_int = (priority == INTR_FIQ) ? 1 : 0;
208
209 LIST_INSERT_HEAD(&adm5120_cpuintrs[cpu_int].cintr_list, ih, ih_q);
210
211 /*
212 * Now enable it.
213 */
214 if (adm5120_intrtab[irq].intr_refcnt++ == 0) {
215 irqmask = 1 << irq;
216
217 /* configure as IRQ or FIQ */
218 if (priority == INTR_FIQ) {
219 REG_WRITE(ICU_MODE_REG,
220 REG_READ(ICU_MODE_REG) | irqmask);
221 } else {
222 REG_WRITE(ICU_MODE_REG,
223 REG_READ(ICU_MODE_REG) & ~irqmask);
224 }
225 /* enable */
226 REG_WRITE(ICU_ENABLE_REG, irqmask);
227 }
228 splx(s);
229
230 return ih;
231 }
232
233 void
adm5120_intr_disestablish(void * cookie)234 adm5120_intr_disestablish(void *cookie)
235 {
236 struct evbmips_intrhand *ih = cookie;
237 int irq, s;
238 uint32_t irqmask;
239
240 irq = ih->ih_irq;
241
242 s = splhigh();
243
244 /*
245 * First, remove it from the table.
246 */
247 LIST_REMOVE(ih, ih_q);
248
249 /*
250 * Now, disable it, if there is nothing remaining on the
251 * list.
252 */
253 if (adm5120_intrtab[irq].intr_refcnt-- == 1) {
254 irqmask = 1 << irq; /* only used as a mask from here on */
255
256 /* disable this irq in HW */
257 REG_WRITE(ICU_DISABLE_REG, irqmask);
258 }
259
260 splx(s);
261
262 kmem_free(ih, sizeof(*ih));
263 }
264 void
evbmips_iointr(int ipl,uint32_t ipending,struct clockframe * cf)265 evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
266 {
267 struct evbmips_intrhand *ih;
268 uint32_t irqmask, irqstat;
269
270 for (int level = NINTRS - 1; level >= 0; level--) {
271 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
272 continue;
273
274 if (level)
275 irqstat = REG_READ(ICU_FIQ_STATUS_REG);
276 else
277 irqstat = REG_READ(ICU_STATUS_REG);
278
279 adm5120_cpuintrs[level].cintr_count.ev_count++;
280 LIST_FOREACH(ih, &adm5120_cpuintrs[level].cintr_list, ih_q) {
281 irqmask = 1 << ih->ih_irq;
282 if (irqmask & irqstat) {
283 adm5120_intrtab[ih->ih_irq].intr_count.ev_count++;
284 (*ih->ih_func)(ih->ih_arg);
285 }
286 }
287 }
288 }
289