1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2015-2018 Intel Corporation 3 */ 4 #ifndef ADF_TRANSPORT_ACCESS_MACROS_H 5 #define ADF_TRANSPORT_ACCESS_MACROS_H 6 7 #include <rte_io.h> 8 9 /* CSR write macro */ 10 #define ADF_CSR_WR(csrAddr, csrOffset, val) \ 11 rte_write32(val, (((uint8_t *)csrAddr) + csrOffset)) 12 #define ADF_CSR_WC_WR(csrAddr, csrOffset, val) \ 13 rte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset)) 14 15 /* CSR read macro */ 16 #define ADF_CSR_RD(csrAddr, csrOffset) \ 17 rte_read32((((uint8_t *)csrAddr) + csrOffset)) 18 19 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL 20 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL 21 #define ADF_RING_CSR_RING_CONFIG 0x000 22 #define ADF_RING_CSR_RING_LBASE 0x040 23 #define ADF_RING_CSR_RING_UBASE 0x080 24 #define ADF_RING_CSR_RING_HEAD 0x0C0 25 #define ADF_RING_CSR_RING_TAIL 0x100 26 #define ADF_RING_CSR_E_STAT 0x14C 27 #define ADF_RING_CSR_INT_SRCSEL 0x174 28 #define ADF_RING_CSR_INT_SRCSEL_2 0x178 29 #define ADF_RING_CSR_INT_COL_EN 0x17C 30 #define ADF_RING_CSR_INT_COL_CTL 0x180 31 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 32 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 33 #define ADF_RING_BUNDLE_SIZE 0x1000 34 #define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A 35 #define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05 36 #define ADF_COALESCING_MIN_TIME 0x1FF 37 #define ADF_COALESCING_MAX_TIME 0xFFFFF 38 #define ADF_COALESCING_DEF_TIME 0x27FF 39 #define ADF_RING_NEAR_WATERMARK_512 0x08 40 #define ADF_RING_NEAR_WATERMARK_0 0x00 41 #define ADF_RING_EMPTY_SIG 0x7F7F7F7F 42 #define ADF_RING_EMPTY_SIG_BYTE 0x7F 43 44 /* Valid internal ring size values */ 45 #define ADF_RING_SIZE_128 0x01 46 #define ADF_RING_SIZE_256 0x02 47 #define ADF_RING_SIZE_512 0x03 48 #define ADF_RING_SIZE_4K 0x06 49 #define ADF_RING_SIZE_16K 0x08 50 #define ADF_RING_SIZE_64K 0x0A 51 #define ADF_RING_SIZE_4M 0x10 52 #define ADF_MIN_RING_SIZE ADF_RING_SIZE_128 53 #define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M 54 #define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K 55 /* ARB CSR offset */ 56 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C 57 58 /* Maximum number of qps on a device for any service type */ 59 #define ADF_MAX_QPS_ON_ANY_SERVICE 4 60 #define ADF_RING_DIR_TX 0 61 #define ADF_RING_DIR_RX 1 62 63 /* Valid internal msg size values */ 64 #define ADF_MSG_SIZE_32 0x01 65 #define ADF_MSG_SIZE_64 0x02 66 #define ADF_MSG_SIZE_128 0x04 67 #define ADF_MIN_MSG_SIZE ADF_MSG_SIZE_32 68 #define ADF_MAX_MSG_SIZE ADF_MSG_SIZE_128 69 70 /* Size to bytes conversion macros for ring and msg size values */ 71 #define ADF_MSG_SIZE_TO_BYTES(SIZE) (SIZE << 5) 72 #define ADF_BYTES_TO_MSG_SIZE(SIZE) (SIZE >> 5) 73 #define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7) 74 #define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7) 75 76 /* Minimum ring buffer size for memory allocation */ 77 #define ADF_RING_SIZE_BYTES_MIN(SIZE) ((SIZE < ADF_RING_SIZE_4K) ? \ 78 ADF_RING_SIZE_4K : SIZE) 79 #define ADF_RING_SIZE_MODULO(SIZE) (SIZE + 0x6) 80 #define ADF_SIZE_TO_POW(SIZE) ((((SIZE & 0x4) >> 1) | ((SIZE & 0x4) >> 2) | \ 81 SIZE) & ~0x4) 82 /* Max outstanding requests */ 83 #define ADF_MAX_INFLIGHTS(RING_SIZE, MSG_SIZE) \ 84 ((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1) 85 #define BUILD_RING_CONFIG(size) \ 86 ((ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_FULL_WM) \ 87 | (ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_EMPTY_WM) \ 88 | size) 89 #define BUILD_RESP_RING_CONFIG(size, watermark_nf, watermark_ne) \ 90 ((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM) \ 91 | (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) \ 92 | size) 93 #define BUILD_RING_BASE_ADDR(addr, size) \ 94 ((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size)) 95 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 96 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 97 ADF_RING_CSR_RING_HEAD + (ring << 2)) 98 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 99 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 100 ADF_RING_CSR_RING_TAIL + (ring << 2)) 101 #define READ_CSR_E_STAT(csr_base_addr, bank) \ 102 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 103 ADF_RING_CSR_E_STAT) 104 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 105 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 106 ADF_RING_CSR_RING_CONFIG + (ring << 2), value) 107 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 108 do { \ 109 uint32_t l_base = 0, u_base = 0; \ 110 l_base = (uint32_t)(value & 0xFFFFFFFF); \ 111 u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \ 112 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 113 ADF_RING_CSR_RING_LBASE + (ring << 2), l_base); \ 114 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 115 ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \ 116 } while (0) 117 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 118 ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 119 ADF_RING_CSR_RING_HEAD + (ring << 2), value) 120 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 121 ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 122 ADF_RING_CSR_RING_TAIL + (ring << 2), value) 123 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 124 do { \ 125 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 126 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \ 127 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 128 ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \ 129 } while (0) 130 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 131 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 132 ADF_RING_CSR_INT_COL_EN, value) 133 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 134 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 135 ADF_RING_CSR_INT_COL_CTL, \ 136 ADF_RING_CSR_INT_COL_CTL_ENABLE | value) 137 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 138 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 139 ADF_RING_CSR_INT_FLAG_AND_COL, value) 140 141 #endif /*ADF_TRANSPORT_ACCESS_MACROS_H */ 142