xref: /llvm-project/llvm/test/CodeGen/SystemZ/addr-01.ll (revision a1710eb3cd5823c5d14899112ca3086acbdbe9cb) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; Test selection of addresses with indices in cases where the address
3; is used once.
4;
5; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
6
7; A simple index address.
8define void @f1(i64 %addr, i64 %index) {
9; CHECK-LABEL: f1:
10; CHECK:       # %bb.0:
11; CHECK-NEXT:    lb %r0, 0(%r3,%r2)
12; CHECK-NEXT:    br %r14
13  %add = add i64 %addr, %index
14  %ptr = inttoptr i64 %add to ptr
15  %a = load volatile i8, ptr %ptr
16  ret void
17}
18
19; An address with an index and a displacement (order 1).
20define void @f2(i64 %addr, i64 %index) {
21; CHECK-LABEL: f2:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    lb %r0, 100(%r3,%r2)
24; CHECK-NEXT:    br %r14
25  %add1 = add i64 %addr, %index
26  %add2 = add i64 %add1, 100
27  %ptr = inttoptr i64 %add2 to ptr
28  %a = load volatile i8, ptr %ptr
29  ret void
30}
31
32; An address with an index and a displacement (order 2).
33define void @f3(i64 %addr, i64 %index) {
34; CHECK-LABEL: f3:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    lb %r0, 100(%r3,%r2)
37; CHECK-NEXT:    br %r14
38  %add1 = add i64 %addr, 100
39  %add2 = add i64 %add1, %index
40  %ptr = inttoptr i64 %add2 to ptr
41  %a = load volatile i8, ptr %ptr
42  ret void
43}
44
45; An address with an index and a subtracted displacement (order 1).
46define void @f4(i64 %addr, i64 %index) {
47; CHECK-LABEL: f4:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    lb %r0, -100(%r3,%r2)
50; CHECK-NEXT:    br %r14
51  %add1 = add i64 %addr, %index
52  %add2 = sub i64 %add1, 100
53  %ptr = inttoptr i64 %add2 to ptr
54  %a = load volatile i8, ptr %ptr
55  ret void
56}
57
58; An address with an index and a subtracted displacement (order 2).
59define void @f5(i64 %addr, i64 %index) {
60; CHECK-LABEL: f5:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    lb %r0, -100(%r3,%r2)
63; CHECK-NEXT:    br %r14
64  %add1 = sub i64 %addr, 100
65  %add2 = add i64 %add1, %index
66  %ptr = inttoptr i64 %add2 to ptr
67  %a = load volatile i8, ptr %ptr
68  ret void
69}
70
71; An address with an index and a displacement added using OR.
72define void @f6(i64 %addr, i64 %index) {
73; CHECK-LABEL: f6:
74; CHECK:       # %bb.0:
75; CHECK-NEXT:    nill %r2, 65528
76; CHECK-NEXT:    lb %r0, 6(%r2,%r3)
77; CHECK-NEXT:    br %r14
78  %aligned = and i64 %addr, -8
79  %or = or i64 %aligned, 6
80  %add = add i64 %or, %index
81  %ptr = inttoptr i64 %add to ptr
82  %a = load volatile i8, ptr %ptr
83  ret void
84}
85
86; Like f6, but without the masking.  This OR doesn't count as a displacement.
87define void @f7(i64 %addr, i64 %index) {
88; CHECK-LABEL: f7:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    oill %r2, 6
91; CHECK-NEXT:    lb %r0, 0(%r3,%r2)
92; CHECK-NEXT:    br %r14
93  %or = or i64 %addr, 6
94  %add = add i64 %or, %index
95  %ptr = inttoptr i64 %add to ptr
96  %a = load volatile i8, ptr %ptr
97  ret void
98}
99
100; Like f6, but with the OR applied after the index.  We don't know anything
101; about the alignment of %add here.
102define void @f8(i64 %addr, i64 %index) {
103; CHECK-LABEL: f8:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    nill %r2, 65528
106; CHECK-NEXT:    agr %r2, %r3
107; CHECK-NEXT:    oill %r2, 6
108; CHECK-NEXT:    lb %r0, 0(%r2)
109; CHECK-NEXT:    br %r14
110  %aligned = and i64 %addr, -8
111  %add = add i64 %aligned, %index
112  %or = or i64 %add, 6
113  %ptr = inttoptr i64 %or to ptr
114  %a = load volatile i8, ptr %ptr
115  ret void
116}
117