1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the X86 Disassembler Emitter.
10 // It contains the implementation of a single recognizable instruction.
11 // Documentation for the disassembler emitter in general can be found in
12 // X86DisassemblerEmitter.h.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "X86RecognizableInstr.h"
17 #include "X86DisassemblerShared.h"
18 #include "X86DisassemblerTables.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/TableGen/Record.h"
22 #include <string>
23
24 using namespace llvm;
25 using namespace X86Disassembler;
26
getMnemonic(const CodeGenInstruction * I,unsigned Variant)27 std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, unsigned Variant) {
28 std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant);
29 StringRef Mnemonic(AsmString);
30 // Extract a mnemonic assuming it's separated by \t
31 Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; });
32
33 // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic.
34 // Replace it with "CC" in-place.
35 size_t CondPos = Mnemonic.find("${cond}");
36 if (CondPos != StringRef::npos)
37 Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC");
38 return Mnemonic.upper();
39 }
40
isRegisterOperand(const Record * Rec)41 bool X86Disassembler::isRegisterOperand(const Record *Rec) {
42 return Rec->isSubClassOf("RegisterClass") ||
43 Rec->isSubClassOf("RegisterOperand");
44 }
45
isMemoryOperand(const Record * Rec)46 bool X86Disassembler::isMemoryOperand(const Record *Rec) {
47 return Rec->isSubClassOf("Operand") &&
48 Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
49 }
50
isImmediateOperand(const Record * Rec)51 bool X86Disassembler::isImmediateOperand(const Record *Rec) {
52 return Rec->isSubClassOf("Operand") &&
53 Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
54 }
55
getRegOperandSize(const Record * RegRec)56 unsigned X86Disassembler::getRegOperandSize(const Record *RegRec) {
57 if (RegRec->isSubClassOf("RegisterClass"))
58 return RegRec->getValueAsInt("Alignment");
59 if (RegRec->isSubClassOf("RegisterOperand"))
60 return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
61
62 llvm_unreachable("Register operand's size not known!");
63 }
64
getMemOperandSize(const Record * MemRec)65 unsigned X86Disassembler::getMemOperandSize(const Record *MemRec) {
66 if (MemRec->isSubClassOf("X86MemOperand"))
67 return MemRec->getValueAsInt("Size");
68
69 llvm_unreachable("Memory operand's size not known!");
70 }
71
72 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
73 /// Useful for switch statements and the like.
74 ///
75 /// @param init - A reference to the BitsInit to be decoded.
76 /// @return - The field, with the first bit in the BitsInit as the lowest
77 /// order bit.
byteFromBitsInit(BitsInit & init)78 static uint8_t byteFromBitsInit(BitsInit &init) {
79 int width = init.getNumBits();
80
81 assert(width <= 8 && "Field is too large for uint8_t!");
82
83 int index;
84 uint8_t mask = 0x01;
85
86 uint8_t ret = 0;
87
88 for (index = 0; index < width; index++) {
89 if (cast<BitInit>(init.getBit(index))->getValue())
90 ret |= mask;
91
92 mask <<= 1;
93 }
94
95 return ret;
96 }
97
98 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
99 /// name of the field.
100 ///
101 /// @param rec - The record from which to extract the value.
102 /// @param name - The name of the field in the record.
103 /// @return - The field, as translated by byteFromBitsInit().
byteFromRec(const Record * rec,StringRef name)104 static uint8_t byteFromRec(const Record* rec, StringRef name) {
105 BitsInit* bits = rec->getValueAsBitsInit(name);
106 return byteFromBitsInit(*bits);
107 }
108
RecognizableInstrBase(const CodeGenInstruction & insn)109 RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) {
110 const Record *Rec = insn.TheDef;
111 assert(Rec->isSubClassOf("X86Inst") && "Not a X86 Instruction");
112 OpPrefix = byteFromRec(Rec, "OpPrefixBits");
113 OpMap = byteFromRec(Rec, "OpMapBits");
114 Opcode = byteFromRec(Rec, "Opcode");
115 Form = byteFromRec(Rec, "FormBits");
116 Encoding = byteFromRec(Rec, "OpEncBits");
117 OpSize = byteFromRec(Rec, "OpSizeBits");
118 AdSize = byteFromRec(Rec, "AdSizeBits");
119 HasREX_W = Rec->getValueAsBit("hasREX_W");
120 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
121 HasVEX_W = Rec->getValueAsBit("HasVEX_W");
122 IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W");
123 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
124 HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2");
125 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
126 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
127 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
128 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
129 IsAsmParserOnly = Rec->getValueAsBit("isAsmParserOnly");
130 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
131 CD8_Scale = byteFromRec(Rec, "CD8_Scale");
132 HasVEX_L = Rec->getValueAsBit("hasVEX_L");
133
134 EncodeRC = HasEVEX_B &&
135 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg);
136 }
137
shouldBeEmitted() const138 bool RecognizableInstrBase::shouldBeEmitted() const {
139 return Form != X86Local::Pseudo && (!IsCodeGenOnly || ForceDisassemble) &&
140 !IsAsmParserOnly;
141 }
142
RecognizableInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)143 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
144 const CodeGenInstruction &insn,
145 InstrUID uid)
146 : RecognizableInstrBase(insn), Rec(insn.TheDef), Name(Rec->getName().str()),
147 Is32Bit(false), Is64Bit(false), Operands(&insn.Operands.OperandList),
148 UID(uid), Spec(&tables.specForUID(uid)) {
149 // Check for 64-bit inst which does not require REX
150 // FIXME: Is there some better way to check for In64BitMode?
151 std::vector<Record *> Predicates = Rec->getValueAsListOfDefs("Predicates");
152 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
153 if (Predicates[i]->getName().contains("Not64Bit") ||
154 Predicates[i]->getName().contains("In32Bit")) {
155 Is32Bit = true;
156 break;
157 }
158 if (Predicates[i]->getName().contains("In64Bit")) {
159 Is64Bit = true;
160 break;
161 }
162 }
163 }
164
processInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)165 void RecognizableInstr::processInstr(DisassemblerTables &tables,
166 const CodeGenInstruction &insn,
167 InstrUID uid) {
168 if (!insn.TheDef->isSubClassOf("X86Inst"))
169 return;
170 RecognizableInstr recogInstr(tables, insn, uid);
171
172 if (!recogInstr.shouldBeEmitted())
173 return;
174 recogInstr.emitInstructionSpecifier();
175 recogInstr.emitDecodePath(tables);
176 }
177
178 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
179 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
180 (HasEVEX_KZ ? n##_KZ : \
181 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
182
insnContext() const183 InstructionContext RecognizableInstr::insnContext() const {
184 InstructionContext insnContext;
185
186 if (Encoding == X86Local::EVEX) {
187 if (HasVEX_L && HasEVEX_L2) {
188 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
189 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
190 }
191 // VEX_L & VEX_W
192 if (!EncodeRC && HasVEX_L && HasVEX_W) {
193 if (OpPrefix == X86Local::PD)
194 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
195 else if (OpPrefix == X86Local::XS)
196 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
197 else if (OpPrefix == X86Local::XD)
198 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
199 else if (OpPrefix == X86Local::PS)
200 insnContext = EVEX_KB(IC_EVEX_L_W);
201 else {
202 errs() << "Instruction does not use a prefix: " << Name << "\n";
203 llvm_unreachable("Invalid prefix");
204 }
205 } else if (!EncodeRC && HasVEX_L) {
206 // VEX_L
207 if (OpPrefix == X86Local::PD)
208 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
209 else if (OpPrefix == X86Local::XS)
210 insnContext = EVEX_KB(IC_EVEX_L_XS);
211 else if (OpPrefix == X86Local::XD)
212 insnContext = EVEX_KB(IC_EVEX_L_XD);
213 else if (OpPrefix == X86Local::PS)
214 insnContext = EVEX_KB(IC_EVEX_L);
215 else {
216 errs() << "Instruction does not use a prefix: " << Name << "\n";
217 llvm_unreachable("Invalid prefix");
218 }
219 } else if (!EncodeRC && HasEVEX_L2 && HasVEX_W) {
220 // EVEX_L2 & VEX_W
221 if (OpPrefix == X86Local::PD)
222 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
223 else if (OpPrefix == X86Local::XS)
224 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
225 else if (OpPrefix == X86Local::XD)
226 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
227 else if (OpPrefix == X86Local::PS)
228 insnContext = EVEX_KB(IC_EVEX_L2_W);
229 else {
230 errs() << "Instruction does not use a prefix: " << Name << "\n";
231 llvm_unreachable("Invalid prefix");
232 }
233 } else if (!EncodeRC && HasEVEX_L2) {
234 // EVEX_L2
235 if (OpPrefix == X86Local::PD)
236 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
237 else if (OpPrefix == X86Local::XD)
238 insnContext = EVEX_KB(IC_EVEX_L2_XD);
239 else if (OpPrefix == X86Local::XS)
240 insnContext = EVEX_KB(IC_EVEX_L2_XS);
241 else if (OpPrefix == X86Local::PS)
242 insnContext = EVEX_KB(IC_EVEX_L2);
243 else {
244 errs() << "Instruction does not use a prefix: " << Name << "\n";
245 llvm_unreachable("Invalid prefix");
246 }
247 }
248 else if (HasVEX_W) {
249 // VEX_W
250 if (OpPrefix == X86Local::PD)
251 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
252 else if (OpPrefix == X86Local::XS)
253 insnContext = EVEX_KB(IC_EVEX_W_XS);
254 else if (OpPrefix == X86Local::XD)
255 insnContext = EVEX_KB(IC_EVEX_W_XD);
256 else if (OpPrefix == X86Local::PS)
257 insnContext = EVEX_KB(IC_EVEX_W);
258 else {
259 errs() << "Instruction does not use a prefix: " << Name << "\n";
260 llvm_unreachable("Invalid prefix");
261 }
262 }
263 // No L, no W
264 else if (OpPrefix == X86Local::PD)
265 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
266 else if (OpPrefix == X86Local::XD)
267 insnContext = EVEX_KB(IC_EVEX_XD);
268 else if (OpPrefix == X86Local::XS)
269 insnContext = EVEX_KB(IC_EVEX_XS);
270 else if (OpPrefix == X86Local::PS)
271 insnContext = EVEX_KB(IC_EVEX);
272 else {
273 errs() << "Instruction does not use a prefix: " << Name << "\n";
274 llvm_unreachable("Invalid prefix");
275 }
276 /// eof EVEX
277 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
278 if (HasVEX_L && HasVEX_W) {
279 if (OpPrefix == X86Local::PD)
280 insnContext = IC_VEX_L_W_OPSIZE;
281 else if (OpPrefix == X86Local::XS)
282 insnContext = IC_VEX_L_W_XS;
283 else if (OpPrefix == X86Local::XD)
284 insnContext = IC_VEX_L_W_XD;
285 else if (OpPrefix == X86Local::PS)
286 insnContext = IC_VEX_L_W;
287 else {
288 errs() << "Instruction does not use a prefix: " << Name << "\n";
289 llvm_unreachable("Invalid prefix");
290 }
291 } else if (OpPrefix == X86Local::PD && HasVEX_L)
292 insnContext = IC_VEX_L_OPSIZE;
293 else if (OpPrefix == X86Local::PD && HasVEX_W)
294 insnContext = IC_VEX_W_OPSIZE;
295 else if (OpPrefix == X86Local::PD)
296 insnContext = IC_VEX_OPSIZE;
297 else if (HasVEX_L && OpPrefix == X86Local::XS)
298 insnContext = IC_VEX_L_XS;
299 else if (HasVEX_L && OpPrefix == X86Local::XD)
300 insnContext = IC_VEX_L_XD;
301 else if (HasVEX_W && OpPrefix == X86Local::XS)
302 insnContext = IC_VEX_W_XS;
303 else if (HasVEX_W && OpPrefix == X86Local::XD)
304 insnContext = IC_VEX_W_XD;
305 else if (HasVEX_W && OpPrefix == X86Local::PS)
306 insnContext = IC_VEX_W;
307 else if (HasVEX_L && OpPrefix == X86Local::PS)
308 insnContext = IC_VEX_L;
309 else if (OpPrefix == X86Local::XD)
310 insnContext = IC_VEX_XD;
311 else if (OpPrefix == X86Local::XS)
312 insnContext = IC_VEX_XS;
313 else if (OpPrefix == X86Local::PS)
314 insnContext = IC_VEX;
315 else {
316 errs() << "Instruction does not use a prefix: " << Name << "\n";
317 llvm_unreachable("Invalid prefix");
318 }
319 } else if (Is64Bit || HasREX_W || AdSize == X86Local::AdSize64) {
320 if (HasREX_W && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
321 insnContext = IC_64BIT_REXW_OPSIZE;
322 else if (HasREX_W && AdSize == X86Local::AdSize32)
323 insnContext = IC_64BIT_REXW_ADSIZE;
324 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
325 insnContext = IC_64BIT_XD_OPSIZE;
326 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
327 insnContext = IC_64BIT_XS_OPSIZE;
328 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD)
329 insnContext = IC_64BIT_OPSIZE_ADSIZE;
330 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
331 insnContext = IC_64BIT_OPSIZE_ADSIZE;
332 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
333 insnContext = IC_64BIT_OPSIZE;
334 else if (AdSize == X86Local::AdSize32)
335 insnContext = IC_64BIT_ADSIZE;
336 else if (HasREX_W && OpPrefix == X86Local::XS)
337 insnContext = IC_64BIT_REXW_XS;
338 else if (HasREX_W && OpPrefix == X86Local::XD)
339 insnContext = IC_64BIT_REXW_XD;
340 else if (OpPrefix == X86Local::XD)
341 insnContext = IC_64BIT_XD;
342 else if (OpPrefix == X86Local::XS)
343 insnContext = IC_64BIT_XS;
344 else if (HasREX_W)
345 insnContext = IC_64BIT_REXW;
346 else
347 insnContext = IC_64BIT;
348 } else {
349 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
350 insnContext = IC_XD_OPSIZE;
351 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
352 insnContext = IC_XS_OPSIZE;
353 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD)
354 insnContext = IC_XD_ADSIZE;
355 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS)
356 insnContext = IC_XS_ADSIZE;
357 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD)
358 insnContext = IC_OPSIZE_ADSIZE;
359 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
360 insnContext = IC_OPSIZE_ADSIZE;
361 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
362 insnContext = IC_OPSIZE;
363 else if (AdSize == X86Local::AdSize16)
364 insnContext = IC_ADSIZE;
365 else if (OpPrefix == X86Local::XD)
366 insnContext = IC_XD;
367 else if (OpPrefix == X86Local::XS)
368 insnContext = IC_XS;
369 else
370 insnContext = IC;
371 }
372
373 return insnContext;
374 }
375
adjustOperandEncoding(OperandEncoding & encoding)376 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
377 // The scaling factor for AVX512 compressed displacement encoding is an
378 // instruction attribute. Adjust the ModRM encoding type to include the
379 // scale for compressed displacement.
380 if ((encoding != ENCODING_RM &&
381 encoding != ENCODING_VSIB &&
382 encoding != ENCODING_SIB) ||CD8_Scale == 0)
383 return;
384 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
385 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) ||
386 (encoding == ENCODING_SIB) ||
387 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) &&
388 "Invalid CDisp scaling");
389 }
390
handleOperand(bool optional,unsigned & operandIndex,unsigned & physicalOperandIndex,unsigned numPhysicalOperands,const unsigned * operandMapping,OperandEncoding (* encodingFromString)(const std::string &,uint8_t OpSize))391 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
392 unsigned &physicalOperandIndex,
393 unsigned numPhysicalOperands,
394 const unsigned *operandMapping,
395 OperandEncoding (*encodingFromString)
396 (const std::string&,
397 uint8_t OpSize)) {
398 if (optional) {
399 if (physicalOperandIndex >= numPhysicalOperands)
400 return;
401 } else {
402 assert(physicalOperandIndex < numPhysicalOperands);
403 }
404
405 while (operandMapping[operandIndex] != operandIndex) {
406 Spec->operands[operandIndex].encoding = ENCODING_DUP;
407 Spec->operands[operandIndex].type =
408 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
409 ++operandIndex;
410 }
411
412 StringRef typeName = (*Operands)[operandIndex].Rec->getName();
413
414 OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize);
415 // Adjust the encoding type for an operand based on the instruction.
416 adjustOperandEncoding(encoding);
417 Spec->operands[operandIndex].encoding = encoding;
418 Spec->operands[operandIndex].type =
419 typeFromString(std::string(typeName), HasREX_W, OpSize);
420
421 ++operandIndex;
422 ++physicalOperandIndex;
423 }
424
emitInstructionSpecifier()425 void RecognizableInstr::emitInstructionSpecifier() {
426 Spec->name = Name;
427
428 Spec->insnContext = insnContext();
429
430 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
431
432 unsigned numOperands = OperandList.size();
433 unsigned numPhysicalOperands = 0;
434
435 // operandMapping maps from operands in OperandList to their originals.
436 // If operandMapping[i] != i, then the entry is a duplicate.
437 unsigned operandMapping[X86_MAX_OPERANDS];
438 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
439
440 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
441 if (!OperandList[operandIndex].Constraints.empty()) {
442 const CGIOperandList::ConstraintInfo &Constraint =
443 OperandList[operandIndex].Constraints[0];
444 if (Constraint.isTied()) {
445 operandMapping[operandIndex] = operandIndex;
446 operandMapping[Constraint.getTiedOperand()] = operandIndex;
447 } else {
448 ++numPhysicalOperands;
449 operandMapping[operandIndex] = operandIndex;
450 }
451 } else {
452 ++numPhysicalOperands;
453 operandMapping[operandIndex] = operandIndex;
454 }
455 }
456
457 #define HANDLE_OPERAND(class) \
458 handleOperand(false, \
459 operandIndex, \
460 physicalOperandIndex, \
461 numPhysicalOperands, \
462 operandMapping, \
463 class##EncodingFromString);
464
465 #define HANDLE_OPTIONAL(class) \
466 handleOperand(true, \
467 operandIndex, \
468 physicalOperandIndex, \
469 numPhysicalOperands, \
470 operandMapping, \
471 class##EncodingFromString);
472
473 // operandIndex should always be < numOperands
474 unsigned operandIndex = 0;
475 // physicalOperandIndex should always be < numPhysicalOperands
476 unsigned physicalOperandIndex = 0;
477
478 #ifndef NDEBUG
479 // Given the set of prefix bits, how many additional operands does the
480 // instruction have?
481 unsigned additionalOperands = 0;
482 if (HasVEX_4V)
483 ++additionalOperands;
484 if (HasEVEX_K)
485 ++additionalOperands;
486 #endif
487
488 switch (Form) {
489 default: llvm_unreachable("Unhandled form");
490 case X86Local::PrefixByte:
491 return;
492 case X86Local::RawFrmSrc:
493 HANDLE_OPERAND(relocation);
494 return;
495 case X86Local::RawFrmDst:
496 HANDLE_OPERAND(relocation);
497 return;
498 case X86Local::RawFrmDstSrc:
499 HANDLE_OPERAND(relocation);
500 HANDLE_OPERAND(relocation);
501 return;
502 case X86Local::RawFrm:
503 // Operand 1 (optional) is an address or immediate.
504 assert(numPhysicalOperands <= 1 &&
505 "Unexpected number of operands for RawFrm");
506 HANDLE_OPTIONAL(relocation)
507 break;
508 case X86Local::RawFrmMemOffs:
509 // Operand 1 is an address.
510 HANDLE_OPERAND(relocation);
511 break;
512 case X86Local::AddRegFrm:
513 // Operand 1 is added to the opcode.
514 // Operand 2 (optional) is an address.
515 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
516 "Unexpected number of operands for AddRegFrm");
517 HANDLE_OPERAND(opcodeModifier)
518 HANDLE_OPTIONAL(relocation)
519 break;
520 case X86Local::AddCCFrm:
521 // Operand 1 (optional) is an address or immediate.
522 assert(numPhysicalOperands == 2 &&
523 "Unexpected number of operands for AddCCFrm");
524 HANDLE_OPERAND(relocation)
525 HANDLE_OPERAND(opcodeModifier)
526 break;
527 case X86Local::MRMDestReg:
528 // Operand 1 is a register operand in the R/M field.
529 // - In AVX512 there may be a mask operand here -
530 // Operand 2 is a register operand in the Reg/Opcode field.
531 // - In AVX, there is a register operand in the VEX.vvvv field here -
532 // Operand 3 (optional) is an immediate.
533 assert(numPhysicalOperands >= 2 + additionalOperands &&
534 numPhysicalOperands <= 3 + additionalOperands &&
535 "Unexpected number of operands for MRMDestRegFrm");
536
537 HANDLE_OPERAND(rmRegister)
538 if (HasEVEX_K)
539 HANDLE_OPERAND(writemaskRegister)
540
541 if (HasVEX_4V)
542 // FIXME: In AVX, the register below becomes the one encoded
543 // in ModRMVEX and the one above the one in the VEX.VVVV field
544 HANDLE_OPERAND(vvvvRegister)
545
546 HANDLE_OPERAND(roRegister)
547 HANDLE_OPTIONAL(immediate)
548 break;
549 case X86Local::MRMDestMem4VOp3CC:
550 // Operand 1 is a register operand in the Reg/Opcode field.
551 // Operand 2 is a register operand in the R/M field.
552 // Operand 3 is VEX.vvvv
553 // Operand 4 is condition code.
554 assert(numPhysicalOperands == 4 &&
555 "Unexpected number of operands for MRMDestMem4VOp3CC");
556 HANDLE_OPERAND(roRegister)
557 HANDLE_OPERAND(memory)
558 HANDLE_OPERAND(vvvvRegister)
559 HANDLE_OPERAND(opcodeModifier)
560 break;
561 case X86Local::MRMDestMem:
562 case X86Local::MRMDestMemFSIB:
563 // Operand 1 is a memory operand (possibly SIB-extended)
564 // Operand 2 is a register operand in the Reg/Opcode field.
565 // - In AVX, there is a register operand in the VEX.vvvv field here -
566 // Operand 3 (optional) is an immediate.
567 assert(numPhysicalOperands >= 2 + additionalOperands &&
568 numPhysicalOperands <= 3 + additionalOperands &&
569 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
570
571 HANDLE_OPERAND(memory)
572
573 if (HasEVEX_K)
574 HANDLE_OPERAND(writemaskRegister)
575
576 if (HasVEX_4V)
577 // FIXME: In AVX, the register below becomes the one encoded
578 // in ModRMVEX and the one above the one in the VEX.VVVV field
579 HANDLE_OPERAND(vvvvRegister)
580
581 HANDLE_OPERAND(roRegister)
582 HANDLE_OPTIONAL(immediate)
583 break;
584 case X86Local::MRMSrcReg:
585 // Operand 1 is a register operand in the Reg/Opcode field.
586 // Operand 2 is a register operand in the R/M field.
587 // - In AVX, there is a register operand in the VEX.vvvv field here -
588 // Operand 3 (optional) is an immediate.
589 // Operand 4 (optional) is an immediate.
590
591 assert(numPhysicalOperands >= 2 + additionalOperands &&
592 numPhysicalOperands <= 4 + additionalOperands &&
593 "Unexpected number of operands for MRMSrcRegFrm");
594
595 HANDLE_OPERAND(roRegister)
596
597 if (HasEVEX_K)
598 HANDLE_OPERAND(writemaskRegister)
599
600 if (HasVEX_4V)
601 // FIXME: In AVX, the register below becomes the one encoded
602 // in ModRMVEX and the one above the one in the VEX.VVVV field
603 HANDLE_OPERAND(vvvvRegister)
604
605 HANDLE_OPERAND(rmRegister)
606 HANDLE_OPTIONAL(immediate)
607 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
608 break;
609 case X86Local::MRMSrcReg4VOp3:
610 assert(numPhysicalOperands == 3 &&
611 "Unexpected number of operands for MRMSrcReg4VOp3Frm");
612 HANDLE_OPERAND(roRegister)
613 HANDLE_OPERAND(rmRegister)
614 HANDLE_OPERAND(vvvvRegister)
615 break;
616 case X86Local::MRMSrcRegOp4:
617 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
618 "Unexpected number of operands for MRMSrcRegOp4Frm");
619 HANDLE_OPERAND(roRegister)
620 HANDLE_OPERAND(vvvvRegister)
621 HANDLE_OPERAND(immediate) // Register in imm[7:4]
622 HANDLE_OPERAND(rmRegister)
623 HANDLE_OPTIONAL(immediate)
624 break;
625 case X86Local::MRMSrcRegCC:
626 assert(numPhysicalOperands == 3 &&
627 "Unexpected number of operands for MRMSrcRegCC");
628 HANDLE_OPERAND(roRegister)
629 HANDLE_OPERAND(rmRegister)
630 HANDLE_OPERAND(opcodeModifier)
631 break;
632 case X86Local::MRMSrcMem:
633 case X86Local::MRMSrcMemFSIB:
634 // Operand 1 is a register operand in the Reg/Opcode field.
635 // Operand 2 is a memory operand (possibly SIB-extended)
636 // - In AVX, there is a register operand in the VEX.vvvv field here -
637 // Operand 3 (optional) is an immediate.
638
639 assert(numPhysicalOperands >= 2 + additionalOperands &&
640 numPhysicalOperands <= 4 + additionalOperands &&
641 "Unexpected number of operands for MRMSrcMemFrm");
642
643 HANDLE_OPERAND(roRegister)
644
645 if (HasEVEX_K)
646 HANDLE_OPERAND(writemaskRegister)
647
648 if (HasVEX_4V)
649 // FIXME: In AVX, the register below becomes the one encoded
650 // in ModRMVEX and the one above the one in the VEX.VVVV field
651 HANDLE_OPERAND(vvvvRegister)
652
653 HANDLE_OPERAND(memory)
654 HANDLE_OPTIONAL(immediate)
655 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
656 break;
657 case X86Local::MRMSrcMem4VOp3:
658 assert(numPhysicalOperands == 3 &&
659 "Unexpected number of operands for MRMSrcMem4VOp3Frm");
660 HANDLE_OPERAND(roRegister)
661 HANDLE_OPERAND(memory)
662 HANDLE_OPERAND(vvvvRegister)
663 break;
664 case X86Local::MRMSrcMemOp4:
665 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
666 "Unexpected number of operands for MRMSrcMemOp4Frm");
667 HANDLE_OPERAND(roRegister)
668 HANDLE_OPERAND(vvvvRegister)
669 HANDLE_OPERAND(immediate) // Register in imm[7:4]
670 HANDLE_OPERAND(memory)
671 HANDLE_OPTIONAL(immediate)
672 break;
673 case X86Local::MRMSrcMemCC:
674 assert(numPhysicalOperands == 3 &&
675 "Unexpected number of operands for MRMSrcMemCC");
676 HANDLE_OPERAND(roRegister)
677 HANDLE_OPERAND(memory)
678 HANDLE_OPERAND(opcodeModifier)
679 break;
680 case X86Local::MRMXrCC:
681 assert(numPhysicalOperands == 2 &&
682 "Unexpected number of operands for MRMXrCC");
683 HANDLE_OPERAND(rmRegister)
684 HANDLE_OPERAND(opcodeModifier)
685 break;
686 case X86Local::MRMr0:
687 // Operand 1 is a register operand in the R/M field.
688 HANDLE_OPERAND(roRegister)
689 break;
690 case X86Local::MRMXr:
691 case X86Local::MRM0r:
692 case X86Local::MRM1r:
693 case X86Local::MRM2r:
694 case X86Local::MRM3r:
695 case X86Local::MRM4r:
696 case X86Local::MRM5r:
697 case X86Local::MRM6r:
698 case X86Local::MRM7r:
699 // Operand 1 is a register operand in the R/M field.
700 // Operand 2 (optional) is an immediate or relocation.
701 // Operand 3 (optional) is an immediate.
702 assert(numPhysicalOperands >= 0 + additionalOperands &&
703 numPhysicalOperands <= 3 + additionalOperands &&
704 "Unexpected number of operands for MRMnr");
705
706 if (HasVEX_4V)
707 HANDLE_OPERAND(vvvvRegister)
708
709 if (HasEVEX_K)
710 HANDLE_OPERAND(writemaskRegister)
711 HANDLE_OPTIONAL(rmRegister)
712 HANDLE_OPTIONAL(relocation)
713 HANDLE_OPTIONAL(immediate)
714 break;
715 case X86Local::MRMXmCC:
716 assert(numPhysicalOperands == 2 &&
717 "Unexpected number of operands for MRMXm");
718 HANDLE_OPERAND(memory)
719 HANDLE_OPERAND(opcodeModifier)
720 break;
721 case X86Local::MRMXm:
722 case X86Local::MRM0m:
723 case X86Local::MRM1m:
724 case X86Local::MRM2m:
725 case X86Local::MRM3m:
726 case X86Local::MRM4m:
727 case X86Local::MRM5m:
728 case X86Local::MRM6m:
729 case X86Local::MRM7m:
730 // Operand 1 is a memory operand (possibly SIB-extended)
731 // Operand 2 (optional) is an immediate or relocation.
732 assert(numPhysicalOperands >= 1 + additionalOperands &&
733 numPhysicalOperands <= 2 + additionalOperands &&
734 "Unexpected number of operands for MRMnm");
735
736 if (HasVEX_4V)
737 HANDLE_OPERAND(vvvvRegister)
738 if (HasEVEX_K)
739 HANDLE_OPERAND(writemaskRegister)
740 HANDLE_OPERAND(memory)
741 HANDLE_OPTIONAL(relocation)
742 break;
743 case X86Local::RawFrmImm8:
744 // operand 1 is a 16-bit immediate
745 // operand 2 is an 8-bit immediate
746 assert(numPhysicalOperands == 2 &&
747 "Unexpected number of operands for X86Local::RawFrmImm8");
748 HANDLE_OPERAND(immediate)
749 HANDLE_OPERAND(immediate)
750 break;
751 case X86Local::RawFrmImm16:
752 // operand 1 is a 16-bit immediate
753 // operand 2 is a 16-bit immediate
754 HANDLE_OPERAND(immediate)
755 HANDLE_OPERAND(immediate)
756 break;
757 case X86Local::MRM0X:
758 case X86Local::MRM1X:
759 case X86Local::MRM2X:
760 case X86Local::MRM3X:
761 case X86Local::MRM4X:
762 case X86Local::MRM5X:
763 case X86Local::MRM6X:
764 case X86Local::MRM7X:
765 #define MAP(from, to) case X86Local::MRM_##from:
766 X86_INSTR_MRM_MAPPING
767 #undef MAP
768 HANDLE_OPTIONAL(relocation)
769 break;
770 }
771
772 #undef HANDLE_OPERAND
773 #undef HANDLE_OPTIONAL
774 }
775
emitDecodePath(DisassemblerTables & tables) const776 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
777 // Special cases where the LLVM tables are not complete
778
779 #define MAP(from, to) \
780 case X86Local::MRM_##from:
781
782 std::optional<OpcodeType> opcodeType;
783 switch (OpMap) {
784 default: llvm_unreachable("Invalid map!");
785 case X86Local::OB: opcodeType = ONEBYTE; break;
786 case X86Local::TB: opcodeType = TWOBYTE; break;
787 case X86Local::T8: opcodeType = THREEBYTE_38; break;
788 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
789 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
790 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
791 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
792 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break;
793 case X86Local::T_MAP5: opcodeType = MAP5; break;
794 case X86Local::T_MAP6: opcodeType = MAP6; break;
795 }
796
797 std::unique_ptr<ModRMFilter> filter;
798 switch (Form) {
799 default: llvm_unreachable("Invalid form!");
800 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!");
801 case X86Local::RawFrm:
802 case X86Local::AddRegFrm:
803 case X86Local::RawFrmMemOffs:
804 case X86Local::RawFrmSrc:
805 case X86Local::RawFrmDst:
806 case X86Local::RawFrmDstSrc:
807 case X86Local::RawFrmImm8:
808 case X86Local::RawFrmImm16:
809 case X86Local::AddCCFrm:
810 case X86Local::PrefixByte:
811 filter = std::make_unique<DumbFilter>();
812 break;
813 case X86Local::MRMDestReg:
814 case X86Local::MRMSrcReg:
815 case X86Local::MRMSrcReg4VOp3:
816 case X86Local::MRMSrcRegOp4:
817 case X86Local::MRMSrcRegCC:
818 case X86Local::MRMXrCC:
819 case X86Local::MRMXr:
820 filter = std::make_unique<ModFilter>(true);
821 break;
822 case X86Local::MRMDestMem:
823 case X86Local::MRMDestMem4VOp3CC:
824 case X86Local::MRMDestMemFSIB:
825 case X86Local::MRMSrcMem:
826 case X86Local::MRMSrcMemFSIB:
827 case X86Local::MRMSrcMem4VOp3:
828 case X86Local::MRMSrcMemOp4:
829 case X86Local::MRMSrcMemCC:
830 case X86Local::MRMXmCC:
831 case X86Local::MRMXm:
832 filter = std::make_unique<ModFilter>(false);
833 break;
834 case X86Local::MRM0r: case X86Local::MRM1r:
835 case X86Local::MRM2r: case X86Local::MRM3r:
836 case X86Local::MRM4r: case X86Local::MRM5r:
837 case X86Local::MRM6r: case X86Local::MRM7r:
838 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r);
839 break;
840 case X86Local::MRM0X: case X86Local::MRM1X:
841 case X86Local::MRM2X: case X86Local::MRM3X:
842 case X86Local::MRM4X: case X86Local::MRM5X:
843 case X86Local::MRM6X: case X86Local::MRM7X:
844 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X);
845 break;
846 case X86Local::MRMr0:
847 filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0);
848 break;
849 case X86Local::MRM0m: case X86Local::MRM1m:
850 case X86Local::MRM2m: case X86Local::MRM3m:
851 case X86Local::MRM4m: case X86Local::MRM5m:
852 case X86Local::MRM6m: case X86Local::MRM7m:
853 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m);
854 break;
855 X86_INSTR_MRM_MAPPING
856 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0);
857 break;
858 } // switch (Form)
859
860 uint8_t opcodeToSet = Opcode;
861
862 unsigned AddressSize = 0;
863 switch (AdSize) {
864 case X86Local::AdSize16: AddressSize = 16; break;
865 case X86Local::AdSize32: AddressSize = 32; break;
866 case X86Local::AdSize64: AddressSize = 64; break;
867 }
868
869 assert(opcodeType && "Opcode type not set");
870 assert(filter && "Filter not set");
871
872 if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC ||
873 Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC ||
874 Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm ||
875 Form == X86Local::MRMDestMem4VOp3CC) {
876 uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16;
877 assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned");
878
879 uint8_t currentOpcode;
880
881 for (currentOpcode = opcodeToSet;
882 currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode)
883 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter,
884 UID, Is32Bit, OpPrefix == 0,
885 IgnoresVEX_L || EncodeRC,
886 IgnoresVEX_W, AddressSize);
887 } else {
888 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID,
889 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC,
890 IgnoresVEX_W, AddressSize);
891 }
892
893 #undef MAP
894 }
895
896 #define TYPE(str, type) if (s == str) return type;
typeFromString(const std::string & s,bool hasREX_W,uint8_t OpSize)897 OperandType RecognizableInstr::typeFromString(const std::string &s,
898 bool hasREX_W,
899 uint8_t OpSize) {
900 if(hasREX_W) {
901 // For instructions with a REX_W prefix, a declared 32-bit register encoding
902 // is special.
903 TYPE("GR32", TYPE_R32)
904 }
905 if(OpSize == X86Local::OpSize16) {
906 // For OpSize16 instructions, a declared 16-bit register or
907 // immediate encoding is special.
908 TYPE("GR16", TYPE_Rv)
909 } else if(OpSize == X86Local::OpSize32) {
910 // For OpSize32 instructions, a declared 32-bit register or
911 // immediate encoding is special.
912 TYPE("GR32", TYPE_Rv)
913 }
914 TYPE("i16mem", TYPE_M)
915 TYPE("i16imm", TYPE_IMM)
916 TYPE("i16i8imm", TYPE_IMM)
917 TYPE("GR16", TYPE_R16)
918 TYPE("GR16orGR32orGR64", TYPE_R16)
919 TYPE("i32mem", TYPE_M)
920 TYPE("i32imm", TYPE_IMM)
921 TYPE("i32i8imm", TYPE_IMM)
922 TYPE("GR32", TYPE_R32)
923 TYPE("GR32orGR64", TYPE_R32)
924 TYPE("i64mem", TYPE_M)
925 TYPE("i64i32imm", TYPE_IMM)
926 TYPE("i64i8imm", TYPE_IMM)
927 TYPE("GR64", TYPE_R64)
928 TYPE("i8mem", TYPE_M)
929 TYPE("i8imm", TYPE_IMM)
930 TYPE("u4imm", TYPE_UIMM8)
931 TYPE("u8imm", TYPE_UIMM8)
932 TYPE("i16u8imm", TYPE_UIMM8)
933 TYPE("i32u8imm", TYPE_UIMM8)
934 TYPE("i64u8imm", TYPE_UIMM8)
935 TYPE("GR8", TYPE_R8)
936 TYPE("VR128", TYPE_XMM)
937 TYPE("VR128X", TYPE_XMM)
938 TYPE("f128mem", TYPE_M)
939 TYPE("f256mem", TYPE_M)
940 TYPE("f512mem", TYPE_M)
941 TYPE("FR128", TYPE_XMM)
942 TYPE("FR64", TYPE_XMM)
943 TYPE("FR64X", TYPE_XMM)
944 TYPE("f64mem", TYPE_M)
945 TYPE("sdmem", TYPE_M)
946 TYPE("FR16X", TYPE_XMM)
947 TYPE("FR32", TYPE_XMM)
948 TYPE("FR32X", TYPE_XMM)
949 TYPE("f32mem", TYPE_M)
950 TYPE("f16mem", TYPE_M)
951 TYPE("ssmem", TYPE_M)
952 TYPE("shmem", TYPE_M)
953 TYPE("RST", TYPE_ST)
954 TYPE("RSTi", TYPE_ST)
955 TYPE("i128mem", TYPE_M)
956 TYPE("i256mem", TYPE_M)
957 TYPE("i512mem", TYPE_M)
958 TYPE("i64i32imm_brtarget", TYPE_REL)
959 TYPE("i16imm_brtarget", TYPE_REL)
960 TYPE("i32imm_brtarget", TYPE_REL)
961 TYPE("ccode", TYPE_IMM)
962 TYPE("AVX512RC", TYPE_IMM)
963 TYPE("brtarget32", TYPE_REL)
964 TYPE("brtarget16", TYPE_REL)
965 TYPE("brtarget8", TYPE_REL)
966 TYPE("f80mem", TYPE_M)
967 TYPE("lea64_32mem", TYPE_M)
968 TYPE("lea64mem", TYPE_M)
969 TYPE("VR64", TYPE_MM64)
970 TYPE("i64imm", TYPE_IMM)
971 TYPE("anymem", TYPE_M)
972 TYPE("opaquemem", TYPE_M)
973 TYPE("sibmem", TYPE_MSIB)
974 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
975 TYPE("DEBUG_REG", TYPE_DEBUGREG)
976 TYPE("CONTROL_REG", TYPE_CONTROLREG)
977 TYPE("srcidx8", TYPE_SRCIDX)
978 TYPE("srcidx16", TYPE_SRCIDX)
979 TYPE("srcidx32", TYPE_SRCIDX)
980 TYPE("srcidx64", TYPE_SRCIDX)
981 TYPE("dstidx8", TYPE_DSTIDX)
982 TYPE("dstidx16", TYPE_DSTIDX)
983 TYPE("dstidx32", TYPE_DSTIDX)
984 TYPE("dstidx64", TYPE_DSTIDX)
985 TYPE("offset16_8", TYPE_MOFFS)
986 TYPE("offset16_16", TYPE_MOFFS)
987 TYPE("offset16_32", TYPE_MOFFS)
988 TYPE("offset32_8", TYPE_MOFFS)
989 TYPE("offset32_16", TYPE_MOFFS)
990 TYPE("offset32_32", TYPE_MOFFS)
991 TYPE("offset32_64", TYPE_MOFFS)
992 TYPE("offset64_8", TYPE_MOFFS)
993 TYPE("offset64_16", TYPE_MOFFS)
994 TYPE("offset64_32", TYPE_MOFFS)
995 TYPE("offset64_64", TYPE_MOFFS)
996 TYPE("VR256", TYPE_YMM)
997 TYPE("VR256X", TYPE_YMM)
998 TYPE("VR512", TYPE_ZMM)
999 TYPE("VK1", TYPE_VK)
1000 TYPE("VK1WM", TYPE_VK)
1001 TYPE("VK2", TYPE_VK)
1002 TYPE("VK2WM", TYPE_VK)
1003 TYPE("VK4", TYPE_VK)
1004 TYPE("VK4WM", TYPE_VK)
1005 TYPE("VK8", TYPE_VK)
1006 TYPE("VK8WM", TYPE_VK)
1007 TYPE("VK16", TYPE_VK)
1008 TYPE("VK16WM", TYPE_VK)
1009 TYPE("VK32", TYPE_VK)
1010 TYPE("VK32WM", TYPE_VK)
1011 TYPE("VK64", TYPE_VK)
1012 TYPE("VK64WM", TYPE_VK)
1013 TYPE("VK1Pair", TYPE_VK_PAIR)
1014 TYPE("VK2Pair", TYPE_VK_PAIR)
1015 TYPE("VK4Pair", TYPE_VK_PAIR)
1016 TYPE("VK8Pair", TYPE_VK_PAIR)
1017 TYPE("VK16Pair", TYPE_VK_PAIR)
1018 TYPE("vx64mem", TYPE_MVSIBX)
1019 TYPE("vx128mem", TYPE_MVSIBX)
1020 TYPE("vx256mem", TYPE_MVSIBX)
1021 TYPE("vy128mem", TYPE_MVSIBY)
1022 TYPE("vy256mem", TYPE_MVSIBY)
1023 TYPE("vx64xmem", TYPE_MVSIBX)
1024 TYPE("vx128xmem", TYPE_MVSIBX)
1025 TYPE("vx256xmem", TYPE_MVSIBX)
1026 TYPE("vy128xmem", TYPE_MVSIBY)
1027 TYPE("vy256xmem", TYPE_MVSIBY)
1028 TYPE("vy512xmem", TYPE_MVSIBY)
1029 TYPE("vz256mem", TYPE_MVSIBZ)
1030 TYPE("vz512mem", TYPE_MVSIBZ)
1031 TYPE("BNDR", TYPE_BNDR)
1032 TYPE("TILE", TYPE_TMM)
1033 errs() << "Unhandled type string " << s << "\n";
1034 llvm_unreachable("Unhandled type string");
1035 }
1036 #undef TYPE
1037
1038 #define ENCODING(str, encoding) if (s == str) return encoding;
1039 OperandEncoding
immediateEncodingFromString(const std::string & s,uint8_t OpSize)1040 RecognizableInstr::immediateEncodingFromString(const std::string &s,
1041 uint8_t OpSize) {
1042 if(OpSize != X86Local::OpSize16) {
1043 // For instructions without an OpSize prefix, a declared 16-bit register or
1044 // immediate encoding is special.
1045 ENCODING("i16imm", ENCODING_IW)
1046 }
1047 ENCODING("i32i8imm", ENCODING_IB)
1048 ENCODING("AVX512RC", ENCODING_IRC)
1049 ENCODING("i16imm", ENCODING_Iv)
1050 ENCODING("i16i8imm", ENCODING_IB)
1051 ENCODING("i32imm", ENCODING_Iv)
1052 ENCODING("i64i32imm", ENCODING_ID)
1053 ENCODING("i64i8imm", ENCODING_IB)
1054 ENCODING("i8imm", ENCODING_IB)
1055 ENCODING("u4imm", ENCODING_IB)
1056 ENCODING("u8imm", ENCODING_IB)
1057 ENCODING("i16u8imm", ENCODING_IB)
1058 ENCODING("i32u8imm", ENCODING_IB)
1059 ENCODING("i64u8imm", ENCODING_IB)
1060 // This is not a typo. Instructions like BLENDVPD put
1061 // register IDs in 8-bit immediates nowadays.
1062 ENCODING("FR32", ENCODING_IB)
1063 ENCODING("FR64", ENCODING_IB)
1064 ENCODING("FR128", ENCODING_IB)
1065 ENCODING("VR128", ENCODING_IB)
1066 ENCODING("VR256", ENCODING_IB)
1067 ENCODING("FR16X", ENCODING_IB)
1068 ENCODING("FR32X", ENCODING_IB)
1069 ENCODING("FR64X", ENCODING_IB)
1070 ENCODING("VR128X", ENCODING_IB)
1071 ENCODING("VR256X", ENCODING_IB)
1072 ENCODING("VR512", ENCODING_IB)
1073 ENCODING("TILE", ENCODING_IB)
1074 errs() << "Unhandled immediate encoding " << s << "\n";
1075 llvm_unreachable("Unhandled immediate encoding");
1076 }
1077
1078 OperandEncoding
rmRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1079 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1080 uint8_t OpSize) {
1081 ENCODING("RST", ENCODING_FP)
1082 ENCODING("RSTi", ENCODING_FP)
1083 ENCODING("GR16", ENCODING_RM)
1084 ENCODING("GR16orGR32orGR64",ENCODING_RM)
1085 ENCODING("GR32", ENCODING_RM)
1086 ENCODING("GR32orGR64", ENCODING_RM)
1087 ENCODING("GR64", ENCODING_RM)
1088 ENCODING("GR8", ENCODING_RM)
1089 ENCODING("VR128", ENCODING_RM)
1090 ENCODING("VR128X", ENCODING_RM)
1091 ENCODING("FR128", ENCODING_RM)
1092 ENCODING("FR64", ENCODING_RM)
1093 ENCODING("FR32", ENCODING_RM)
1094 ENCODING("FR64X", ENCODING_RM)
1095 ENCODING("FR32X", ENCODING_RM)
1096 ENCODING("FR16X", ENCODING_RM)
1097 ENCODING("VR64", ENCODING_RM)
1098 ENCODING("VR256", ENCODING_RM)
1099 ENCODING("VR256X", ENCODING_RM)
1100 ENCODING("VR512", ENCODING_RM)
1101 ENCODING("VK1", ENCODING_RM)
1102 ENCODING("VK2", ENCODING_RM)
1103 ENCODING("VK4", ENCODING_RM)
1104 ENCODING("VK8", ENCODING_RM)
1105 ENCODING("VK16", ENCODING_RM)
1106 ENCODING("VK32", ENCODING_RM)
1107 ENCODING("VK64", ENCODING_RM)
1108 ENCODING("BNDR", ENCODING_RM)
1109 ENCODING("TILE", ENCODING_RM)
1110 errs() << "Unhandled R/M register encoding " << s << "\n";
1111 llvm_unreachable("Unhandled R/M register encoding");
1112 }
1113
1114 OperandEncoding
roRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1115 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1116 uint8_t OpSize) {
1117 ENCODING("GR16", ENCODING_REG)
1118 ENCODING("GR16orGR32orGR64",ENCODING_REG)
1119 ENCODING("GR32", ENCODING_REG)
1120 ENCODING("GR32orGR64", ENCODING_REG)
1121 ENCODING("GR64", ENCODING_REG)
1122 ENCODING("GR8", ENCODING_REG)
1123 ENCODING("VR128", ENCODING_REG)
1124 ENCODING("FR128", ENCODING_REG)
1125 ENCODING("FR64", ENCODING_REG)
1126 ENCODING("FR32", ENCODING_REG)
1127 ENCODING("VR64", ENCODING_REG)
1128 ENCODING("SEGMENT_REG", ENCODING_REG)
1129 ENCODING("DEBUG_REG", ENCODING_REG)
1130 ENCODING("CONTROL_REG", ENCODING_REG)
1131 ENCODING("VR256", ENCODING_REG)
1132 ENCODING("VR256X", ENCODING_REG)
1133 ENCODING("VR128X", ENCODING_REG)
1134 ENCODING("FR64X", ENCODING_REG)
1135 ENCODING("FR32X", ENCODING_REG)
1136 ENCODING("FR16X", ENCODING_REG)
1137 ENCODING("VR512", ENCODING_REG)
1138 ENCODING("VK1", ENCODING_REG)
1139 ENCODING("VK2", ENCODING_REG)
1140 ENCODING("VK4", ENCODING_REG)
1141 ENCODING("VK8", ENCODING_REG)
1142 ENCODING("VK16", ENCODING_REG)
1143 ENCODING("VK32", ENCODING_REG)
1144 ENCODING("VK64", ENCODING_REG)
1145 ENCODING("VK1Pair", ENCODING_REG)
1146 ENCODING("VK2Pair", ENCODING_REG)
1147 ENCODING("VK4Pair", ENCODING_REG)
1148 ENCODING("VK8Pair", ENCODING_REG)
1149 ENCODING("VK16Pair", ENCODING_REG)
1150 ENCODING("VK1WM", ENCODING_REG)
1151 ENCODING("VK2WM", ENCODING_REG)
1152 ENCODING("VK4WM", ENCODING_REG)
1153 ENCODING("VK8WM", ENCODING_REG)
1154 ENCODING("VK16WM", ENCODING_REG)
1155 ENCODING("VK32WM", ENCODING_REG)
1156 ENCODING("VK64WM", ENCODING_REG)
1157 ENCODING("BNDR", ENCODING_REG)
1158 ENCODING("TILE", ENCODING_REG)
1159 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1160 llvm_unreachable("Unhandled reg/opcode register encoding");
1161 }
1162
1163 OperandEncoding
vvvvRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1164 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1165 uint8_t OpSize) {
1166 ENCODING("GR32", ENCODING_VVVV)
1167 ENCODING("GR64", ENCODING_VVVV)
1168 ENCODING("FR32", ENCODING_VVVV)
1169 ENCODING("FR128", ENCODING_VVVV)
1170 ENCODING("FR64", ENCODING_VVVV)
1171 ENCODING("VR128", ENCODING_VVVV)
1172 ENCODING("VR256", ENCODING_VVVV)
1173 ENCODING("FR16X", ENCODING_VVVV)
1174 ENCODING("FR32X", ENCODING_VVVV)
1175 ENCODING("FR64X", ENCODING_VVVV)
1176 ENCODING("VR128X", ENCODING_VVVV)
1177 ENCODING("VR256X", ENCODING_VVVV)
1178 ENCODING("VR512", ENCODING_VVVV)
1179 ENCODING("VK1", ENCODING_VVVV)
1180 ENCODING("VK2", ENCODING_VVVV)
1181 ENCODING("VK4", ENCODING_VVVV)
1182 ENCODING("VK8", ENCODING_VVVV)
1183 ENCODING("VK16", ENCODING_VVVV)
1184 ENCODING("VK32", ENCODING_VVVV)
1185 ENCODING("VK64", ENCODING_VVVV)
1186 ENCODING("TILE", ENCODING_VVVV)
1187 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1188 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1189 }
1190
1191 OperandEncoding
writemaskRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1192 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1193 uint8_t OpSize) {
1194 ENCODING("VK1WM", ENCODING_WRITEMASK)
1195 ENCODING("VK2WM", ENCODING_WRITEMASK)
1196 ENCODING("VK4WM", ENCODING_WRITEMASK)
1197 ENCODING("VK8WM", ENCODING_WRITEMASK)
1198 ENCODING("VK16WM", ENCODING_WRITEMASK)
1199 ENCODING("VK32WM", ENCODING_WRITEMASK)
1200 ENCODING("VK64WM", ENCODING_WRITEMASK)
1201 errs() << "Unhandled mask register encoding " << s << "\n";
1202 llvm_unreachable("Unhandled mask register encoding");
1203 }
1204
1205 OperandEncoding
memoryEncodingFromString(const std::string & s,uint8_t OpSize)1206 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1207 uint8_t OpSize) {
1208 ENCODING("i16mem", ENCODING_RM)
1209 ENCODING("i32mem", ENCODING_RM)
1210 ENCODING("i64mem", ENCODING_RM)
1211 ENCODING("i8mem", ENCODING_RM)
1212 ENCODING("shmem", ENCODING_RM)
1213 ENCODING("ssmem", ENCODING_RM)
1214 ENCODING("sdmem", ENCODING_RM)
1215 ENCODING("f128mem", ENCODING_RM)
1216 ENCODING("f256mem", ENCODING_RM)
1217 ENCODING("f512mem", ENCODING_RM)
1218 ENCODING("f64mem", ENCODING_RM)
1219 ENCODING("f32mem", ENCODING_RM)
1220 ENCODING("f16mem", ENCODING_RM)
1221 ENCODING("i128mem", ENCODING_RM)
1222 ENCODING("i256mem", ENCODING_RM)
1223 ENCODING("i512mem", ENCODING_RM)
1224 ENCODING("f80mem", ENCODING_RM)
1225 ENCODING("lea64_32mem", ENCODING_RM)
1226 ENCODING("lea64mem", ENCODING_RM)
1227 ENCODING("anymem", ENCODING_RM)
1228 ENCODING("opaquemem", ENCODING_RM)
1229 ENCODING("sibmem", ENCODING_SIB)
1230 ENCODING("vx64mem", ENCODING_VSIB)
1231 ENCODING("vx128mem", ENCODING_VSIB)
1232 ENCODING("vx256mem", ENCODING_VSIB)
1233 ENCODING("vy128mem", ENCODING_VSIB)
1234 ENCODING("vy256mem", ENCODING_VSIB)
1235 ENCODING("vx64xmem", ENCODING_VSIB)
1236 ENCODING("vx128xmem", ENCODING_VSIB)
1237 ENCODING("vx256xmem", ENCODING_VSIB)
1238 ENCODING("vy128xmem", ENCODING_VSIB)
1239 ENCODING("vy256xmem", ENCODING_VSIB)
1240 ENCODING("vy512xmem", ENCODING_VSIB)
1241 ENCODING("vz256mem", ENCODING_VSIB)
1242 ENCODING("vz512mem", ENCODING_VSIB)
1243 errs() << "Unhandled memory encoding " << s << "\n";
1244 llvm_unreachable("Unhandled memory encoding");
1245 }
1246
1247 OperandEncoding
relocationEncodingFromString(const std::string & s,uint8_t OpSize)1248 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1249 uint8_t OpSize) {
1250 if(OpSize != X86Local::OpSize16) {
1251 // For instructions without an OpSize prefix, a declared 16-bit register or
1252 // immediate encoding is special.
1253 ENCODING("i16imm", ENCODING_IW)
1254 }
1255 ENCODING("i16imm", ENCODING_Iv)
1256 ENCODING("i16i8imm", ENCODING_IB)
1257 ENCODING("i32imm", ENCODING_Iv)
1258 ENCODING("i32i8imm", ENCODING_IB)
1259 ENCODING("i64i32imm", ENCODING_ID)
1260 ENCODING("i64i8imm", ENCODING_IB)
1261 ENCODING("i8imm", ENCODING_IB)
1262 ENCODING("u8imm", ENCODING_IB)
1263 ENCODING("i16u8imm", ENCODING_IB)
1264 ENCODING("i32u8imm", ENCODING_IB)
1265 ENCODING("i64u8imm", ENCODING_IB)
1266 ENCODING("i64i32imm_brtarget", ENCODING_ID)
1267 ENCODING("i16imm_brtarget", ENCODING_IW)
1268 ENCODING("i32imm_brtarget", ENCODING_ID)
1269 ENCODING("brtarget32", ENCODING_ID)
1270 ENCODING("brtarget16", ENCODING_IW)
1271 ENCODING("brtarget8", ENCODING_IB)
1272 ENCODING("i64imm", ENCODING_IO)
1273 ENCODING("offset16_8", ENCODING_Ia)
1274 ENCODING("offset16_16", ENCODING_Ia)
1275 ENCODING("offset16_32", ENCODING_Ia)
1276 ENCODING("offset32_8", ENCODING_Ia)
1277 ENCODING("offset32_16", ENCODING_Ia)
1278 ENCODING("offset32_32", ENCODING_Ia)
1279 ENCODING("offset32_64", ENCODING_Ia)
1280 ENCODING("offset64_8", ENCODING_Ia)
1281 ENCODING("offset64_16", ENCODING_Ia)
1282 ENCODING("offset64_32", ENCODING_Ia)
1283 ENCODING("offset64_64", ENCODING_Ia)
1284 ENCODING("srcidx8", ENCODING_SI)
1285 ENCODING("srcidx16", ENCODING_SI)
1286 ENCODING("srcidx32", ENCODING_SI)
1287 ENCODING("srcidx64", ENCODING_SI)
1288 ENCODING("dstidx8", ENCODING_DI)
1289 ENCODING("dstidx16", ENCODING_DI)
1290 ENCODING("dstidx32", ENCODING_DI)
1291 ENCODING("dstidx64", ENCODING_DI)
1292 errs() << "Unhandled relocation encoding " << s << "\n";
1293 llvm_unreachable("Unhandled relocation encoding");
1294 }
1295
1296 OperandEncoding
opcodeModifierEncodingFromString(const std::string & s,uint8_t OpSize)1297 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1298 uint8_t OpSize) {
1299 ENCODING("GR32", ENCODING_Rv)
1300 ENCODING("GR64", ENCODING_RO)
1301 ENCODING("GR16", ENCODING_Rv)
1302 ENCODING("GR8", ENCODING_RB)
1303 ENCODING("ccode", ENCODING_CC)
1304 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1305 llvm_unreachable("Unhandled opcode modifier encoding");
1306 }
1307 #undef ENCODING
1308