1 //===- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp - X86 backend-*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This tablegen backend is responsible for emitting the X86 backend EVEX2VEX
10 /// compression tables.
11 ///
12 //===----------------------------------------------------------------------===//
13
14 #include "CodeGenInstruction.h"
15 #include "CodeGenTarget.h"
16 #include "X86RecognizableInstr.h"
17 #include "llvm/TableGen/Error.h"
18 #include "llvm/TableGen/TableGenBackend.h"
19
20 using namespace llvm;
21 using namespace X86Disassembler;
22
23 namespace {
24
25 class X86EVEX2VEXTablesEmitter {
26 RecordKeeper &Records;
27 CodeGenTarget Target;
28
29 // Hold all non-masked & non-broadcasted EVEX encoded instructions
30 std::vector<const CodeGenInstruction *> EVEXInsts;
31 // Hold all VEX encoded instructions. Divided into groups with same opcodes
32 // to make the search more efficient
33 std::map<uint64_t, std::vector<const CodeGenInstruction *>> VEXInsts;
34
35 typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *> Entry;
36 typedef std::pair<StringRef, StringRef> Predicate;
37
38 // Represent both compress tables
39 std::vector<Entry> EVEX2VEX128;
40 std::vector<Entry> EVEX2VEX256;
41 // Represent predicates of VEX instructions.
42 std::vector<Predicate> EVEX2VEXPredicates;
43
44 public:
X86EVEX2VEXTablesEmitter(RecordKeeper & R)45 X86EVEX2VEXTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
46
47 // run - Output X86 EVEX2VEX tables.
48 void run(raw_ostream &OS);
49
50 private:
51 // Prints the given table as a C++ array of type
52 // X86EvexToVexCompressTableEntry
53 void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
54 // Prints function which checks target feature specific predicate.
55 void printCheckPredicate(const std::vector<Predicate> &Predicates,
56 raw_ostream &OS);
57 };
58
printTable(const std::vector<Entry> & Table,raw_ostream & OS)59 void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
60 raw_ostream &OS) {
61 StringRef Size = (Table == EVEX2VEX128) ? "128" : "256";
62
63 OS << "// X86 EVEX encoded instructions that have a VEX " << Size
64 << " encoding\n"
65 << "// (table format: <EVEX opcode, VEX-" << Size << " opcode>).\n"
66 << "static const X86EvexToVexCompressTableEntry X86EvexToVex" << Size
67 << "CompressTable[] = {\n"
68 << " // EVEX scalar with corresponding VEX.\n";
69
70 // Print all entries added to the table
71 for (const auto &Pair : Table) {
72 OS << " { X86::" << Pair.first->TheDef->getName()
73 << ", X86::" << Pair.second->TheDef->getName() << " },\n";
74 }
75
76 OS << "};\n\n";
77 }
78
printCheckPredicate(const std::vector<Predicate> & Predicates,raw_ostream & OS)79 void X86EVEX2VEXTablesEmitter::printCheckPredicate(
80 const std::vector<Predicate> &Predicates, raw_ostream &OS) {
81 OS << "static bool CheckVEXInstPredicate"
82 << "(MachineInstr &MI, const X86Subtarget *Subtarget) {\n"
83 << " unsigned Opc = MI.getOpcode();\n"
84 << " switch (Opc) {\n"
85 << " default: return true;\n";
86 for (const auto &Pair : Predicates)
87 OS << " case X86::" << Pair.first << ": return " << Pair.second << ";\n";
88 OS << " }\n"
89 << "}\n\n";
90 }
91
92 // Return true if the 2 BitsInits are equal
93 // Calculates the integer value residing BitsInit object
getValueFromBitsInit(const BitsInit * B)94 static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
95 uint64_t Value = 0;
96 for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
97 if (BitInit *Bit = dyn_cast<BitInit>(B->getBit(i)))
98 Value |= uint64_t(Bit->getValue()) << i;
99 else
100 PrintFatalError("Invalid VectSize bit");
101 }
102 return Value;
103 }
104
105 // Function object - Operator() returns true if the given VEX instruction
106 // matches the EVEX instruction of this object.
107 class IsMatch {
108 const CodeGenInstruction *EVEXInst;
109
110 public:
IsMatch(const CodeGenInstruction * EVEXInst)111 IsMatch(const CodeGenInstruction *EVEXInst) : EVEXInst(EVEXInst) {}
112
operator ()(const CodeGenInstruction * VEXInst)113 bool operator()(const CodeGenInstruction *VEXInst) {
114 RecognizableInstrBase VEXRI(*VEXInst);
115 RecognizableInstrBase EVEXRI(*EVEXInst);
116 bool VEX_W = VEXRI.HasVEX_W;
117 bool EVEX_W = EVEXRI.HasVEX_W;
118 bool VEX_WIG = VEXRI.IgnoresVEX_W;
119 bool EVEX_WIG = EVEXRI.IgnoresVEX_W;
120 bool EVEX_W1_VEX_W0 = EVEXInst->TheDef->getValueAsBit("EVEX_W1_VEX_W0");
121
122 if (VEXRI.IsCodeGenOnly != EVEXRI.IsCodeGenOnly ||
123 // VEX/EVEX fields
124 VEXRI.OpPrefix != EVEXRI.OpPrefix || VEXRI.OpMap != EVEXRI.OpMap ||
125 VEXRI.HasVEX_4V != EVEXRI.HasVEX_4V ||
126 VEXRI.HasVEX_L != EVEXRI.HasVEX_L ||
127 // Match is allowed if either is VEX_WIG, or they match, or EVEX
128 // is VEX_W1X and VEX is VEX_W0.
129 (!(VEX_WIG || (!EVEX_WIG && EVEX_W == VEX_W) ||
130 (EVEX_W1_VEX_W0 && EVEX_W && !VEX_W))) ||
131 // Instruction's format
132 VEXRI.Form != EVEXRI.Form)
133 return false;
134
135 // This is needed for instructions with intrinsic version (_Int).
136 // Where the only difference is the size of the operands.
137 // For example: VUCOMISDZrm and Int_VUCOMISDrm
138 // Also for instructions that their EVEX version was upgraded to work with
139 // k-registers. For example VPCMPEQBrm (xmm output register) and
140 // VPCMPEQBZ128rm (k register output register).
141 for (unsigned i = 0, e = EVEXInst->Operands.size(); i < e; i++) {
142 Record *OpRec1 = EVEXInst->Operands[i].Rec;
143 Record *OpRec2 = VEXInst->Operands[i].Rec;
144
145 if (OpRec1 == OpRec2)
146 continue;
147
148 if (isRegisterOperand(OpRec1) && isRegisterOperand(OpRec2)) {
149 if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
150 return false;
151 } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
152 return false;
153 } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
154 if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type")) {
155 return false;
156 }
157 } else
158 return false;
159 }
160
161 return true;
162 }
163 };
164
run(raw_ostream & OS)165 void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
166 auto getPredicates = [&](const CodeGenInstruction *Inst) {
167 std::vector<Record *> PredicatesRecords =
168 Inst->TheDef->getValueAsListOfDefs("Predicates");
169 // Currently we only do AVX related checks and assume each instruction
170 // has one and only one AVX related predicates.
171 for (unsigned i = 0, e = PredicatesRecords.size(); i != e; ++i)
172 if (PredicatesRecords[i]->getName().startswith("HasAVX"))
173 return PredicatesRecords[i]->getValueAsString("CondString");
174 llvm_unreachable(
175 "Instruction with checkPredicate set must have one predicate!");
176 };
177
178 emitSourceFileHeader("X86 EVEX2VEX tables", OS);
179
180 ArrayRef<const CodeGenInstruction *> NumberedInstructions =
181 Target.getInstructionsByEnumValue();
182
183 for (const CodeGenInstruction *Inst : NumberedInstructions) {
184 const Record *Def = Inst->TheDef;
185 // Filter non-X86 instructions.
186 if (!Def->isSubClassOf("X86Inst"))
187 continue;
188 RecognizableInstrBase RI(*Inst);
189
190 // Add VEX encoded instructions to one of VEXInsts vectors according to
191 // it's opcode.
192 if (RI.Encoding == X86Local::VEX)
193 VEXInsts[RI.Opcode].push_back(Inst);
194 // Add relevant EVEX encoded instructions to EVEXInsts
195 else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_B &&
196 !RI.HasEVEX_L2 && !Def->getValueAsBit("notEVEX2VEXConvertible"))
197 EVEXInsts.push_back(Inst);
198 }
199
200 for (const CodeGenInstruction *EVEXInst : EVEXInsts) {
201 uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
202 getValueAsBitsInit("Opcode"));
203 // For each EVEX instruction look for a VEX match in the appropriate vector
204 // (instructions with the same opcode) using function object IsMatch.
205 // Allow EVEX2VEXOverride to explicitly specify a match.
206 const CodeGenInstruction *VEXInst = nullptr;
207 if (!EVEXInst->TheDef->isValueUnset("EVEX2VEXOverride")) {
208 StringRef AltInstStr =
209 EVEXInst->TheDef->getValueAsString("EVEX2VEXOverride");
210 Record *AltInstRec = Records.getDef(AltInstStr);
211 assert(AltInstRec && "EVEX2VEXOverride instruction not found!");
212 VEXInst = &Target.getInstruction(AltInstRec);
213 } else {
214 auto Match = llvm::find_if(VEXInsts[Opcode], IsMatch(EVEXInst));
215 if (Match != VEXInsts[Opcode].end())
216 VEXInst = *Match;
217 }
218
219 if (!VEXInst)
220 continue;
221
222 // In case a match is found add new entry to the appropriate table
223 if (EVEXInst->TheDef->getValueAsBit("hasVEX_L"))
224 EVEX2VEX256.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,1}
225 else
226 EVEX2VEX128.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,0}
227
228 // Adding predicate check to EVEX2VEXPredicates table when needed.
229 if (VEXInst->TheDef->getValueAsBit("checkVEXPredicate"))
230 EVEX2VEXPredicates.push_back(
231 std::make_pair(EVEXInst->TheDef->getName(), getPredicates(VEXInst)));
232 }
233
234 // Print both tables
235 printTable(EVEX2VEX128, OS);
236 printTable(EVEX2VEX256, OS);
237 // Print CheckVEXInstPredicate function.
238 printCheckPredicate(EVEX2VEXPredicates, OS);
239 }
240 }
241
242 namespace llvm {
EmitX86EVEX2VEXTables(RecordKeeper & RK,raw_ostream & OS)243 void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS) {
244 X86EVEX2VEXTablesEmitter(RK).run(OS);
245 }
246 }
247