1 //===- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp - X86 backend-*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This tablegen backend is responsible for emitting the X86 backend EVEX2VEX
10 /// compression tables.
11 ///
12 //===----------------------------------------------------------------------===//
13
14 #include "CodeGenTarget.h"
15 #include "llvm/TableGen/Error.h"
16 #include "llvm/TableGen/TableGenBackend.h"
17
18 using namespace llvm;
19
20 namespace {
21
22 class X86EVEX2VEXTablesEmitter {
23 RecordKeeper &Records;
24 CodeGenTarget Target;
25
26 // Hold all non-masked & non-broadcasted EVEX encoded instructions
27 std::vector<const CodeGenInstruction *> EVEXInsts;
28 // Hold all VEX encoded instructions. Divided into groups with same opcodes
29 // to make the search more efficient
30 std::map<uint64_t, std::vector<const CodeGenInstruction *>> VEXInsts;
31
32 typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *> Entry;
33 typedef std::pair<StringRef, StringRef> Predicate;
34
35 // Represent both compress tables
36 std::vector<Entry> EVEX2VEX128;
37 std::vector<Entry> EVEX2VEX256;
38 // Represent predicates of VEX instructions.
39 std::vector<Predicate> EVEX2VEXPredicates;
40
41 public:
X86EVEX2VEXTablesEmitter(RecordKeeper & R)42 X86EVEX2VEXTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
43
44 // run - Output X86 EVEX2VEX tables.
45 void run(raw_ostream &OS);
46
47 private:
48 // Prints the given table as a C++ array of type
49 // X86EvexToVexCompressTableEntry
50 void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
51 // Prints function which checks target feature specific predicate.
52 void printCheckPredicate(const std::vector<Predicate> &Predicates,
53 raw_ostream &OS);
54 };
55
printTable(const std::vector<Entry> & Table,raw_ostream & OS)56 void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
57 raw_ostream &OS) {
58 StringRef Size = (Table == EVEX2VEX128) ? "128" : "256";
59
60 OS << "// X86 EVEX encoded instructions that have a VEX " << Size
61 << " encoding\n"
62 << "// (table format: <EVEX opcode, VEX-" << Size << " opcode>).\n"
63 << "static const X86EvexToVexCompressTableEntry X86EvexToVex" << Size
64 << "CompressTable[] = {\n"
65 << " // EVEX scalar with corresponding VEX.\n";
66
67 // Print all entries added to the table
68 for (auto Pair : Table) {
69 OS << " { X86::" << Pair.first->TheDef->getName()
70 << ", X86::" << Pair.second->TheDef->getName() << " },\n";
71 }
72
73 OS << "};\n\n";
74 }
75
printCheckPredicate(const std::vector<Predicate> & Predicates,raw_ostream & OS)76 void X86EVEX2VEXTablesEmitter::printCheckPredicate(
77 const std::vector<Predicate> &Predicates, raw_ostream &OS) {
78 OS << "static bool CheckVEXInstPredicate"
79 << "(MachineInstr &MI, const X86Subtarget *Subtarget) {\n"
80 << " unsigned Opc = MI.getOpcode();\n"
81 << " switch (Opc) {\n"
82 << " default: return true;\n";
83 for (auto Pair : Predicates)
84 OS << " case X86::" << Pair.first << ": return " << Pair.second << ";\n";
85 OS << " }\n"
86 << "}\n\n";
87 }
88
89 // Return true if the 2 BitsInits are equal
90 // Calculates the integer value residing BitsInit object
getValueFromBitsInit(const BitsInit * B)91 static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
92 uint64_t Value = 0;
93 for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
94 if (BitInit *Bit = dyn_cast<BitInit>(B->getBit(i)))
95 Value |= uint64_t(Bit->getValue()) << i;
96 else
97 PrintFatalError("Invalid VectSize bit");
98 }
99 return Value;
100 }
101
102 // Function object - Operator() returns true if the given VEX instruction
103 // matches the EVEX instruction of this object.
104 class IsMatch {
105 const CodeGenInstruction *EVEXInst;
106
107 public:
IsMatch(const CodeGenInstruction * EVEXInst)108 IsMatch(const CodeGenInstruction *EVEXInst) : EVEXInst(EVEXInst) {}
109
operator ()(const CodeGenInstruction * VEXInst)110 bool operator()(const CodeGenInstruction *VEXInst) {
111 Record *RecE = EVEXInst->TheDef;
112 Record *RecV = VEXInst->TheDef;
113 bool EVEX_W = RecE->getValueAsBit("HasVEX_W");
114 bool VEX_W = RecV->getValueAsBit("HasVEX_W");
115 bool VEX_WIG = RecV->getValueAsBit("IgnoresVEX_W");
116 bool EVEX_WIG = RecE->getValueAsBit("IgnoresVEX_W");
117 bool EVEX_W1_VEX_W0 = RecE->getValueAsBit("EVEX_W1_VEX_W0");
118
119 if (RecV->getValueAsDef("OpEnc")->getName().str() != "EncVEX" ||
120 RecV->getValueAsBit("isCodeGenOnly") != RecE->getValueAsBit("isCodeGenOnly") ||
121 // VEX/EVEX fields
122 RecV->getValueAsDef("OpPrefix") != RecE->getValueAsDef("OpPrefix") ||
123 RecV->getValueAsDef("OpMap") != RecE->getValueAsDef("OpMap") ||
124 RecV->getValueAsBit("hasVEX_4V") != RecE->getValueAsBit("hasVEX_4V") ||
125 RecV->getValueAsBit("hasEVEX_L2") != RecE->getValueAsBit("hasEVEX_L2") ||
126 RecV->getValueAsBit("hasVEX_L") != RecE->getValueAsBit("hasVEX_L") ||
127 // Match is allowed if either is VEX_WIG, or they match, or EVEX
128 // is VEX_W1X and VEX is VEX_W0.
129 (!(VEX_WIG || (!EVEX_WIG && EVEX_W == VEX_W) ||
130 (EVEX_W1_VEX_W0 && EVEX_W && !VEX_W))) ||
131 // Instruction's format
132 RecV->getValueAsDef("Form") != RecE->getValueAsDef("Form"))
133 return false;
134
135 // This is needed for instructions with intrinsic version (_Int).
136 // Where the only difference is the size of the operands.
137 // For example: VUCOMISDZrm and Int_VUCOMISDrm
138 // Also for instructions that their EVEX version was upgraded to work with
139 // k-registers. For example VPCMPEQBrm (xmm output register) and
140 // VPCMPEQBZ128rm (k register output register).
141 for (unsigned i = 0, e = EVEXInst->Operands.size(); i < e; i++) {
142 Record *OpRec1 = EVEXInst->Operands[i].Rec;
143 Record *OpRec2 = VEXInst->Operands[i].Rec;
144
145 if (OpRec1 == OpRec2)
146 continue;
147
148 if (isRegisterOperand(OpRec1) && isRegisterOperand(OpRec2)) {
149 if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
150 return false;
151 } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
152 return false;
153 } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
154 if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type")) {
155 return false;
156 }
157 } else
158 return false;
159 }
160
161 return true;
162 }
163
164 private:
isRegisterOperand(const Record * Rec)165 static inline bool isRegisterOperand(const Record *Rec) {
166 return Rec->isSubClassOf("RegisterClass") ||
167 Rec->isSubClassOf("RegisterOperand");
168 }
169
isMemoryOperand(const Record * Rec)170 static inline bool isMemoryOperand(const Record *Rec) {
171 return Rec->isSubClassOf("Operand") &&
172 Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
173 }
174
isImmediateOperand(const Record * Rec)175 static inline bool isImmediateOperand(const Record *Rec) {
176 return Rec->isSubClassOf("Operand") &&
177 Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
178 }
179
getRegOperandSize(const Record * RegRec)180 static inline unsigned int getRegOperandSize(const Record *RegRec) {
181 if (RegRec->isSubClassOf("RegisterClass"))
182 return RegRec->getValueAsInt("Alignment");
183 if (RegRec->isSubClassOf("RegisterOperand"))
184 return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
185
186 llvm_unreachable("Register operand's size not known!");
187 }
188 };
189
run(raw_ostream & OS)190 void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
191 auto getPredicates = [&](const CodeGenInstruction *Inst) {
192 std::vector<Record *> PredicatesRecords =
193 Inst->TheDef->getValueAsListOfDefs("Predicates");
194 // Currently we only do AVX related checks and assume each instruction
195 // has one and only one AVX related predicates.
196 for (unsigned i = 0, e = PredicatesRecords.size(); i != e; ++i)
197 if (PredicatesRecords[i]->getName().startswith("HasAVX"))
198 return PredicatesRecords[i]->getValueAsString("CondString");
199 llvm_unreachable(
200 "Instruction with checkPredicate set must have one predicate!");
201 };
202
203 emitSourceFileHeader("X86 EVEX2VEX tables", OS);
204
205 ArrayRef<const CodeGenInstruction *> NumberedInstructions =
206 Target.getInstructionsByEnumValue();
207
208 for (const CodeGenInstruction *Inst : NumberedInstructions) {
209 // Filter non-X86 instructions.
210 if (!Inst->TheDef->isSubClassOf("X86Inst"))
211 continue;
212
213 // Add VEX encoded instructions to one of VEXInsts vectors according to
214 // it's opcode.
215 if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
216 uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
217 getValueAsBitsInit("Opcode"));
218 VEXInsts[Opcode].push_back(Inst);
219 }
220 // Add relevant EVEX encoded instructions to EVEXInsts
221 else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
222 !Inst->TheDef->getValueAsBit("hasEVEX_K") &&
223 !Inst->TheDef->getValueAsBit("hasEVEX_B") &&
224 !Inst->TheDef->getValueAsBit("hasEVEX_L2") &&
225 !Inst->TheDef->getValueAsBit("notEVEX2VEXConvertible"))
226 EVEXInsts.push_back(Inst);
227 }
228
229 for (const CodeGenInstruction *EVEXInst : EVEXInsts) {
230 uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
231 getValueAsBitsInit("Opcode"));
232 // For each EVEX instruction look for a VEX match in the appropriate vector
233 // (instructions with the same opcode) using function object IsMatch.
234 // Allow EVEX2VEXOverride to explicitly specify a match.
235 const CodeGenInstruction *VEXInst = nullptr;
236 if (!EVEXInst->TheDef->isValueUnset("EVEX2VEXOverride")) {
237 StringRef AltInstStr =
238 EVEXInst->TheDef->getValueAsString("EVEX2VEXOverride");
239 Record *AltInstRec = Records.getDef(AltInstStr);
240 assert(AltInstRec && "EVEX2VEXOverride instruction not found!");
241 VEXInst = &Target.getInstruction(AltInstRec);
242 } else {
243 auto Match = llvm::find_if(VEXInsts[Opcode], IsMatch(EVEXInst));
244 if (Match != VEXInsts[Opcode].end())
245 VEXInst = *Match;
246 }
247
248 if (!VEXInst)
249 continue;
250
251 // In case a match is found add new entry to the appropriate table
252 if (EVEXInst->TheDef->getValueAsBit("hasVEX_L"))
253 EVEX2VEX256.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,1}
254 else
255 EVEX2VEX128.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,0}
256
257 // Adding predicate check to EVEX2VEXPredicates table when needed.
258 if (VEXInst->TheDef->getValueAsBit("checkVEXPredicate"))
259 EVEX2VEXPredicates.push_back(
260 std::make_pair(EVEXInst->TheDef->getName(), getPredicates(VEXInst)));
261 }
262
263 // Print both tables
264 printTable(EVEX2VEX128, OS);
265 printTable(EVEX2VEX256, OS);
266 // Print CheckVEXInstPredicate function.
267 printCheckPredicate(EVEX2VEXPredicates, OS);
268 }
269 }
270
271 namespace llvm {
EmitX86EVEX2VEXTables(RecordKeeper & RK,raw_ostream & OS)272 void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS) {
273 X86EVEX2VEXTablesEmitter(RK).run(OS);
274 }
275 }
276