1//===-- VOPCInstructions.td - Vector Instruction Definitions --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Encodings 11//===----------------------------------------------------------------------===// 12 13class VOPCe <bits<8> op> : Enc32 { 14 bits<9> src0; 15 bits<8> src1; 16 17 let Inst{8-0} = src0; 18 let Inst{16-9} = src1; 19 let Inst{24-17} = op; 20 let Inst{31-25} = 0x3e; 21} 22 23class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> { 24 bits<8> src1; 25 26 let Inst{8-0} = 0xf9; // sdwa 27 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 28 let Inst{24-17} = op; 29 let Inst{31-25} = 0x3e; // encoding 30} 31 32class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> { 33 bits<9> src1; 34 35 let Inst{8-0} = 0xf9; // sdwa 36 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 37 let Inst{24-17} = op; 38 let Inst{31-25} = 0x3e; // encoding 39 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr 40} 41 42 43//===----------------------------------------------------------------------===// 44// VOPC classes 45//===----------------------------------------------------------------------===// 46 47// VOPC instructions are a special case because for the 32-bit 48// encoding, we want to display the implicit vcc write as if it were 49// an explicit $dst. 50class VOPC_Profile<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> : 51 VOPProfile <[i1, vt0, vt1, untyped]> { 52 // We want to exclude instructions with 64bit operands 53 let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret; 54 let Asm32 = "$src0, $src1"; 55 56 let AsmDPP = !if (HasModifiers, 57 "$src0_modifiers, $src1_modifiers " 58 "$dpp_ctrl$row_mask$bank_mask$bound_ctrl", 59 "$src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"); 60 let AsmDPP8 = "$src0, $src1 $dpp8$fi"; 61 let AsmDPP16 = AsmDPP#"$fi"; 62 // VOPC DPP Instructions do not need an old operand 63 let TieRegDPP = ""; 64 let InsDPP = getInsDPP<VOPDstOperand<Src0DPP.RegClass>, Src0DPP, Src1DPP, Src2DPP, 65 NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, 66 Src2ModDPP, 0/*HasOld*/>.ret; 67 let InsDPP16 = getInsDPP16<VOPDstOperand<Src0DPP.RegClass>, Src0DPP, Src1DPP, Src2DPP, 68 NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, 69 Src2ModDPP, 0/*HasOld*/>.ret; 70 let InsDPP8 = getInsDPP8<VOPDstOperand<Src0DPP.RegClass>, Src0DPP, Src1DPP, Src2DPP, 71 NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, 72 Src2ModDPP, 0/*HasOld*/>.ret; 73 74 // The destination for 32-bit encoding is implicit. 75 let HasDst32 = 0; 76 // VOPC disallows dst_sel and dst_unused as they have no effect on destination 77 let EmitDstSel = 0; 78 let Outs64 = (outs VOPDstS64orS32:$sdst); 79 let OutsVOP3DPP = Outs64; 80 let OutsVOP3DPP8 = Outs64; 81 let InsVOP3DPP = getInsVOP3DPP<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret; 82 let InsVOP3DPP16 = getInsVOP3DPP16<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret; 83 let InsVOP3DPP8 = getInsVOP3DPP8<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret; 84 list<SchedReadWrite> Schedule = sched; 85} 86 87multiclass VOPC_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> { 88 def NAME : VOPC_Profile<sched, vt0, vt1>; 89 def _t16 : VOPC_Profile<sched, vt0, vt1> { 90 let IsTrue16 = 1; 91 let IsRealTrue16 = 1; 92 let HasOpSel = 1; 93 let HasModifiers = 1; // All instructions at least have OpSel 94 let DstRC = getVALUDstForVT<DstVT, 1 /*IsTrue16*/, 0 /*IsVOP3Encoding*/>.ret; 95 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 96 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 97 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 98 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 99 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 100 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret; 101 let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0/*IsFake16*/>.ret; 102 let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0/*IsFake16*/>.ret; 103 let Src0VOP3DPP = VGPRSrc_16; 104 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret; 105 let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret; 106 107 let DstRC64 = getVALUDstForVT<DstVT, 1/*IsTrue16*/, 1/*IsVOP3Encoding*/>.ret; 108 let Src0RC64 = getVOP3SrcForVT<Src0VT, 1/*IsTrue16*/>.ret; 109 let Src1RC64 = getVOP3SrcForVT<Src1VT, 1/*IsTrue16*/>.ret; 110 let Src2RC64 = getVOP3SrcForVT<Src2VT, 1/*IsTrue16*/>.ret; 111 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 112 let Src1Mod = getSrcMod<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 113 let Src2Mod = getSrcMod<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 114 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret; 115 let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 0/*IsFake16*/>.ret; 116 let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 0/*IsFake16*/>.ret; 117 } 118 def _fake16: VOPC_Profile<sched, vt0, vt1> { 119 let IsTrue16 = 1; 120 let DstRC = getVALUDstForVT_fake16<DstVT>.ret; 121 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 122 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 123 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 124 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 125 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 126 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret; 127 let Src1ModDPP = getSrcModDPP_t16<Src1VT, 1/*IsFake16*/>.ret; 128 let Src2ModDPP = getSrcModDPP_t16<Src2VT, 1/*IsFake16*/>.ret; 129 let Src0VOP3DPP = VGPRSrc_32; 130 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret; 131 let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret; 132 133 let DstRC64 = getVALUDstForVT<DstVT>.ret; 134 let Src0RC64 = getVOP3SrcForVT<Src0VT, 0/*IsTrue16*/>.ret; 135 let Src1RC64 = getVOP3SrcForVT<Src1VT, 0/*IsTrue16*/>.ret; 136 let Src2RC64 = getVOP3SrcForVT<Src2VT, 0/*IsTrue16*/>.ret; 137 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 138 let Src1Mod = getSrcMod<Src1VT, 0/*IsTrue16*/, 1/*IsFake16*/>.ret; 139 let Src2Mod = getSrcMod<Src2VT, 0/*IsTrue16*/, 1/*IsFake16*/>.ret; 140 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 1/*IsFake16*/>.ret; 141 let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 1/*IsFake16*/>.ret; 142 let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 1/*IsFake16*/>.ret; 143 } 144} 145 146class VOPC_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt0, 147 ValueType vt1 = vt0> : 148 VOPC_Profile<sched, vt0, vt1> { 149 let Outs64 = (outs ); 150 let OutsVOP3DPP = Outs64; 151 let OutsVOP3DPP8 = Outs64; 152 let OutsSDWA = (outs ); 153 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 154 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 155 src0_sel:$src0_sel, src1_sel:$src1_sel); 156 let HasDst = 0; 157 let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel"; 158 let EmitDst = 0; 159} 160 161multiclass VOPC_NoSdst_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> { 162 def NAME : VOPC_NoSdst_Profile<sched, vt0, vt1>; 163 def _t16 : VOPC_NoSdst_Profile<sched, vt0, vt1> { 164 let IsTrue16 = 1; 165 let IsRealTrue16 = 1; 166 let HasOpSel = 1; 167 let HasModifiers = 1; // All instructions at least have OpSel 168 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 169 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 170 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 171 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 172 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 173 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret; 174 let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0/*IsFake16*/>.ret; 175 let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0/*IsFake16*/>.ret; 176 let Src0VOP3DPP = VGPRSrc_16; 177 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret; 178 let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret; 179 180 let Src0RC64 = getVOP3SrcForVT<Src0VT, 1/*IsTrue16*/>.ret; 181 let Src1RC64 = getVOP3SrcForVT<Src1VT, 1/*IsTrue16*/>.ret; 182 let Src2RC64 = getVOP3SrcForVT<Src2VT, 1/*IsTrue16*/>.ret; 183 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 184 let Src1Mod = getSrcMod<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 185 let Src2Mod = getSrcMod<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 186 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret; 187 let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 0/*IsFake16*/>.ret; 188 let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 0/*IsFake16*/>.ret; 189 } 190 def _fake16 : VOPC_NoSdst_Profile<sched, vt0, vt1> { 191 let IsTrue16 = 1; 192 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 193 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 194 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 195 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 196 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 197 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret; 198 let Src1ModDPP = getSrcModDPP_t16<Src1VT, 1/*IsFake16*/>.ret; 199 let Src2ModDPP = getSrcModDPP_t16<Src2VT, 1/*IsFake16*/>.ret; 200 let Src0VOP3DPP = VGPRSrc_32; 201 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret; 202 let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret; 203 204 let Src0RC64 = getVOP3SrcForVT<Src0VT, 0/*IsTrue16*/>.ret; 205 let Src1RC64 = getVOP3SrcForVT<Src1VT, 0/*IsTrue16*/>.ret; 206 let Src2RC64 = getVOP3SrcForVT<Src2VT, 0/*IsTrue16*/>.ret; 207 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 208 let Src1Mod = getSrcMod<Src1VT, 0/*IsTrue16*/, 1/*IsFake16*/>.ret; 209 let Src2Mod = getSrcMod<Src2VT, 0/*IsTrue16*/, 1/*IsFake16*/>.ret; 210 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 1/*IsFake16*/>.ret; 211 let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 1/*IsFake16*/>.ret; 212 let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 1/*IsFake16*/>.ret; 213 } 214} 215 216class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[], 217 bit DefVcc = 1> : 218 InstSI<(outs), P.Ins32, "", pattern>, 219 VOP <opName>, 220 SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> { 221 222 let isPseudo = 1; 223 let isCodeGenOnly = 1; 224 let UseNamedOperandTable = 1; 225 226 string Mnemonic = opName; 227 string AsmOperands = P.Asm32; 228 229 let Size = 4; 230 let mayLoad = 0; 231 let mayStore = 0; 232 let hasSideEffects = 0; 233 234 let ReadsModeReg = P.Src0VT.isFP; 235 236 let VALU = 1; 237 let VOPC = 1; 238 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 239 let Defs = !if(DefVcc, [VCC], []); 240 241 VOPProfile Pfl = P; 242} 243 244class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily, string asm_name = ps.PseudoInstr> : 245 InstSI <ps.OutOperandList, ps.InOperandList, asm_name # " " # ps.AsmOperands, []>, 246 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 247 248 let VALU = 1; 249 let VOPC = 1; 250 let isPseudo = 0; 251 let isCodeGenOnly = 0; 252 253 let Constraints = ps.Constraints; 254 let DisableEncoding = ps.DisableEncoding; 255 256 // copy relevant pseudo op flags 257 let SubtargetPredicate = ps.SubtargetPredicate; 258 let True16Predicate = ps.True16Predicate; 259 let OtherPredicates = ps.OtherPredicates; 260 let AsmMatchConverter = ps.AsmMatchConverter; 261 let Constraints = ps.Constraints; 262 let DisableEncoding = ps.DisableEncoding; 263 let TSFlags = ps.TSFlags; 264 let UseNamedOperandTable = ps.UseNamedOperandTable; 265 let Uses = ps.Uses; 266 let Defs = ps.Defs; 267 let SchedRW = ps.SchedRW; 268 let mayLoad = ps.mayLoad; 269 let mayStore = ps.mayStore; 270 let isConvergent = ps.isConvergent; 271} 272 273class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 274 VOP_SDWA_Pseudo <OpName, P, pattern> { 275 let AsmMatchConverter = "cvtSdwaVOPC"; 276} 277 278// This class is used only with VOPC instructions. Use $sdst for out operand 279class VOPCInstAlias <VOP3_Pseudo ps, Instruction inst, 280 string Asm32 = ps.Pfl.Asm32, string real_name = ps.OpName, 281 VOPProfile p = ps.Pfl> : 282 InstAlias <real_name#" "#Asm32, (inst)>, PredicateControl { 283 284 field bit isCompare; 285 field bit isCommutable; 286 287 let ResultInst = 288 !if (p.HasDst32, 289 !if (!eq(p.NumSrcArgs, 0), 290 // 1 dst, 0 src 291 (inst p.DstRC:$sdst), 292 !if (!eq(p.NumSrcArgs, 1), 293 // 1 dst, 1 src 294 (inst p.DstRC:$sdst, p.Src0RC32:$src0), 295 !if (!eq(p.NumSrcArgs, 2), 296 // 1 dst, 2 src 297 (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1), 298 // else - unreachable 299 (inst)))), 300 // else 301 !if (!eq(p.NumSrcArgs, 2), 302 // 0 dst, 2 src 303 (inst p.Src0RC32:$src0, p.Src1RC32:$src1), 304 !if (!eq(p.NumSrcArgs, 1), 305 // 0 dst, 1 src 306 (inst p.Src0RC32:$src1), 307 // else 308 // 0 dst, 0 src 309 (inst)))); 310 311 let AsmVariantName = AMDGPUAsmVariants.Default; 312 let SubtargetPredicate = AssemblerPredicate; 313 314 string DecoderNamespace; // dummy 315} 316 317multiclass VOPCInstAliases <string old_name, string Arch, string real_name = old_name, string mnemonic_from = real_name> { 318 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 319 !cast<Instruction>(real_name#"_e32_"#Arch), 320 !cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 321 mnemonic_from>; 322 let WaveSizePredicate = isWave32 in { 323 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 324 !cast<Instruction>(real_name#"_e32_"#Arch), 325 "vcc_lo, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 326 mnemonic_from>; 327 } 328 let WaveSizePredicate = isWave64 in { 329 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 330 !cast<Instruction>(real_name#"_e32_"#Arch), 331 "vcc, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 332 mnemonic_from>; 333 } 334} 335 336multiclass VOPCXInstAliases <string old_name, string Arch, string real_name = old_name, string mnemonic_from = real_name> { 337 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 338 !cast<Instruction>(real_name#"_e32_"#Arch), 339 !cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 340 mnemonic_from>; 341} 342 343class getVOPCPat64 <SDPatternOperator cond, VOPProfile P> : LetDummies { 344 list<dag> ret = !if(P.HasModifiers, 345 [(set i1:$sdst, 346 (setcc (P.Src0VT 347 !if(P.HasOMod, 348 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 349 !if(P.HasClamp, 350 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp), 351 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers)))), 352 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 353 cond))], 354 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]); 355} 356 357class VCMPXNoSDstTable <bit has_sdst, string Name> { 358 bit HasSDst = has_sdst; 359 string NoSDstOp = Name; 360} 361 362class VCMPVCMPXTable <string Name> { 363 bit IsVCMPX = 0; 364 string VCMPOp = Name; 365} 366 367multiclass VOPC_Pseudos <string opName, 368 VOPC_Profile P, 369 SDPatternOperator cond = COND_NULL, 370 string revOp = opName, 371 bit DefExec = 0> { 372 373 def _e32 : VOPC_Pseudo <opName, P>, 374 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>, 375 VCMPXNoSDstTable<1, opName#"_e32">, 376 VCMPVCMPXTable<opName#"_e32"> { 377 let Defs = !if(DefExec, [VCC, EXEC], [VCC]); 378 let SchedRW = P.Schedule; 379 let isConvergent = DefExec; 380 let isCompare = 1; 381 let isCommutable = 1; 382 } 383 384 def _e64 : VOP3_Pseudo<opName, P, getVOPCPat64<cond, P>.ret, /*IsVOP3P*/false, P.HasOpSel>, 385 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>, 386 VCMPXNoSDstTable<1, opName#"_e64">, 387 VCMPVCMPXTable<opName#"_e64"> { 388 let Defs = !if(DefExec, [EXEC], []); 389 let SchedRW = P.Schedule; 390 let isCompare = 1; 391 let isCommutable = 1; 392 let AsmMatchConverter = 393 !if (P.HasOpSel, "cvtVOP3OpSel", 394 !if (!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), "cvtVOP3", 395 "")); 396 } 397 398 if P.HasExtSDWA then 399 def _sdwa : VOPC_SDWA_Pseudo <opName, P> { 400 let Defs = !if(DefExec, [EXEC], []); 401 let SchedRW = P.Schedule; 402 let isConvergent = DefExec; 403 let isCompare = 1; 404 } 405 406 let SubtargetPredicate = isGFX11Plus in { 407 if P.HasExtDPP then 408 def _e32_dpp : VOP_DPP_Pseudo<opName, P> { 409 let Defs = !if(DefExec, [VCC, EXEC], [VCC]); 410 let SchedRW = P.Schedule; 411 let isConvergent = DefExec; 412 let isCompare = 1; 413 let VOPC = 1; 414 let Constraints = ""; 415 } 416 if P.HasExtVOP3DPP then 417 def _e64_dpp : VOP3_DPP_Pseudo<opName, P> { 418 let Defs = !if(DefExec, [EXEC], []); 419 let SchedRW = P.Schedule; 420 let isCompare = 1; 421 let Constraints = ""; 422 } 423 } // end SubtargetPredicate = isGFX11Plus 424 425} 426 427let SubtargetPredicate = HasSdstCMPX in { 428multiclass VOPCX_Pseudos <string opName, 429 VOPC_Profile P, VOPC_Profile P_NoSDst, 430 SDPatternOperator cond = COND_NULL, 431 string revOp = opName> : 432 VOPC_Pseudos <opName, P, cond, revOp, 1> { 433 434 def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>, 435 Commutable_REV<revOp#"_nosdst_e32", !eq(revOp, opName)>, 436 VCMPXNoSDstTable<0, opName#"_e32">, 437 VCMPVCMPXTable<!subst("v_cmpx", "v_cmp", opName#"_e32")> { 438 let Defs = [EXEC]; 439 let SchedRW = P_NoSDst.Schedule; 440 let isConvergent = 1; 441 let isCompare = 1; 442 let isCommutable = 1; 443 let SubtargetPredicate = HasNoSdstCMPX; 444 let IsVCMPX = 1; 445 } 446 447 def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst, [], /*IsVOP3P*/false, P_NoSDst.HasOpSel>, 448 Commutable_REV<revOp#"_nosdst_e64", !eq(revOp, opName)>, 449 VCMPXNoSDstTable<0, opName#"_e64">, 450 VCMPVCMPXTable<!subst("v_cmpx", "v_cmp", opName#"_e64")> { 451 let Defs = [EXEC]; 452 let SchedRW = P_NoSDst.Schedule; 453 let isCompare = 1; 454 let isCommutable = 1; 455 let SubtargetPredicate = HasNoSdstCMPX; 456 let IsVCMPX = 1; 457 } 458 459 if P_NoSDst.HasExtSDWA then 460 def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> { 461 let Defs = [EXEC]; 462 let SchedRW = P_NoSDst.Schedule; 463 let isConvergent = 1; 464 let isCompare = 1; 465 let SubtargetPredicate = HasNoSdstCMPX; 466 } 467 468 let SubtargetPredicate = isGFX11Plus in { 469 if P.HasExtDPP then 470 def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 471 let Defs = [EXEC]; 472 let SchedRW = P_NoSDst.Schedule; 473 let isConvergent = 1; 474 let isCompare = 1; 475 let VOPC = 1; 476 let Constraints = ""; 477 } 478 if P.HasExtVOP3DPP then 479 def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 480 let Defs = [EXEC]; 481 let SchedRW = P_NoSDst.Schedule; 482 let isCompare = 1; 483 let Constraints = ""; 484 } 485 } // end SubtargetPredicate = isGFX11Plus 486} 487} // End SubtargetPredicate = HasSdstCMPX 488 489defm VOPC_I1_F16_F16 : VOPC_Profile_t16<[Write32Bit], f16>; 490def VOPC_I1_F32_F32 : VOPC_Profile<[Write32Bit], f32>; 491def VOPC_I1_F64_F64 : VOPC_Profile<[WriteDoubleAdd], f64>; 492defm VOPC_I1_I16_I16 : VOPC_Profile_t16<[Write32Bit], i16>; 493def VOPC_I1_I32_I32 : VOPC_Profile<[Write32Bit], i32>; 494def VOPC_I1_I64_I64 : VOPC_Profile<[Write64Bit], i64>; 495 496defm VOPC_F16_F16 : VOPC_NoSdst_Profile_t16<[Write32Bit], f16>; 497def VOPC_F32_F32 : VOPC_NoSdst_Profile<[Write32Bit], f32>; 498def VOPC_F64_F64 : VOPC_NoSdst_Profile<[Write64Bit], f64>; 499defm VOPC_I16_I16 : VOPC_NoSdst_Profile_t16<[Write32Bit], i16>; 500def VOPC_I32_I32 : VOPC_NoSdst_Profile<[Write32Bit], i32>; 501def VOPC_I64_I64 : VOPC_NoSdst_Profile<[Write64Bit], i64>; 502 503multiclass VOPC_F16 <string opName, SDPatternOperator cond = COND_NULL, 504 string revOp = opName> { 505 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 506 defm NAME : VOPC_Pseudos <opName, VOPC_I1_F16_F16, cond, revOp, 0>; 507 } 508 let True16Predicate = UseRealTrue16Insts in { 509 defm _t16 : VOPC_Pseudos <opName#"_t16", VOPC_I1_F16_F16_t16, cond, revOp#"_t16", 0>; 510 } 511 let True16Predicate = UseFakeTrue16Insts in { 512 defm _fake16 : VOPC_Pseudos <opName#"_fake16", VOPC_I1_F16_F16_fake16, cond, revOp#"_fake16", 0>; 513 } 514} 515 516multiclass VOPC_F32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 517 VOPC_Pseudos <opName, VOPC_I1_F32_F32, cond, revOp, 0>; 518 519multiclass VOPC_F64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 520 VOPC_Pseudos <opName, VOPC_I1_F64_F64, cond, revOp, 0>; 521 522multiclass VOPC_I16 <string opName, SDPatternOperator cond = COND_NULL, 523 string revOp = opName> { 524 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 525 defm NAME : VOPC_Pseudos <opName, VOPC_I1_I16_I16, cond, revOp, 0>; 526 } 527 let True16Predicate = UseRealTrue16Insts in { 528 defm _t16 : VOPC_Pseudos <opName#"_t16", VOPC_I1_I16_I16_t16, cond, revOp#"_t16", 0>; 529 } 530 let True16Predicate = UseFakeTrue16Insts in { 531 defm _fake16 : VOPC_Pseudos <opName#"_fake16", VOPC_I1_I16_I16_fake16, cond, revOp#"_fake16", 0>; 532 } 533} 534 535multiclass VOPC_I32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 536 VOPC_Pseudos <opName, VOPC_I1_I32_I32, cond, revOp, 0>; 537 538multiclass VOPC_I64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 539 VOPC_Pseudos <opName, VOPC_I1_I64_I64, cond, revOp, 0>; 540 541 542multiclass VOPCX_F16<string opName, string revOp = opName> { 543 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 544 defm NAME : VOPCX_Pseudos <opName, VOPC_I1_F16_F16, VOPC_F16_F16, COND_NULL, revOp>; 545 } 546 let True16Predicate = UseRealTrue16Insts in { 547 defm _t16 : VOPCX_Pseudos <opName#"_t16", VOPC_I1_F16_F16_t16, VOPC_F16_F16_t16, COND_NULL, revOp#"_t16">; 548 } 549 let True16Predicate = UseFakeTrue16Insts in { 550 defm _fake16 : VOPCX_Pseudos <opName#"_fake16", VOPC_I1_F16_F16_fake16, VOPC_F16_F16_fake16, COND_NULL, revOp#"_fake16">; 551 } 552} 553 554multiclass VOPCX_F32 <string opName, string revOp = opName> : 555 VOPCX_Pseudos <opName, VOPC_I1_F32_F32, VOPC_F32_F32, COND_NULL, revOp>; 556 557multiclass VOPCX_F64 <string opName, string revOp = opName> : 558 VOPCX_Pseudos <opName, VOPC_I1_F64_F64, VOPC_F64_F64, COND_NULL, revOp>; 559 560multiclass VOPCX_I16<string opName, string revOp = opName> { 561 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 562 defm NAME : VOPCX_Pseudos <opName, VOPC_I1_I16_I16, VOPC_I16_I16, COND_NULL, revOp>; 563 } 564 let True16Predicate = UseRealTrue16Insts in { 565 defm _t16 : VOPCX_Pseudos <opName#"_t16", VOPC_I1_I16_I16_t16, VOPC_I16_I16_t16, COND_NULL, revOp#"_t16">; 566 } 567 let True16Predicate = UseFakeTrue16Insts in { 568 defm _fake16 : VOPCX_Pseudos <opName#"_fake16", VOPC_I1_I16_I16_fake16, VOPC_I16_I16_fake16, COND_NULL, revOp#"_fake16">; 569 } 570} 571 572multiclass VOPCX_I32 <string opName, string revOp = opName> : 573 VOPCX_Pseudos <opName, VOPC_I1_I32_I32, VOPC_I32_I32, COND_NULL, revOp>; 574 575multiclass VOPCX_I64 <string opName, string revOp = opName> : 576 VOPCX_Pseudos <opName, VOPC_I1_I64_I64, VOPC_I64_I64, COND_NULL, revOp>; 577 578 579//===----------------------------------------------------------------------===// 580// Compare instructions 581//===----------------------------------------------------------------------===// 582 583defm V_CMP_F_F32 : VOPC_F32 <"v_cmp_f_f32">; 584defm V_CMP_LT_F32 : VOPC_F32 <"v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">; 585defm V_CMP_EQ_F32 : VOPC_F32 <"v_cmp_eq_f32", COND_OEQ>; 586defm V_CMP_LE_F32 : VOPC_F32 <"v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">; 587defm V_CMP_GT_F32 : VOPC_F32 <"v_cmp_gt_f32", COND_OGT>; 588defm V_CMP_LG_F32 : VOPC_F32 <"v_cmp_lg_f32", COND_ONE>; 589defm V_CMP_GE_F32 : VOPC_F32 <"v_cmp_ge_f32", COND_OGE>; 590defm V_CMP_O_F32 : VOPC_F32 <"v_cmp_o_f32", COND_O>; 591defm V_CMP_U_F32 : VOPC_F32 <"v_cmp_u_f32", COND_UO>; 592defm V_CMP_NGE_F32 : VOPC_F32 <"v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">; 593defm V_CMP_NLG_F32 : VOPC_F32 <"v_cmp_nlg_f32", COND_UEQ>; 594defm V_CMP_NGT_F32 : VOPC_F32 <"v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">; 595defm V_CMP_NLE_F32 : VOPC_F32 <"v_cmp_nle_f32", COND_UGT>; 596defm V_CMP_NEQ_F32 : VOPC_F32 <"v_cmp_neq_f32", COND_UNE>; 597defm V_CMP_NLT_F32 : VOPC_F32 <"v_cmp_nlt_f32", COND_UGE>; 598defm V_CMP_TRU_F32 : VOPC_F32 <"v_cmp_tru_f32">; 599 600defm V_CMPX_F_F32 : VOPCX_F32 <"v_cmpx_f_f32">; 601defm V_CMPX_LT_F32 : VOPCX_F32 <"v_cmpx_lt_f32", "v_cmpx_gt_f32">; 602defm V_CMPX_EQ_F32 : VOPCX_F32 <"v_cmpx_eq_f32">; 603defm V_CMPX_LE_F32 : VOPCX_F32 <"v_cmpx_le_f32", "v_cmpx_ge_f32">; 604defm V_CMPX_GT_F32 : VOPCX_F32 <"v_cmpx_gt_f32">; 605defm V_CMPX_LG_F32 : VOPCX_F32 <"v_cmpx_lg_f32">; 606defm V_CMPX_GE_F32 : VOPCX_F32 <"v_cmpx_ge_f32">; 607defm V_CMPX_O_F32 : VOPCX_F32 <"v_cmpx_o_f32">; 608defm V_CMPX_U_F32 : VOPCX_F32 <"v_cmpx_u_f32">; 609defm V_CMPX_NGE_F32 : VOPCX_F32 <"v_cmpx_nge_f32", "v_cmpx_nle_f32">; 610defm V_CMPX_NLG_F32 : VOPCX_F32 <"v_cmpx_nlg_f32">; 611defm V_CMPX_NGT_F32 : VOPCX_F32 <"v_cmpx_ngt_f32", "v_cmpx_nlt_f32">; 612defm V_CMPX_NLE_F32 : VOPCX_F32 <"v_cmpx_nle_f32">; 613defm V_CMPX_NEQ_F32 : VOPCX_F32 <"v_cmpx_neq_f32">; 614defm V_CMPX_NLT_F32 : VOPCX_F32 <"v_cmpx_nlt_f32">; 615defm V_CMPX_TRU_F32 : VOPCX_F32 <"v_cmpx_tru_f32">; 616 617defm V_CMP_F_F64 : VOPC_F64 <"v_cmp_f_f64">; 618defm V_CMP_LT_F64 : VOPC_F64 <"v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">; 619defm V_CMP_EQ_F64 : VOPC_F64 <"v_cmp_eq_f64", COND_OEQ>; 620defm V_CMP_LE_F64 : VOPC_F64 <"v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">; 621defm V_CMP_GT_F64 : VOPC_F64 <"v_cmp_gt_f64", COND_OGT>; 622defm V_CMP_LG_F64 : VOPC_F64 <"v_cmp_lg_f64", COND_ONE>; 623defm V_CMP_GE_F64 : VOPC_F64 <"v_cmp_ge_f64", COND_OGE>; 624defm V_CMP_O_F64 : VOPC_F64 <"v_cmp_o_f64", COND_O>; 625defm V_CMP_U_F64 : VOPC_F64 <"v_cmp_u_f64", COND_UO>; 626defm V_CMP_NGE_F64 : VOPC_F64 <"v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">; 627defm V_CMP_NLG_F64 : VOPC_F64 <"v_cmp_nlg_f64", COND_UEQ>; 628defm V_CMP_NGT_F64 : VOPC_F64 <"v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">; 629defm V_CMP_NLE_F64 : VOPC_F64 <"v_cmp_nle_f64", COND_UGT>; 630defm V_CMP_NEQ_F64 : VOPC_F64 <"v_cmp_neq_f64", COND_UNE>; 631defm V_CMP_NLT_F64 : VOPC_F64 <"v_cmp_nlt_f64", COND_UGE>; 632defm V_CMP_TRU_F64 : VOPC_F64 <"v_cmp_tru_f64">; 633 634defm V_CMPX_F_F64 : VOPCX_F64 <"v_cmpx_f_f64">; 635defm V_CMPX_LT_F64 : VOPCX_F64 <"v_cmpx_lt_f64", "v_cmpx_gt_f64">; 636defm V_CMPX_EQ_F64 : VOPCX_F64 <"v_cmpx_eq_f64">; 637defm V_CMPX_LE_F64 : VOPCX_F64 <"v_cmpx_le_f64", "v_cmpx_ge_f64">; 638defm V_CMPX_GT_F64 : VOPCX_F64 <"v_cmpx_gt_f64">; 639defm V_CMPX_LG_F64 : VOPCX_F64 <"v_cmpx_lg_f64">; 640defm V_CMPX_GE_F64 : VOPCX_F64 <"v_cmpx_ge_f64">; 641defm V_CMPX_O_F64 : VOPCX_F64 <"v_cmpx_o_f64">; 642defm V_CMPX_U_F64 : VOPCX_F64 <"v_cmpx_u_f64">; 643defm V_CMPX_NGE_F64 : VOPCX_F64 <"v_cmpx_nge_f64", "v_cmpx_nle_f64">; 644defm V_CMPX_NLG_F64 : VOPCX_F64 <"v_cmpx_nlg_f64">; 645defm V_CMPX_NGT_F64 : VOPCX_F64 <"v_cmpx_ngt_f64", "v_cmpx_nlt_f64">; 646defm V_CMPX_NLE_F64 : VOPCX_F64 <"v_cmpx_nle_f64">; 647defm V_CMPX_NEQ_F64 : VOPCX_F64 <"v_cmpx_neq_f64">; 648defm V_CMPX_NLT_F64 : VOPCX_F64 <"v_cmpx_nlt_f64">; 649defm V_CMPX_TRU_F64 : VOPCX_F64 <"v_cmpx_tru_f64">; 650 651let SubtargetPredicate = isGFX6GFX7 in { 652 653defm V_CMPS_F_F32 : VOPC_F32 <"v_cmps_f_f32">; 654defm V_CMPS_LT_F32 : VOPC_F32 <"v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">; 655defm V_CMPS_EQ_F32 : VOPC_F32 <"v_cmps_eq_f32">; 656defm V_CMPS_LE_F32 : VOPC_F32 <"v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">; 657defm V_CMPS_GT_F32 : VOPC_F32 <"v_cmps_gt_f32">; 658defm V_CMPS_LG_F32 : VOPC_F32 <"v_cmps_lg_f32">; 659defm V_CMPS_GE_F32 : VOPC_F32 <"v_cmps_ge_f32">; 660defm V_CMPS_O_F32 : VOPC_F32 <"v_cmps_o_f32">; 661defm V_CMPS_U_F32 : VOPC_F32 <"v_cmps_u_f32">; 662defm V_CMPS_NGE_F32 : VOPC_F32 <"v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">; 663defm V_CMPS_NLG_F32 : VOPC_F32 <"v_cmps_nlg_f32">; 664defm V_CMPS_NGT_F32 : VOPC_F32 <"v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">; 665defm V_CMPS_NLE_F32 : VOPC_F32 <"v_cmps_nle_f32">; 666defm V_CMPS_NEQ_F32 : VOPC_F32 <"v_cmps_neq_f32">; 667defm V_CMPS_NLT_F32 : VOPC_F32 <"v_cmps_nlt_f32">; 668defm V_CMPS_TRU_F32 : VOPC_F32 <"v_cmps_tru_f32">; 669 670defm V_CMPSX_F_F32 : VOPCX_F32 <"v_cmpsx_f_f32">; 671defm V_CMPSX_LT_F32 : VOPCX_F32 <"v_cmpsx_lt_f32", "v_cmpsx_gt_f32">; 672defm V_CMPSX_EQ_F32 : VOPCX_F32 <"v_cmpsx_eq_f32">; 673defm V_CMPSX_LE_F32 : VOPCX_F32 <"v_cmpsx_le_f32", "v_cmpsx_ge_f32">; 674defm V_CMPSX_GT_F32 : VOPCX_F32 <"v_cmpsx_gt_f32">; 675defm V_CMPSX_LG_F32 : VOPCX_F32 <"v_cmpsx_lg_f32">; 676defm V_CMPSX_GE_F32 : VOPCX_F32 <"v_cmpsx_ge_f32">; 677defm V_CMPSX_O_F32 : VOPCX_F32 <"v_cmpsx_o_f32">; 678defm V_CMPSX_U_F32 : VOPCX_F32 <"v_cmpsx_u_f32">; 679defm V_CMPSX_NGE_F32 : VOPCX_F32 <"v_cmpsx_nge_f32", "v_cmpsx_nle_f32">; 680defm V_CMPSX_NLG_F32 : VOPCX_F32 <"v_cmpsx_nlg_f32">; 681defm V_CMPSX_NGT_F32 : VOPCX_F32 <"v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">; 682defm V_CMPSX_NLE_F32 : VOPCX_F32 <"v_cmpsx_nle_f32">; 683defm V_CMPSX_NEQ_F32 : VOPCX_F32 <"v_cmpsx_neq_f32">; 684defm V_CMPSX_NLT_F32 : VOPCX_F32 <"v_cmpsx_nlt_f32">; 685defm V_CMPSX_TRU_F32 : VOPCX_F32 <"v_cmpsx_tru_f32">; 686 687defm V_CMPS_F_F64 : VOPC_F64 <"v_cmps_f_f64">; 688defm V_CMPS_LT_F64 : VOPC_F64 <"v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">; 689defm V_CMPS_EQ_F64 : VOPC_F64 <"v_cmps_eq_f64">; 690defm V_CMPS_LE_F64 : VOPC_F64 <"v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">; 691defm V_CMPS_GT_F64 : VOPC_F64 <"v_cmps_gt_f64">; 692defm V_CMPS_LG_F64 : VOPC_F64 <"v_cmps_lg_f64">; 693defm V_CMPS_GE_F64 : VOPC_F64 <"v_cmps_ge_f64">; 694defm V_CMPS_O_F64 : VOPC_F64 <"v_cmps_o_f64">; 695defm V_CMPS_U_F64 : VOPC_F64 <"v_cmps_u_f64">; 696defm V_CMPS_NGE_F64 : VOPC_F64 <"v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">; 697defm V_CMPS_NLG_F64 : VOPC_F64 <"v_cmps_nlg_f64">; 698defm V_CMPS_NGT_F64 : VOPC_F64 <"v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">; 699defm V_CMPS_NLE_F64 : VOPC_F64 <"v_cmps_nle_f64">; 700defm V_CMPS_NEQ_F64 : VOPC_F64 <"v_cmps_neq_f64">; 701defm V_CMPS_NLT_F64 : VOPC_F64 <"v_cmps_nlt_f64">; 702defm V_CMPS_TRU_F64 : VOPC_F64 <"v_cmps_tru_f64">; 703 704defm V_CMPSX_F_F64 : VOPCX_F64 <"v_cmpsx_f_f64">; 705defm V_CMPSX_LT_F64 : VOPCX_F64 <"v_cmpsx_lt_f64", "v_cmpsx_gt_f64">; 706defm V_CMPSX_EQ_F64 : VOPCX_F64 <"v_cmpsx_eq_f64">; 707defm V_CMPSX_LE_F64 : VOPCX_F64 <"v_cmpsx_le_f64", "v_cmpsx_ge_f64">; 708defm V_CMPSX_GT_F64 : VOPCX_F64 <"v_cmpsx_gt_f64">; 709defm V_CMPSX_LG_F64 : VOPCX_F64 <"v_cmpsx_lg_f64">; 710defm V_CMPSX_GE_F64 : VOPCX_F64 <"v_cmpsx_ge_f64">; 711defm V_CMPSX_O_F64 : VOPCX_F64 <"v_cmpsx_o_f64">; 712defm V_CMPSX_U_F64 : VOPCX_F64 <"v_cmpsx_u_f64">; 713defm V_CMPSX_NGE_F64 : VOPCX_F64 <"v_cmpsx_nge_f64", "v_cmpsx_nle_f64">; 714defm V_CMPSX_NLG_F64 : VOPCX_F64 <"v_cmpsx_nlg_f64">; 715defm V_CMPSX_NGT_F64 : VOPCX_F64 <"v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">; 716defm V_CMPSX_NLE_F64 : VOPCX_F64 <"v_cmpsx_nle_f64">; 717defm V_CMPSX_NEQ_F64 : VOPCX_F64 <"v_cmpsx_neq_f64">; 718defm V_CMPSX_NLT_F64 : VOPCX_F64 <"v_cmpsx_nlt_f64">; 719defm V_CMPSX_TRU_F64 : VOPCX_F64 <"v_cmpsx_tru_f64">; 720 721} // End SubtargetPredicate = isGFX6GFX7 722 723let SubtargetPredicate = Has16BitInsts in { 724 725defm V_CMP_F_F16 : VOPC_F16 <"v_cmp_f_f16">; 726defm V_CMP_LT_F16 : VOPC_F16 <"v_cmp_lt_f16", COND_OLT, "v_cmp_gt_f16">; 727defm V_CMP_EQ_F16 : VOPC_F16 <"v_cmp_eq_f16", COND_OEQ>; 728defm V_CMP_LE_F16 : VOPC_F16 <"v_cmp_le_f16", COND_OLE, "v_cmp_ge_f16">; 729defm V_CMP_GT_F16 : VOPC_F16 <"v_cmp_gt_f16", COND_OGT>; 730defm V_CMP_LG_F16 : VOPC_F16 <"v_cmp_lg_f16", COND_ONE>; 731defm V_CMP_GE_F16 : VOPC_F16 <"v_cmp_ge_f16", COND_OGE>; 732defm V_CMP_O_F16 : VOPC_F16 <"v_cmp_o_f16", COND_O>; 733defm V_CMP_U_F16 : VOPC_F16 <"v_cmp_u_f16", COND_UO>; 734defm V_CMP_NGE_F16 : VOPC_F16 <"v_cmp_nge_f16", COND_ULT, "v_cmp_nle_f16">; 735defm V_CMP_NLG_F16 : VOPC_F16 <"v_cmp_nlg_f16", COND_UEQ>; 736defm V_CMP_NGT_F16 : VOPC_F16 <"v_cmp_ngt_f16", COND_ULE, "v_cmp_nlt_f16">; 737defm V_CMP_NLE_F16 : VOPC_F16 <"v_cmp_nle_f16", COND_UGT>; 738defm V_CMP_NEQ_F16 : VOPC_F16 <"v_cmp_neq_f16", COND_UNE>; 739defm V_CMP_NLT_F16 : VOPC_F16 <"v_cmp_nlt_f16", COND_UGE>; 740defm V_CMP_TRU_F16 : VOPC_F16 <"v_cmp_tru_f16">; 741 742defm V_CMPX_F_F16 : VOPCX_F16 <"v_cmpx_f_f16">; 743defm V_CMPX_LT_F16 : VOPCX_F16 <"v_cmpx_lt_f16", "v_cmpx_gt_f16">; 744defm V_CMPX_EQ_F16 : VOPCX_F16 <"v_cmpx_eq_f16">; 745defm V_CMPX_LE_F16 : VOPCX_F16 <"v_cmpx_le_f16", "v_cmpx_ge_f16">; 746defm V_CMPX_GT_F16 : VOPCX_F16 <"v_cmpx_gt_f16">; 747defm V_CMPX_LG_F16 : VOPCX_F16 <"v_cmpx_lg_f16">; 748defm V_CMPX_GE_F16 : VOPCX_F16 <"v_cmpx_ge_f16">; 749defm V_CMPX_O_F16 : VOPCX_F16 <"v_cmpx_o_f16">; 750defm V_CMPX_U_F16 : VOPCX_F16 <"v_cmpx_u_f16">; 751defm V_CMPX_NGE_F16 : VOPCX_F16 <"v_cmpx_nge_f16", "v_cmpx_nle_f16">; 752defm V_CMPX_NLG_F16 : VOPCX_F16 <"v_cmpx_nlg_f16">; 753defm V_CMPX_NGT_F16 : VOPCX_F16 <"v_cmpx_ngt_f16", "v_cmpx_nlt_f16">; 754defm V_CMPX_NLE_F16 : VOPCX_F16 <"v_cmpx_nle_f16">; 755defm V_CMPX_NEQ_F16 : VOPCX_F16 <"v_cmpx_neq_f16">; 756defm V_CMPX_NLT_F16 : VOPCX_F16 <"v_cmpx_nlt_f16">; 757defm V_CMPX_TRU_F16 : VOPCX_F16 <"v_cmpx_tru_f16">; 758 759defm V_CMP_F_I16 : VOPC_I16 <"v_cmp_f_i16">; 760defm V_CMP_LT_I16 : VOPC_I16 <"v_cmp_lt_i16", COND_SLT, "v_cmp_gt_i16">; 761defm V_CMP_EQ_I16 : VOPC_I16 <"v_cmp_eq_i16">; 762defm V_CMP_LE_I16 : VOPC_I16 <"v_cmp_le_i16", COND_SLE, "v_cmp_ge_i16">; 763defm V_CMP_GT_I16 : VOPC_I16 <"v_cmp_gt_i16", COND_SGT>; 764defm V_CMP_NE_I16 : VOPC_I16 <"v_cmp_ne_i16">; 765defm V_CMP_GE_I16 : VOPC_I16 <"v_cmp_ge_i16", COND_SGE>; 766defm V_CMP_T_I16 : VOPC_I16 <"v_cmp_t_i16">; 767 768defm V_CMP_F_U16 : VOPC_I16 <"v_cmp_f_u16">; 769defm V_CMP_LT_U16 : VOPC_I16 <"v_cmp_lt_u16", COND_ULT, "v_cmp_gt_u16">; 770defm V_CMP_EQ_U16 : VOPC_I16 <"v_cmp_eq_u16", COND_EQ>; 771defm V_CMP_LE_U16 : VOPC_I16 <"v_cmp_le_u16", COND_ULE, "v_cmp_ge_u16">; 772defm V_CMP_GT_U16 : VOPC_I16 <"v_cmp_gt_u16", COND_UGT>; 773defm V_CMP_NE_U16 : VOPC_I16 <"v_cmp_ne_u16", COND_NE>; 774defm V_CMP_GE_U16 : VOPC_I16 <"v_cmp_ge_u16", COND_UGE>; 775defm V_CMP_T_U16 : VOPC_I16 <"v_cmp_t_u16">; 776 777defm V_CMPX_F_I16 : VOPCX_I16 <"v_cmpx_f_i16">; 778defm V_CMPX_LT_I16 : VOPCX_I16 <"v_cmpx_lt_i16", "v_cmpx_gt_i16">; 779defm V_CMPX_EQ_I16 : VOPCX_I16 <"v_cmpx_eq_i16">; 780defm V_CMPX_LE_I16 : VOPCX_I16 <"v_cmpx_le_i16", "v_cmpx_ge_i16">; 781defm V_CMPX_GT_I16 : VOPCX_I16 <"v_cmpx_gt_i16">; 782defm V_CMPX_NE_I16 : VOPCX_I16 <"v_cmpx_ne_i16">; 783defm V_CMPX_GE_I16 : VOPCX_I16 <"v_cmpx_ge_i16">; 784defm V_CMPX_T_I16 : VOPCX_I16 <"v_cmpx_t_i16">; 785 786defm V_CMPX_F_U16 : VOPCX_I16 <"v_cmpx_f_u16">; 787defm V_CMPX_LT_U16 : VOPCX_I16 <"v_cmpx_lt_u16", "v_cmpx_gt_u16">; 788defm V_CMPX_EQ_U16 : VOPCX_I16 <"v_cmpx_eq_u16">; 789defm V_CMPX_LE_U16 : VOPCX_I16 <"v_cmpx_le_u16", "v_cmpx_ge_u16">; 790defm V_CMPX_GT_U16 : VOPCX_I16 <"v_cmpx_gt_u16">; 791defm V_CMPX_NE_U16 : VOPCX_I16 <"v_cmpx_ne_u16">; 792defm V_CMPX_GE_U16 : VOPCX_I16 <"v_cmpx_ge_u16">; 793defm V_CMPX_T_U16 : VOPCX_I16 <"v_cmpx_t_u16">; 794 795} // End SubtargetPredicate = Has16BitInsts 796 797defm V_CMP_F_I32 : VOPC_I32 <"v_cmp_f_i32">; 798defm V_CMP_LT_I32 : VOPC_I32 <"v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">; 799defm V_CMP_EQ_I32 : VOPC_I32 <"v_cmp_eq_i32">; 800defm V_CMP_LE_I32 : VOPC_I32 <"v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">; 801defm V_CMP_GT_I32 : VOPC_I32 <"v_cmp_gt_i32", COND_SGT>; 802defm V_CMP_NE_I32 : VOPC_I32 <"v_cmp_ne_i32">; 803defm V_CMP_GE_I32 : VOPC_I32 <"v_cmp_ge_i32", COND_SGE>; 804defm V_CMP_T_I32 : VOPC_I32 <"v_cmp_t_i32">; 805 806defm V_CMPX_F_I32 : VOPCX_I32 <"v_cmpx_f_i32">; 807defm V_CMPX_LT_I32 : VOPCX_I32 <"v_cmpx_lt_i32", "v_cmpx_gt_i32">; 808defm V_CMPX_EQ_I32 : VOPCX_I32 <"v_cmpx_eq_i32">; 809defm V_CMPX_LE_I32 : VOPCX_I32 <"v_cmpx_le_i32", "v_cmpx_ge_i32">; 810defm V_CMPX_GT_I32 : VOPCX_I32 <"v_cmpx_gt_i32">; 811defm V_CMPX_NE_I32 : VOPCX_I32 <"v_cmpx_ne_i32">; 812defm V_CMPX_GE_I32 : VOPCX_I32 <"v_cmpx_ge_i32">; 813defm V_CMPX_T_I32 : VOPCX_I32 <"v_cmpx_t_i32">; 814 815defm V_CMP_F_I64 : VOPC_I64 <"v_cmp_f_i64">; 816defm V_CMP_LT_I64 : VOPC_I64 <"v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">; 817defm V_CMP_EQ_I64 : VOPC_I64 <"v_cmp_eq_i64">; 818defm V_CMP_LE_I64 : VOPC_I64 <"v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">; 819defm V_CMP_GT_I64 : VOPC_I64 <"v_cmp_gt_i64", COND_SGT>; 820defm V_CMP_NE_I64 : VOPC_I64 <"v_cmp_ne_i64">; 821defm V_CMP_GE_I64 : VOPC_I64 <"v_cmp_ge_i64", COND_SGE>; 822defm V_CMP_T_I64 : VOPC_I64 <"v_cmp_t_i64">; 823 824defm V_CMPX_F_I64 : VOPCX_I64 <"v_cmpx_f_i64">; 825defm V_CMPX_LT_I64 : VOPCX_I64 <"v_cmpx_lt_i64", "v_cmpx_gt_i64">; 826defm V_CMPX_EQ_I64 : VOPCX_I64 <"v_cmpx_eq_i64">; 827defm V_CMPX_LE_I64 : VOPCX_I64 <"v_cmpx_le_i64", "v_cmpx_ge_i64">; 828defm V_CMPX_GT_I64 : VOPCX_I64 <"v_cmpx_gt_i64">; 829defm V_CMPX_NE_I64 : VOPCX_I64 <"v_cmpx_ne_i64">; 830defm V_CMPX_GE_I64 : VOPCX_I64 <"v_cmpx_ge_i64">; 831defm V_CMPX_T_I64 : VOPCX_I64 <"v_cmpx_t_i64">; 832 833defm V_CMP_F_U32 : VOPC_I32 <"v_cmp_f_u32">; 834defm V_CMP_LT_U32 : VOPC_I32 <"v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">; 835defm V_CMP_EQ_U32 : VOPC_I32 <"v_cmp_eq_u32", COND_EQ>; 836defm V_CMP_LE_U32 : VOPC_I32 <"v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">; 837defm V_CMP_GT_U32 : VOPC_I32 <"v_cmp_gt_u32", COND_UGT>; 838defm V_CMP_NE_U32 : VOPC_I32 <"v_cmp_ne_u32", COND_NE>; 839defm V_CMP_GE_U32 : VOPC_I32 <"v_cmp_ge_u32", COND_UGE>; 840defm V_CMP_T_U32 : VOPC_I32 <"v_cmp_t_u32">; 841 842defm V_CMPX_F_U32 : VOPCX_I32 <"v_cmpx_f_u32">; 843defm V_CMPX_LT_U32 : VOPCX_I32 <"v_cmpx_lt_u32", "v_cmpx_gt_u32">; 844defm V_CMPX_EQ_U32 : VOPCX_I32 <"v_cmpx_eq_u32">; 845defm V_CMPX_LE_U32 : VOPCX_I32 <"v_cmpx_le_u32", "v_cmpx_le_u32">; 846defm V_CMPX_GT_U32 : VOPCX_I32 <"v_cmpx_gt_u32">; 847defm V_CMPX_NE_U32 : VOPCX_I32 <"v_cmpx_ne_u32">; 848defm V_CMPX_GE_U32 : VOPCX_I32 <"v_cmpx_ge_u32">; 849defm V_CMPX_T_U32 : VOPCX_I32 <"v_cmpx_t_u32">; 850 851defm V_CMP_F_U64 : VOPC_I64 <"v_cmp_f_u64">; 852defm V_CMP_LT_U64 : VOPC_I64 <"v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">; 853defm V_CMP_EQ_U64 : VOPC_I64 <"v_cmp_eq_u64", COND_EQ>; 854defm V_CMP_LE_U64 : VOPC_I64 <"v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">; 855defm V_CMP_GT_U64 : VOPC_I64 <"v_cmp_gt_u64", COND_UGT>; 856defm V_CMP_NE_U64 : VOPC_I64 <"v_cmp_ne_u64", COND_NE>; 857defm V_CMP_GE_U64 : VOPC_I64 <"v_cmp_ge_u64", COND_UGE>; 858defm V_CMP_T_U64 : VOPC_I64 <"v_cmp_t_u64">; 859 860defm V_CMPX_F_U64 : VOPCX_I64 <"v_cmpx_f_u64">; 861defm V_CMPX_LT_U64 : VOPCX_I64 <"v_cmpx_lt_u64", "v_cmpx_gt_u64">; 862defm V_CMPX_EQ_U64 : VOPCX_I64 <"v_cmpx_eq_u64">; 863defm V_CMPX_LE_U64 : VOPCX_I64 <"v_cmpx_le_u64", "v_cmpx_ge_u64">; 864defm V_CMPX_GT_U64 : VOPCX_I64 <"v_cmpx_gt_u64">; 865defm V_CMPX_NE_U64 : VOPCX_I64 <"v_cmpx_ne_u64">; 866defm V_CMPX_GE_U64 : VOPCX_I64 <"v_cmpx_ge_u64">; 867defm V_CMPX_T_U64 : VOPCX_I64 <"v_cmpx_t_u64">; 868 869//===----------------------------------------------------------------------===// 870// Class instructions 871//===----------------------------------------------------------------------===// 872 873class VOPC_Class_Profile_Base<list<SchedReadWrite> sched, ValueType src0VT, ValueType src1VT = i32> : 874 VOPC_Profile<sched, src0VT, src1VT> { 875 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 876 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 877 Clamp:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel); 878 879 let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel"; 880 let HasClamp = 0; 881 let HasOMod = 0; 882} 883 884class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType src1VT = i32> : 885 VOPC_Class_Profile_Base<sched, src0VT, src1VT> { 886 let AsmDPP = "$src0_modifiers, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 887 let AsmDPP16 = AsmDPP#"$fi"; 888 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, Src1DPP:$src1, dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask, DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl); 889 let InsDPP16 = !con(InsDPP, (ins Dpp16FI:$fi)); 890 // DPP8 forbids modifiers and can inherit from VOPC_Profile 891 892 let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); 893 dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VCSrc_b32:$src1); 894 let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel), 895 (ins))); 896 let AsmVOP3Base = "$sdst, $src0_modifiers, $src1"; 897 let HasSrc1Mods = 0; 898} 899 900multiclass VOPC_Class_Profile_t16<list<SchedReadWrite> sched> { 901 def NAME : VOPC_Class_Profile<sched, f16>; 902 def _t16 : VOPC_Class_Profile_Base<sched, f16, f16> { 903 let IsTrue16 = 1; 904 let IsRealTrue16 = 1; 905 let HasOpSel = 1; 906 let HasModifiers = 1; // All instructions at least have OpSel 907 let DstRC = getVALUDstForVT<DstVT, 1 /*IsTrue16*/, 0 /*IsVOP3Encoding*/>.ret; 908 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 909 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 910 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 911 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 912 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 913 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret; 914 let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0/*IsFake16*/>.ret; 915 let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0/*IsFake16*/>.ret; 916 let Src0VOP3DPP = VGPRSrc_16; 917 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret; 918 let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret; 919 920 let DstRC64 = getVALUDstForVT<DstVT, 1/*IsTrue16*/, 1/*IsVOP3Encoding*/>.ret; 921 let Src0RC64 = getVOP3SrcForVT<Src0VT, 1/*IsTrue16*/>.ret; 922 let Src1RC64 = getVOP3SrcForVT<Src1VT, 1/*IsTrue16*/>.ret; 923 let Src2RC64 = getVOP3SrcForVT<Src2VT, 1/*IsTrue16*/>.ret; 924 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 925 let Src1Mod = getSrcMod<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 926 let Src2Mod = getSrcMod<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 927 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret; 928 let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 0/*IsFake16*/>.ret; 929 let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 0/*IsFake16*/>.ret; 930 } 931 def _fake16 : VOPC_Class_Profile_Base<sched, f16, f16> { 932 let IsTrue16 = 1; 933 let DstRC = getVALUDstForVT_fake16<DstVT>.ret; 934 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 935 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 936 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 937 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 938 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 939 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret; 940 let Src1ModDPP = getSrcModDPP_t16<Src1VT, 1/*IsFake16*/>.ret; 941 let Src2ModDPP = getSrcModDPP_t16<Src2VT, 1/*IsFake16*/>.ret; 942 let Src0VOP3DPP = VGPRSrc_32; 943 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret; 944 let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret; 945 946 let DstRC64 = getVALUDstForVT<DstVT>.ret; 947 let Src0RC64 = getVOP3SrcForVT<Src0VT, 0/*IsTrue16*/>.ret; 948 let Src1RC64 = getVOP3SrcForVT<Src1VT, 0/*IsTrue16*/>.ret; 949 let Src2RC64 = getVOP3SrcForVT<Src2VT, 0/*IsTrue16*/>.ret; 950 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 951 let Src1Mod = getSrcMod<Src1VT, 0/*IsTrue16*/, 1/*IsFake16*/>.ret; 952 let Src2Mod = getSrcMod<Src2VT, 0/*IsTrue16*/, 1/*IsFake16*/>.ret; 953 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 1/*IsFake16*/>.ret; 954 let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 1/*IsFake16*/>.ret; 955 let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 1/*IsFake16*/>.ret; 956 } 957} 958 959class VOPC_Class_NoSdst_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType src1VT = i32> : 960 VOPC_Class_Profile_Base<sched, src0VT, src1VT> { 961 let Outs64 = (outs ); 962 let OutsSDWA = (outs ); 963 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 964 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 965 src0_sel:$src0_sel, src1_sel:$src1_sel); 966 let HasDst = 0; 967 let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel"; 968 let EmitDst = 0; 969} 970 971multiclass VOPC_Class_NoSdst_Profile_t16<list<SchedReadWrite> sched> { 972 def NAME : VOPC_Class_NoSdst_Profile<sched, f16>; 973 def _t16 : VOPC_Class_NoSdst_Profile<sched, f16, f16> { 974 let IsTrue16 = 1; 975 let IsRealTrue16 = 1; 976 let HasOpSel = 1; 977 let HasModifiers = 1; // All instructions at least have OpSel 978 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 979 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 980 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 981 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 982 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 983 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret; 984 let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0/*IsFake16*/>.ret; 985 let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0/*IsFake16*/>.ret; 986 let Src0VOP3DPP = VGPRSrc_16; 987 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret; 988 let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret; 989 990 let Src0RC64 = getVOP3SrcForVT<Src0VT, 1/*IsTrue16*/>.ret; 991 let Src1RC64 = getVOP3SrcForVT<Src1VT, 1/*IsTrue16*/>.ret; 992 let Src2RC64 = getVOP3SrcForVT<Src2VT, 1/*IsTrue16*/>.ret; 993 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 994 let Src1Mod = getSrcMod<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 995 let Src2Mod = getSrcMod<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret; 996 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret; 997 let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 0/*IsFake16*/>.ret; 998 let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 0/*IsFake16*/>.ret; 999 } 1000 def _fake16 : VOPC_Class_NoSdst_Profile<sched, f16, f16> { 1001 let IsTrue16 = 1; 1002 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 1003 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 1004 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 1005 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 1006 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 1007 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret; 1008 let Src1ModDPP = getSrcModDPP_t16<Src1VT, 1/*IsFake16*/>.ret; 1009 let Src2ModDPP = getSrcModDPP_t16<Src2VT, 1/*IsFake16*/>.ret; 1010 let Src0VOP3DPP = VGPRSrc_32; 1011 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret; 1012 let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret; 1013 1014 let Src0RC64 = getVOP3SrcForVT<Src0VT, 0/*IsTrue16*/>.ret; 1015 let Src1RC64 = getVOP3SrcForVT<Src1VT, 0/*IsTrue16*/>.ret; 1016 let Src2RC64 = getVOP3SrcForVT<Src2VT, 0/*IsTrue16*/>.ret; 1017 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 1018 let Src1Mod = getSrcMod<Src1VT, 0/*IsTrue16*/, 1/*IsFake16*/>.ret; 1019 let Src2Mod = getSrcMod<Src2VT, 0/*IsTrue16*/, 1/*IsFake16*/>.ret; 1020 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 1/*IsFake16*/>.ret; 1021 let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 1/*IsFake16*/>.ret; 1022 let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 1/*IsFake16*/>.ret; 1023 } 1024} 1025 1026multiclass VOPCClassPat64<string inst_name> { 1027 defvar inst = !cast<VOP_Pseudo>(inst_name#"_e64"); 1028 defvar P = inst.Pfl; 1029 def : GCNPat < 1030 (i1:$sdst 1031 (AMDGPUfp_class 1032 (P.Src0VT (VOP3ModsNonCanonicalizing P.Src0VT:$src0, i32:$src0_modifiers)), 1033 P.Src1VT:$src1)), 1034 (inst i32:$src0_modifiers, P.Src0VT:$src0, P.Src1VT:$src1) 1035 >; 1036} 1037 1038multiclass VOPCClassPat64_fake16<string inst_name> { 1039 defvar inst = !cast<VOP_Pseudo>(inst_name#"_fake16_e64"); 1040 defvar P = inst.Pfl; 1041 def : GCNPat < 1042 (i1:$sdst 1043 (AMDGPUfp_class 1044 (P.Src0VT (VOP3ModsNonCanonicalizing P.Src0VT:$src0, i32:$src0_modifiers)), 1045 i32:$src1)), 1046 (inst i32:$src0_modifiers, P.Src0VT:$src0, 1047 0 /*src1_modifiers*/, VGPR_32:$src1) 1048 >; 1049} 1050 1051// cmp_class ignores the FP mode and faithfully reports the unmodified 1052// source value. 1053let ReadsModeReg = 0, mayRaiseFPException = 0 in { 1054multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec, 1055 bit DefVcc = 1> { 1056 def _e32 : VOPC_Pseudo <opName, p>, 1057 VCMPXNoSDstTable<1, opName#"_e32"> { 1058 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]), 1059 !if(DefVcc, [VCC], [])); 1060 let SchedRW = p.Schedule; 1061 let isConvergent = DefExec; 1062 } 1063 1064 def _e64 : VOP3_Pseudo<opName, p, [], 0/*IsVOP3P*/, p.HasOpSel>, 1065 VCMPXNoSDstTable<1, opName#"_e64"> { 1066 let Defs = !if(DefExec, [EXEC], []); 1067 let SchedRW = p.Schedule; 1068 } 1069 1070 if p.HasExtSDWA then 1071 def _sdwa : VOPC_SDWA_Pseudo <opName, p> { 1072 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]), 1073 !if(DefVcc, [VCC], [])); 1074 let SchedRW = p.Schedule; 1075 let isConvergent = DefExec; 1076 } 1077 1078 let SubtargetPredicate = isGFX11Plus in { 1079 if p.HasExtDPP then 1080 def _e32_dpp : VOP_DPP_Pseudo<opName, p> { 1081 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]), 1082 !if(DefVcc, [VCC], [])); 1083 let SchedRW = p.Schedule; 1084 let isConvergent = DefExec; 1085 let VOPC = 1; 1086 let Constraints = ""; 1087 } 1088 if p.HasExtVOP3DPP then 1089 def _e64_dpp : VOP3_DPP_Pseudo<opName, p> { 1090 let Defs = !if(DefExec, [EXEC], []); 1091 let SchedRW = p.Schedule; 1092 let Constraints = ""; 1093 } 1094 } // end SubtargetPredicate = isGFX11Plus 1095} 1096 1097let SubtargetPredicate = HasSdstCMPX in { 1098multiclass VOPCX_Class_Pseudos <string opName, 1099 VOPC_Profile P, 1100 VOPC_Profile P_NoSDst> : 1101 VOPC_Class_Pseudos <opName, P, 1, 1> { 1102 1103 def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>, 1104 VCMPXNoSDstTable<0, opName#"_e32"> { 1105 let Defs = [EXEC]; 1106 let SchedRW = P_NoSDst.Schedule; 1107 let isConvergent = 1; 1108 let SubtargetPredicate = HasNoSdstCMPX; 1109 } 1110 1111 def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst, [], 0/*IsVOP3P*/, P_NoSDst.HasOpSel>, 1112 VCMPXNoSDstTable<0, opName#"_e64"> { 1113 let Defs = [EXEC]; 1114 let SchedRW = P_NoSDst.Schedule; 1115 let SubtargetPredicate = HasNoSdstCMPX; 1116 } 1117 1118 if P_NoSDst.HasExtSDWA then 1119 def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> { 1120 let Defs = [EXEC]; 1121 let SchedRW = P_NoSDst.Schedule; 1122 let isConvergent = 1; 1123 let SubtargetPredicate = HasNoSdstCMPX; 1124 } 1125 1126 let SubtargetPredicate = isGFX11Plus in { 1127 if P.HasExtDPP then 1128 def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 1129 let Defs = [EXEC]; 1130 let SchedRW = P_NoSDst.Schedule; 1131 let isConvergent = 1; 1132 let VOPC = 1; 1133 let Constraints = ""; 1134 } 1135 if P.HasExtVOP3DPP then 1136 def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 1137 let Defs = [EXEC]; 1138 let SchedRW = P_NoSDst.Schedule; 1139 let Constraints = ""; 1140 } 1141 } // end SubtargetPredicate = isGFX11Plus 1142} 1143} // End SubtargetPredicate = HasSdstCMPX 1144} // End ReadsModeReg = 0, mayRaiseFPException = 0 1145 1146defm VOPC_I1_F16_I16 : VOPC_Class_Profile_t16<[Write32Bit]>; 1147def VOPC_I1_F32_I32 : VOPC_Class_Profile<[Write32Bit], f32>; 1148def VOPC_I1_F64_I32 : VOPC_Class_Profile<[WriteDoubleAdd], f64>; 1149 1150defm VOPC_F16_I16 : VOPC_Class_NoSdst_Profile_t16<[Write32Bit]>; 1151def VOPC_F32_I32 : VOPC_Class_NoSdst_Profile<[Write32Bit], f32>; 1152def VOPC_F64_I32 : VOPC_Class_NoSdst_Profile<[Write64Bit], f64>; 1153 1154multiclass VOPC_CLASS_F16 <string opName> { 1155 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 1156 defm NAME : VOPC_Class_Pseudos <opName, VOPC_I1_F16_I16, 0>; 1157 defm : VOPCClassPat64<NAME>; 1158 } 1159 let True16Predicate = UseRealTrue16Insts in { 1160 defm _t16 : VOPC_Class_Pseudos <opName#"_t16", VOPC_I1_F16_I16_t16, 0>; 1161 } 1162 let True16Predicate = UseFakeTrue16Insts in { 1163 defm _fake16 : VOPC_Class_Pseudos <opName#"_fake16", VOPC_I1_F16_I16_fake16, 0>; 1164 defm : VOPCClassPat64_fake16<NAME>; 1165 } 1166} 1167 1168multiclass VOPCX_CLASS_F16 <string opName> { 1169 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 1170 defm NAME : VOPCX_Class_Pseudos <opName, VOPC_I1_F16_I16, VOPC_F16_I16>; 1171 } 1172 let True16Predicate = UseRealTrue16Insts in { 1173 defm _t16 : VOPCX_Class_Pseudos <opName#"_t16", VOPC_I1_F16_I16_t16, VOPC_F16_I16_t16>; 1174 } 1175 let True16Predicate = UseFakeTrue16Insts in { 1176 defm _fake16 : VOPCX_Class_Pseudos <opName#"_fake16", VOPC_I1_F16_I16_fake16, VOPC_F16_I16_fake16>; 1177 } 1178} 1179 1180multiclass VOPC_CLASS_F32 <string opName> { 1181 defm NAME : VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 0>; 1182 defm : VOPCClassPat64<NAME>; 1183} 1184 1185multiclass VOPCX_CLASS_F32 <string opName> : 1186 VOPCX_Class_Pseudos <opName, VOPC_I1_F32_I32, VOPC_F32_I32>; 1187 1188multiclass VOPC_CLASS_F64 <string opName> { 1189 defm NAME : VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>; 1190 defm : VOPCClassPat64<NAME>; 1191} 1192 1193multiclass VOPCX_CLASS_F64 <string opName> : 1194 VOPCX_Class_Pseudos <opName, VOPC_I1_F64_I32, VOPC_F64_I32>; 1195 1196defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">; 1197defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">; 1198defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">; 1199defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">; 1200 1201defm V_CMP_CLASS_F16 : VOPC_CLASS_F16 <"v_cmp_class_f16">; 1202defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">; 1203 1204//===----------------------------------------------------------------------===// 1205// V_ICMPIntrinsic Pattern. 1206//===----------------------------------------------------------------------===// 1207 1208// We need to use COPY_TO_REGCLASS to w/a the problem when ReplaceAllUsesWith() 1209// complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place. 1210multiclass ICMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> { 1211 let WaveSizePredicate = isWave64 in 1212 def : GCNPat < 1213 (i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)), 1214 (i64 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_64)) 1215 >; 1216 1217 let WaveSizePredicate = isWave32 in { 1218 def : GCNPat < 1219 (i32 (AMDGPUsetcc vt:$src0, vt:$src1, cond)), 1220 (i32 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_32)) 1221 >; 1222 1223 // Support codegen of i64 setcc in wave32 mode. 1224 def : GCNPat < 1225 (i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)), 1226 (i64 (REG_SEQUENCE SReg_64, (inst $src0, $src1), sub0, (S_MOV_B32 (i32 0)), sub1)) 1227 >; 1228 } 1229} 1230 1231defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U32_e64, i32>; 1232defm : ICMP_Pattern <COND_NE, V_CMP_NE_U32_e64, i32>; 1233defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>; 1234defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>; 1235defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>; 1236defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>; 1237defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>; 1238defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>; 1239defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>; 1240defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>; 1241 1242defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U64_e64, i64>; 1243defm : ICMP_Pattern <COND_NE, V_CMP_NE_U64_e64, i64>; 1244defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>; 1245defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>; 1246defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>; 1247defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>; 1248defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>; 1249defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>; 1250defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>; 1251defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>; 1252 1253let True16Predicate = UseFakeTrue16Insts in { 1254defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_fake16_e64, i16>; 1255defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_fake16_e64, i16>; 1256defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_fake16_e64, i16>; 1257defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U16_fake16_e64, i16>; 1258defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U16_fake16_e64, i16>; 1259defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U16_fake16_e64, i16>; 1260defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I16_fake16_e64, i16>; 1261defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_fake16_e64, i16>; 1262defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_fake16_e64, i16>; 1263defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_fake16_e64, i16>; 1264} // End True16Predicate = UseFakeTrue16Insts 1265 1266let True16Predicate = NotHasTrue16BitInsts in { 1267defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_e64, i16>; 1268defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_e64, i16>; 1269defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_e64, i16>; 1270defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U16_e64, i16>; 1271defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U16_e64, i16>; 1272defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U16_e64, i16>; 1273defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I16_e64, i16>; 1274defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_e64, i16>; 1275defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_e64, i16>; 1276defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_e64, i16>; 1277} // End True16Predicate = NotHasTrue16BitInsts 1278 1279multiclass FCMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> { 1280 let WaveSizePredicate = isWave64 in 1281 def : GCNPat < 1282 (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 1283 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)), 1284 (i64 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1, 1285 DSTCLAMP.NONE), SReg_64)) 1286 >; 1287 1288 let WaveSizePredicate = isWave32 in { 1289 def : GCNPat < 1290 (i32 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 1291 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)), 1292 (i32 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1, 1293 DSTCLAMP.NONE), SReg_32)) 1294 >; 1295 1296 def : GCNPat < 1297 (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 1298 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)), 1299 (i64 (REG_SEQUENCE SReg_64, (inst $src0_modifiers, $src0, $src1_modifiers, $src1, 1300 DSTCLAMP.NONE), sub0, 1301 (S_MOV_B32 (i32 0)), sub1)) 1302 >; 1303 } 1304} 1305 1306defm : FCMP_Pattern <COND_O, V_CMP_O_F32_e64, f32>; 1307defm : FCMP_Pattern <COND_UO, V_CMP_U_F32_e64, f32>; 1308defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>; 1309defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>; 1310defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>; 1311defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>; 1312defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>; 1313defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>; 1314 1315defm : FCMP_Pattern <COND_O, V_CMP_O_F64_e64, f64>; 1316defm : FCMP_Pattern <COND_UO, V_CMP_U_F64_e64, f64>; 1317defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>; 1318defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>; 1319defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>; 1320defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>; 1321defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>; 1322defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>; 1323 1324defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>; 1325defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>; 1326defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>; 1327defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>; 1328defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>; 1329defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>; 1330 1331defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>; 1332defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>; 1333defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>; 1334defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>; 1335defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>; 1336defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>; 1337 1338let True16Predicate = UseFakeTrue16Insts in { 1339defm : FCMP_Pattern <COND_O, V_CMP_O_F16_fake16_e64, f16>; 1340defm : FCMP_Pattern <COND_UO, V_CMP_U_F16_fake16_e64, f16>; 1341defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_fake16_e64, f16>; 1342defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_fake16_e64, f16>; 1343defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_fake16_e64, f16>; 1344defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_fake16_e64, f16>; 1345defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_fake16_e64, f16>; 1346defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_fake16_e64, f16>; 1347 1348defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_fake16_e64, f16>; 1349defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_fake16_e64, f16>; 1350defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_fake16_e64, f16>; 1351defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_fake16_e64, f16>; 1352defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_fake16_e64, f16>; 1353defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_fake16_e64, f16>; 1354} // End True16Predicate = UseFakeTrue16Insts 1355 1356let True16Predicate = NotHasTrue16BitInsts in { 1357defm : FCMP_Pattern <COND_O, V_CMP_O_F16_e64, f16>; 1358defm : FCMP_Pattern <COND_UO, V_CMP_U_F16_e64, f16>; 1359defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_e64, f16>; 1360defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_e64, f16>; 1361defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_e64, f16>; 1362defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_e64, f16>; 1363defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_e64, f16>; 1364defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_e64, f16>; 1365 1366defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_e64, f16>; 1367defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_e64, f16>; 1368defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_e64, f16>; 1369defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_e64, f16>; 1370defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_e64, f16>; 1371defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_e64, f16>; 1372} // End True16Predicate = NotHasTrue16BitInsts 1373 1374//===----------------------------------------------------------------------===// 1375// DPP Encodings 1376//===----------------------------------------------------------------------===// 1377 1378// VOPC32 1379 1380class VOPC_DPPe_Common<bits<8> op> : Enc64 { 1381 bits<8> src1; 1382 let Inst{16-9} = src1; 1383 let Inst{24-17} = op; 1384 let Inst{31-25} = 0x3e; 1385} 1386 1387class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P> 1388 : VOP_DPP_Base<OpName, P, P.InsDPP16, " " #P.AsmDPP16>, 1389 VOPC_DPPe_Common<op> { 1390 Instruction Opcode = !cast<Instruction>(NAME); 1391 1392 bits<2> src0_modifiers; 1393 bits<8> src0; 1394 bits<2> src1_modifiers; 1395 bits<9> dpp_ctrl; 1396 bits<1> bound_ctrl; 1397 bits<4> bank_mask; 1398 bits<4> row_mask; 1399 bit fi; 1400 1401 let Inst{8-0} = 0xfa; 1402 1403 let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0); 1404 let Inst{48-40} = dpp_ctrl; 1405 let Inst{50} = fi; 1406 let Inst{51} = bound_ctrl; 1407 let Inst{52} = !if (P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 1408 let Inst{53} = !if (P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 1409 let Inst{54} = !if (P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 1410 let Inst{55} = !if (P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 1411 let Inst{59-56} = bank_mask; 1412 let Inst{63-60} = row_mask; 1413 1414 let AsmMatchConverter = "cvtDPP"; 1415 let VOPC = 1; 1416} 1417 1418class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P> 1419 : VOP_DPP8_Base<OpName, P, P.InsDPP8, " " #P.AsmDPP8>, 1420 VOPC_DPPe_Common<op> { 1421 Instruction Opcode = !cast<Instruction>(NAME); 1422 1423 bits<8> src0; 1424 bits<24> dpp8; 1425 bits<9> fi; 1426 1427 let Inst{8-0} = fi; 1428 1429 let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0); 1430 let Inst{63-40} = dpp8{23-0}; 1431 1432 let AsmMatchConverter = "cvtDPP8"; 1433 let VOPC = 1; 1434} 1435 1436class VOPC_DPP16<bits<8> op, VOP_DPP_Pseudo ps, string opName = ps.OpName> 1437 : VOPC_DPP_Base<op, opName, ps.Pfl> { 1438 let AssemblerPredicate = HasDPP16; 1439 let SubtargetPredicate = HasDPP16; 1440 let True16Predicate = ps.True16Predicate; 1441 let hasSideEffects = ps.hasSideEffects; 1442 let Defs = ps.Defs; 1443 let SchedRW = ps.SchedRW; 1444 let Uses = ps.Uses; 1445 let OtherPredicates = ps.OtherPredicates; 1446 let Constraints = ps.Constraints; 1447} 1448 1449class VOPC_DPP16_SIMC<bits<8> op, VOP_DPP_Pseudo ps, int subtarget, 1450 string opName = ps.OpName> 1451 : VOPC_DPP16<op, ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>; 1452 1453class VOPC_DPP8<bits<8> op, VOPC_Pseudo ps, string opName = ps.OpName> 1454 : VOPC_DPP8_Base<op, opName, ps.Pfl> { 1455 // Note ps is the non-dpp pseudo 1456 let hasSideEffects = ps.hasSideEffects; 1457 let Defs = ps.Defs; 1458 let SchedRW = ps.SchedRW; 1459 let Uses = ps.Uses; 1460 let OtherPredicates = ps.OtherPredicates; 1461 let True16Predicate = ps.True16Predicate; 1462 let Constraints = ""; 1463} 1464 1465// VOPC64 1466 1467class VOPC64_DPP<VOP_DPP_Pseudo ps, string opName = ps.OpName> 1468 : VOP3_DPP_Base<opName, ps.Pfl, 1> { 1469 Instruction Opcode = !cast<Instruction>(NAME); 1470 let AssemblerPredicate = HasDPP16; 1471 let SubtargetPredicate = HasDPP16; 1472 let True16Predicate = ps.True16Predicate; 1473 let hasSideEffects = ps.hasSideEffects; 1474 let Defs = ps.Defs; 1475 let SchedRW = ps.SchedRW; 1476 let Uses = ps.Uses; 1477 let OtherPredicates = ps.OtherPredicates; 1478 let Constraints = ps.Constraints; 1479} 1480 1481class VOPC64_DPP16_Dst<bits<10> op, VOP_DPP_Pseudo ps, 1482 string opName = ps.OpName> 1483 : VOPC64_DPP<ps, opName>, VOP3_DPP_Enc<op, ps.Pfl, 1> { 1484 bits<8> sdst; 1485 let Inst{7-0} = sdst; 1486} 1487 1488class VOPC64_DPP16_NoDst<bits<10> op, VOP_DPP_Pseudo ps, 1489 string opName = ps.OpName> 1490 : VOPC64_DPP<ps, opName>, VOP3_DPP_Enc<op, ps.Pfl, 1> { 1491 let Inst{7-0} = ?; 1492} 1493 1494class VOPC64_DPP16_Dst_t16<bits<10> op, VOP_DPP_Pseudo ps, 1495 string opName = ps.OpName> 1496 : VOPC64_DPP<ps, opName>, VOP3_DPP_Enc_t16<op, ps.Pfl, 1> { 1497 bits<8> sdst; 1498 let Inst{7-0} = sdst; 1499 let Inst{14} = 0; 1500} 1501 1502class VOPC64_DPP16_NoDst_t16<bits<10> op, VOP_DPP_Pseudo ps, 1503 string opName = ps.OpName> 1504 : VOPC64_DPP<ps, opName>, VOP3_DPP_Enc_t16<op, ps.Pfl, 1> { 1505 let Inst{7-0} = ?; 1506 let Inst{14} = 0; 1507} 1508 1509class VOPC64_DPP8<VOP_Pseudo ps, string opName = ps.OpName> 1510 : VOP3_DPP8_Base<opName, ps.Pfl> { 1511 Instruction Opcode = !cast<Instruction>(NAME); 1512 // Note ps is the non-dpp pseudo 1513 let hasSideEffects = ps.hasSideEffects; 1514 let Defs = ps.Defs; 1515 let SchedRW = ps.SchedRW; 1516 let Uses = ps.Uses; 1517 let OtherPredicates = ps.OtherPredicates; 1518 let True16Predicate = ps.True16Predicate; 1519} 1520 1521class VOPC64_DPP8_Dst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1522 : VOPC64_DPP8<ps, opName>, VOP3_DPP8_Enc<op, ps.Pfl> { 1523 bits<8> sdst; 1524 let Inst{7-0} = sdst; 1525 let Constraints = ""; 1526} 1527 1528class VOPC64_DPP8_NoDst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1529 : VOPC64_DPP8<ps, opName>, VOP3_DPP8_Enc<op, ps.Pfl> { 1530 let Inst{7-0} = ?; 1531 let Constraints = ""; 1532} 1533 1534class VOPC64_DPP8_Dst_t16<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1535 : VOPC64_DPP8<ps, opName>, VOP3_DPP8_Enc_t16<op, ps.Pfl> { 1536 bits<8> sdst; 1537 let Inst{7-0} = sdst; 1538 let Inst{14} = 0; 1539 let Constraints = ""; 1540} 1541 1542class VOPC64_DPP8_NoDst_t16<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1543 : VOPC64_DPP8<ps, opName>, VOP3_DPP8_Enc_t16<op, ps.Pfl> { 1544 let Inst{7-0} = ?; 1545 let Inst{14} = 0; 1546 let Constraints = ""; 1547} 1548 1549//===----------------------------------------------------------------------===// 1550// Target-specific instruction encodings. 1551//===----------------------------------------------------------------------===// 1552 1553//===----------------------------------------------------------------------===// 1554// GFX11, GFX12 1555//===----------------------------------------------------------------------===// 1556 1557multiclass VOPC_Real_Base<GFXGen Gen, bits<9> op> { 1558 let AssemblerPredicate = Gen.AssemblerPredicate, DecoderNamespace = Gen.DecoderNamespace in { 1559 defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_e32"); 1560 defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_e64"); 1561 def _e32#Gen.Suffix : VOPC_Real<ps32, Gen.Subtarget>, 1562 VOPCe<op{7-0}>; 1563 def _e64#Gen.Suffix : VOP3_Real_Gen<ps64, Gen>, 1564 VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> { 1565 // Encoding used for VOPC instructions encoded as VOP3 differs from 1566 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 1567 bits<8> sdst; 1568 let Inst{7-0} = sdst; 1569 } 1570 1571 defm : VOPCInstAliases<NAME, !substr(Gen.Suffix,1)>; 1572 1573 if ps32.Pfl.HasExtDPP then { 1574 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e32" #"_dpp"); 1575 defvar AsmDPP = ps32.Pfl.AsmDPP16; 1576 def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP, Gen.Subtarget>; 1577 def _e32_dpp_w32#Gen.Suffix : VOPC_DPP16<op{7-0}, psDPP> { 1578 let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP; 1579 let isAsmParserOnly = 1; 1580 let WaveSizePredicate = isWave32; 1581 } 1582 def _e32_dpp_w64#Gen.Suffix : VOPC_DPP16<op{7-0}, psDPP> { 1583 let AsmString = psDPP.OpName # " vcc, " # AsmDPP; 1584 let isAsmParserOnly = 1; 1585 let WaveSizePredicate = isWave64; 1586 } 1587 defvar AsmDPP8 = ps32.Pfl.AsmDPP8; 1588 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32>; 1589 def _e32_dpp8_w32#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> { 1590 let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8; 1591 let isAsmParserOnly = 1; 1592 let WaveSizePredicate = isWave32; 1593 } 1594 def _e32_dpp8_w64#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> { 1595 let AsmString = ps32.OpName # " vcc, " # AsmDPP8; 1596 let isAsmParserOnly = 1; 1597 let WaveSizePredicate = isWave64; 1598 } 1599 } 1600 if ps64.Pfl.HasExtVOP3DPP then { 1601 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e64" #"_dpp"); 1602 def _e64_dpp#Gen.Suffix : VOPC64_DPP16_Dst<{0, op}, psDPP>, 1603 SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget>; 1604 def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_Dst<{0, op}, ps64>; 1605 } 1606 } // AssemblerPredicate = Gen.AssemblerPredicate, DecoderNamespace = Gen.DecoderNamespace 1607} 1608 1609multiclass VOPC_Real_with_name<GFXGen Gen, bits<9> op, string OpName, 1610 string asm_name, string pseudo_mnemonic = ""> { 1611 defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_e32"); 1612 defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_e64"); 1613 let AssemblerPredicate = Gen.AssemblerPredicate in { 1614 def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), ps32.Mnemonic, 1615 pseudo_mnemonic), 1616 asm_name, ps32.AsmVariantName>; 1617 def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), ps64.Mnemonic, 1618 pseudo_mnemonic), 1619 asm_name, ps64.AsmVariantName>; 1620 1621 let DecoderNamespace = Gen.DecoderNamespace # !if(ps32.Pfl.IsRealTrue16, "", "_FAKE16") in { 1622 def _e32#Gen.Suffix : 1623 // 32 and 64 bit forms of the instruction have _e32 and _e64 1624 // respectively appended to their assembly mnemonic. 1625 // _e64 is printed as part of the VOPDstS64orS32 operand, whereas 1626 // the destination-less 32bit forms add it to the asmString here. 1627 VOPC_Real<ps32, Gen.Subtarget, asm_name#"_e32">, 1628 VOPCe<op{7-0}>; 1629 if ps64.Pfl.IsRealTrue16 then { 1630 def _e64#Gen.Suffix : 1631 VOP3_Real_Gen<ps64, Gen, asm_name>, 1632 VOP3e_t16_gfx11_gfx12<{0, op}, ps64.Pfl> { 1633 // Encoding used for VOPC instructions encoded as VOP3 differs from 1634 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 1635 bits<8> sdst; 1636 let Inst{7-0} = sdst; 1637 let Inst{14} = 0; 1638 } 1639 } else { 1640 def _e64#Gen.Suffix : 1641 VOP3_Real_Gen<ps64, Gen, asm_name>, 1642 VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> { 1643 // Encoding used for VOPC instructions encoded as VOP3 differs from 1644 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 1645 bits<8> sdst; 1646 let Inst{7-0} = sdst; 1647 } 1648 } 1649 1650 defm : VOPCInstAliases<OpName, !substr(Gen.Suffix, 1), NAME, asm_name>; 1651 1652 if ps32.Pfl.HasExtDPP then { 1653 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e32" #"_dpp"); 1654 defvar AsmDPP = ps32.Pfl.AsmDPP16; 1655 def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP, 1656 Gen.Subtarget, asm_name>; 1657 def _e32_dpp_w32#Gen.Suffix 1658 : VOPC_DPP16<op{7-0}, psDPP, asm_name> { 1659 let AsmString = asm_name # " vcc_lo, " # AsmDPP; 1660 let isAsmParserOnly = 1; 1661 let WaveSizePredicate = isWave32; 1662 } 1663 def _e32_dpp_w64#Gen.Suffix 1664 : VOPC_DPP16<op{7-0}, psDPP, asm_name> { 1665 let AsmString = asm_name # " vcc, " # AsmDPP; 1666 let isAsmParserOnly = 1; 1667 let WaveSizePredicate = isWave64; 1668 } 1669 defvar AsmDPP8 = ps32.Pfl.AsmDPP8; 1670 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32, asm_name>; 1671 def _e32_dpp8_w32#Gen.Suffix 1672 : VOPC_DPP8<op{7-0}, ps32, asm_name> { 1673 let AsmString = asm_name # " vcc_lo, " # AsmDPP8; 1674 let isAsmParserOnly = 1; 1675 let WaveSizePredicate = isWave32; 1676 } 1677 def _e32_dpp8_w64#Gen.Suffix 1678 : VOPC_DPP8<op{7-0}, ps32, asm_name> { 1679 let AsmString = asm_name # " vcc, " # AsmDPP8; 1680 let isAsmParserOnly = 1; 1681 let WaveSizePredicate = isWave64; 1682 } 1683 } 1684 1685 if ps64.Pfl.HasExtVOP3DPP then { 1686 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e64" #"_dpp"); 1687 if ps64.Pfl.IsRealTrue16 then { 1688 def _e64_dpp#Gen.Suffix : VOPC64_DPP16_Dst_t16<{0, op}, psDPP, asm_name>, 1689 SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget>; 1690 def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_Dst_t16<{0, op}, ps64, asm_name>; 1691 } else { 1692 def _e64_dpp#Gen.Suffix : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name>, 1693 SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget>; 1694 def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name>; 1695 } 1696 } // end if ps64.Pfl.HasExtVOP3DPP 1697 } // End DecoderNamespace 1698 } // End AssemblerPredicate 1699} 1700 1701multiclass VOPC_Real_t16<GFXGen Gen, bits<9> op, string asm_name, 1702 string OpName = NAME, string pseudo_mnemonic = ""> : 1703 VOPC_Real_with_name<Gen, op, OpName, asm_name, pseudo_mnemonic>; 1704 1705multiclass VOPCX_Real<GFXGen Gen, bits<9> op> { 1706 let AssemblerPredicate = Gen.AssemblerPredicate, DecoderNamespace = Gen.DecoderNamespace in { 1707 defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_nosdst_e32"); 1708 defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_nosdst_e64"); 1709 def _e32#Gen.Suffix : 1710 VOPC_Real<ps32, Gen.Subtarget>, 1711 VOPCe<op{7-0}> { 1712 let AsmString = !subst("_nosdst", "", ps32.PseudoInstr) 1713 # " " # ps32.AsmOperands; 1714 } 1715 def _e64#Gen.Suffix : 1716 VOP3_Real_Gen<ps64, Gen>, 1717 VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> { 1718 let Inst{7-0} = ?; // sdst 1719 let AsmString = !subst("_nosdst", "", ps64.Mnemonic) 1720 # "{_e64} " # ps64.AsmOperands; 1721 } 1722 1723 defm : VOPCXInstAliases<NAME, !substr(Gen.Suffix, 1)>; 1724 1725 if ps32.Pfl.HasExtDPP then { 1726 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e32" #"_dpp"); 1727 defvar AsmDPP = ps32.Pfl.AsmDPP16; 1728 def _e32_dpp#Gen.Suffix 1729 : VOPC_DPP16_SIMC<op{7-0}, psDPP, Gen.Subtarget> { 1730 let AsmString = !subst("_nosdst", "", psDPP.OpName) # " " # AsmDPP; 1731 } 1732 defvar AsmDPP8 = ps32.Pfl.AsmDPP8; 1733 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> { 1734 let AsmString = !subst("_nosdst", "", ps32.OpName) # " " # AsmDPP8; 1735 } 1736 } 1737 1738 if ps64.Pfl.HasExtVOP3DPP then { 1739 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e64" #"_dpp"); 1740 defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16; 1741 def _e64_dpp#Gen.Suffix 1742 : VOPC64_DPP16_NoDst<{0, op}, psDPP>, 1743 SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget> { 1744 let AsmString = !subst("_nosdst", "", psDPP.OpName) 1745 # "{_e64_dpp} " # AsmDPP; 1746 } 1747 defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8; 1748 def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_NoDst<{0, op}, ps64> { 1749 let AsmString = !subst("_nosdst", "", ps64.OpName) 1750 # "{_e64_dpp} " # AsmDPP8; 1751 } 1752 } 1753 } // End AssemblerPredicate = Gen.AssemblerPredicate, DecoderNamespace = Gen.DecoderNamespace 1754} 1755 1756multiclass VOPCX_Real_with_name<GFXGen Gen, bits<9> op, string OpName, 1757 string asm_name, string pseudo_mnemonic = ""> { 1758 defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_nosdst_e32"); 1759 defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_nosdst_e64"); 1760 let AssemblerPredicate = Gen.AssemblerPredicate in { 1761 def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps32.Mnemonic), 1762 pseudo_mnemonic), 1763 asm_name, ps32.AsmVariantName>; 1764 def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps64.Mnemonic), 1765 pseudo_mnemonic), 1766 asm_name, ps64.AsmVariantName>; 1767 1768 let DecoderNamespace = Gen.DecoderNamespace # !if(ps32.Pfl.IsRealTrue16, "", "_FAKE16") in { 1769 def _e32#Gen.Suffix 1770 : VOPC_Real<ps32, Gen.Subtarget, asm_name>, 1771 VOPCe<op{7-0}> { 1772 let AsmString = asm_name # "{_e32} " # ps32.AsmOperands; 1773 } 1774 1775 if ps64.Pfl.IsRealTrue16 then { 1776 def _e64#Gen.Suffix 1777 : VOP3_Real_Gen<ps64, Gen, asm_name>, 1778 VOP3e_t16_gfx11_gfx12<{0, op}, ps64.Pfl> { 1779 let Inst{7-0} = ?; // sdst 1780 let Inst{14} = 0; 1781 let AsmString = asm_name # "{_e64} " # ps64.AsmOperands; 1782 } 1783 } else { 1784 def _e64#Gen.Suffix 1785 : VOP3_Real_Gen<ps64, Gen, asm_name>, 1786 VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> { 1787 let Inst{7-0} = ?; // sdst 1788 let AsmString = asm_name # "{_e64} " # ps64.AsmOperands; 1789 } 1790 } 1791 1792 defm : VOPCXInstAliases<OpName, !substr(Gen.Suffix, 1), NAME, asm_name>; 1793 1794 if ps32.Pfl.HasExtDPP then { 1795 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e32"#"_dpp"); 1796 def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP, 1797 Gen.Subtarget, asm_name>; 1798 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32, asm_name>; 1799 } 1800 if ps64.Pfl.HasExtVOP3DPP then { 1801 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e64"#"_dpp"); 1802 defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16; 1803 defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8; 1804 if ps64.Pfl.IsRealTrue16 then { 1805 def _e64_dpp#Gen.Suffix 1806 : VOPC64_DPP16_NoDst_t16<{0, op}, psDPP, asm_name>, 1807 SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget> { 1808 let AsmString = asm_name # "{_e64_dpp} " # AsmDPP; 1809 } 1810 def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_NoDst_t16<{0, op}, ps64, asm_name> { 1811 let AsmString = asm_name # "{_e64_dpp} " # AsmDPP8; 1812 } 1813 } else { 1814 def _e64_dpp#Gen.Suffix 1815 : VOPC64_DPP16_NoDst<{0, op}, psDPP, asm_name>, 1816 SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget> { 1817 let AsmString = asm_name # "{_e64_dpp} " # AsmDPP; 1818 } 1819 def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_NoDst<{0, op}, ps64, asm_name> { 1820 let AsmString = asm_name # "{_e64_dpp} " # AsmDPP8; 1821 } 1822 } 1823 } // End if ps64.Pfl.HasExtVOP3DPP 1824 } // End DecoderNamespace 1825 } // End AssemblerPredicate 1826} 1827 1828multiclass VOPCX_Real_t16<GFXGen Gen, bits<9> op, string asm_name, 1829 string OpName = NAME, string pseudo_mnemonic = ""> : 1830 VOPCX_Real_with_name<Gen, op, OpName, asm_name, pseudo_mnemonic>; 1831 1832multiclass VOPC_Real_gfx11<bits<9> op> : VOPC_Real_Base<GFX11Gen, op>; 1833 1834multiclass VOPC_Real_with_name_gfx11<bits<9> op, string OpName, string asm_name, 1835 string pseudo_mnemonic = ""> 1836 : VOPC_Real_with_name<GFX11Gen, op, OpName, asm_name, pseudo_mnemonic>; 1837 1838multiclass VOPCX_Real_gfx11<bits<9> op> : VOPCX_Real<GFX11Gen, op>; 1839 1840multiclass VOPCX_Real_with_name_gfx11<bits<9> op, string OpName, 1841 string asm_name, string pseudo_mnemonic = ""> : 1842 VOPCX_Real_with_name<GFX11Gen, op, OpName, asm_name, pseudo_mnemonic>; 1843 1844multiclass VOPC_Real_gfx11_gfx12<bits<9> op> : 1845 VOPC_Real_Base<GFX11Gen, op>, VOPC_Real_Base<GFX12Gen, op>; 1846 1847multiclass VOPCX_Real_gfx11_gfx12<bits<9> op> : 1848 VOPCX_Real<GFX11Gen, op>, VOPCX_Real<GFX12Gen, op>; 1849 1850multiclass VOPC_Real_t16_gfx11<bits <9> op, string asm_name, 1851 string OpName = NAME, string pseudo_mnemonic = ""> : 1852 VOPC_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>; 1853 1854multiclass VOPC_Real_t16_and_fake16_gfx11<bits <9> op, string asm_name, 1855 string OpName = NAME, string pseudo_mnemonic = ""> { 1856 defm _t16: VOPC_Real_t16_gfx11<op, asm_name, OpName#"_t16", pseudo_mnemonic>; 1857 defm _fake16: VOPC_Real_t16_gfx11<op, asm_name, OpName#"_fake16", pseudo_mnemonic>; 1858} 1859 1860multiclass VOPC_Real_t16_gfx11_gfx12<bits <9> op, string asm_name, 1861 string OpName = NAME, string pseudo_mnemonic = ""> : 1862 VOPC_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>, 1863 VOPC_Real_t16<GFX12Gen, op, asm_name, OpName, pseudo_mnemonic>; 1864 1865multiclass VOPC_Real_t16_and_fake16_gfx11_gfx12<bits <9> op, string asm_name, 1866 string OpName = NAME, string pseudo_mnemonic = ""> { 1867 defm _t16: VOPC_Real_t16_gfx11_gfx12<op, asm_name, OpName#"_t16", pseudo_mnemonic>; 1868 defm _fake16: VOPC_Real_t16_gfx11_gfx12<op, asm_name, OpName#"_fake16", pseudo_mnemonic>; 1869} 1870 1871multiclass VOPCX_Real_t16_gfx11<bits<9> op, string asm_name, 1872 string OpName = NAME, string pseudo_mnemonic = ""> : 1873 VOPCX_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>; 1874 1875multiclass VOPCX_Real_t16_and_fake16_gfx11<bits<9> op, string asm_name, 1876 string OpName = NAME, string pseudo_mnemonic = ""> { 1877 defm _t16: VOPCX_Real_t16_gfx11<op, asm_name, OpName#"_t16", pseudo_mnemonic>; 1878 defm _fake16: VOPCX_Real_t16_gfx11<op, asm_name, OpName#"_fake16", pseudo_mnemonic>; 1879} 1880 1881multiclass VOPCX_Real_t16_gfx11_gfx12<bits<9> op, string asm_name, 1882 string OpName = NAME, string pseudo_mnemonic = ""> : 1883 VOPCX_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>, 1884 VOPCX_Real_t16<GFX12Gen, op, asm_name, OpName, pseudo_mnemonic>; 1885 1886multiclass VOPCX_Real_t16_and_fake16_gfx11_gfx12<bits<9> op, string asm_name, 1887 string OpName = NAME, string pseudo_mnemonic = ""> { 1888 defm _t16: VOPCX_Real_t16_gfx11_gfx12<op, asm_name, OpName#"_t16", pseudo_mnemonic>; 1889 defm _fake16: VOPCX_Real_t16_gfx11_gfx12<op, asm_name, OpName#"_fake16", pseudo_mnemonic>; 1890} 1891 1892defm V_CMP_F_F16 : VOPC_Real_t16_and_fake16_gfx11<0x000, "v_cmp_f_f16">; 1893defm V_CMP_LT_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x001, "v_cmp_lt_f16">; 1894defm V_CMP_EQ_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x002, "v_cmp_eq_f16">; 1895defm V_CMP_LE_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x003, "v_cmp_le_f16">; 1896defm V_CMP_GT_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x004, "v_cmp_gt_f16">; 1897defm V_CMP_LG_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x005, "v_cmp_lg_f16">; 1898defm V_CMP_GE_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x006, "v_cmp_ge_f16">; 1899defm V_CMP_O_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x007, "v_cmp_o_f16">; 1900defm V_CMP_U_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x008, "v_cmp_u_f16">; 1901defm V_CMP_NGE_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x009, "v_cmp_nge_f16">; 1902defm V_CMP_NLG_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x00a, "v_cmp_nlg_f16">; 1903defm V_CMP_NGT_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x00b, "v_cmp_ngt_f16">; 1904defm V_CMP_NLE_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x00c, "v_cmp_nle_f16">; 1905defm V_CMP_NEQ_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x00d, "v_cmp_neq_f16">; 1906defm V_CMP_NLT_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x00e, "v_cmp_nlt_f16">; 1907defm V_CMP_T_F16 : VOPC_Real_t16_and_fake16_gfx11<0x00f, "v_cmp_t_f16", "V_CMP_TRU_F16", "v_cmp_tru_f16">; 1908 1909defm V_CMP_F_F32 : VOPC_Real_gfx11<0x010>; 1910defm V_CMP_LT_F32 : VOPC_Real_gfx11_gfx12<0x011>; 1911defm V_CMP_EQ_F32 : VOPC_Real_gfx11_gfx12<0x012>; 1912defm V_CMP_LE_F32 : VOPC_Real_gfx11_gfx12<0x013>; 1913defm V_CMP_GT_F32 : VOPC_Real_gfx11_gfx12<0x014>; 1914defm V_CMP_LG_F32 : VOPC_Real_gfx11_gfx12<0x015>; 1915defm V_CMP_GE_F32 : VOPC_Real_gfx11_gfx12<0x016>; 1916defm V_CMP_O_F32 : VOPC_Real_gfx11_gfx12<0x017>; 1917defm V_CMP_U_F32 : VOPC_Real_gfx11_gfx12<0x018>; 1918defm V_CMP_NGE_F32 : VOPC_Real_gfx11_gfx12<0x019>; 1919defm V_CMP_NLG_F32 : VOPC_Real_gfx11_gfx12<0x01a>; 1920defm V_CMP_NGT_F32 : VOPC_Real_gfx11_gfx12<0x01b>; 1921defm V_CMP_NLE_F32 : VOPC_Real_gfx11_gfx12<0x01c>; 1922defm V_CMP_NEQ_F32 : VOPC_Real_gfx11_gfx12<0x01d>; 1923defm V_CMP_NLT_F32 : VOPC_Real_gfx11_gfx12<0x01e>; 1924defm V_CMP_T_F32 : VOPC_Real_with_name_gfx11<0x01f, "V_CMP_TRU_F32", "v_cmp_t_f32">; 1925defm V_CMP_T_F64 : VOPC_Real_with_name_gfx11<0x02f, "V_CMP_TRU_F64", "v_cmp_t_f64">; 1926 1927defm V_CMP_LT_I16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x031, "v_cmp_lt_i16">; 1928defm V_CMP_EQ_I16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x032, "v_cmp_eq_i16">; 1929defm V_CMP_LE_I16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x033, "v_cmp_le_i16">; 1930defm V_CMP_GT_I16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x034, "v_cmp_gt_i16">; 1931defm V_CMP_NE_I16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x035, "v_cmp_ne_i16">; 1932defm V_CMP_GE_I16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x036, "v_cmp_ge_i16">; 1933defm V_CMP_LT_U16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x039, "v_cmp_lt_u16">; 1934defm V_CMP_EQ_U16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x03a, "v_cmp_eq_u16">; 1935defm V_CMP_LE_U16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x03b, "v_cmp_le_u16">; 1936defm V_CMP_GT_U16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x03c, "v_cmp_gt_u16">; 1937defm V_CMP_NE_U16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x03d, "v_cmp_ne_u16">; 1938defm V_CMP_GE_U16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x03e, "v_cmp_ge_u16">; 1939 1940defm V_CMP_F_I32 : VOPC_Real_gfx11<0x040>; 1941defm V_CMP_LT_I32 : VOPC_Real_gfx11_gfx12<0x041>; 1942defm V_CMP_EQ_I32 : VOPC_Real_gfx11_gfx12<0x042>; 1943defm V_CMP_LE_I32 : VOPC_Real_gfx11_gfx12<0x043>; 1944defm V_CMP_GT_I32 : VOPC_Real_gfx11_gfx12<0x044>; 1945defm V_CMP_NE_I32 : VOPC_Real_gfx11_gfx12<0x045>; 1946defm V_CMP_GE_I32 : VOPC_Real_gfx11_gfx12<0x046>; 1947defm V_CMP_T_I32 : VOPC_Real_gfx11<0x047>; 1948defm V_CMP_F_U32 : VOPC_Real_gfx11<0x048>; 1949defm V_CMP_LT_U32 : VOPC_Real_gfx11_gfx12<0x049>; 1950defm V_CMP_EQ_U32 : VOPC_Real_gfx11_gfx12<0x04a>; 1951defm V_CMP_LE_U32 : VOPC_Real_gfx11_gfx12<0x04b>; 1952defm V_CMP_GT_U32 : VOPC_Real_gfx11_gfx12<0x04c>; 1953defm V_CMP_NE_U32 : VOPC_Real_gfx11_gfx12<0x04d>; 1954defm V_CMP_GE_U32 : VOPC_Real_gfx11_gfx12<0x04e>; 1955defm V_CMP_T_U32 : VOPC_Real_gfx11<0x04f>; 1956 1957defm V_CMP_F_I64 : VOPC_Real_gfx11<0x050>; 1958defm V_CMP_LT_I64 : VOPC_Real_gfx11_gfx12<0x051>; 1959defm V_CMP_EQ_I64 : VOPC_Real_gfx11_gfx12<0x052>; 1960defm V_CMP_LE_I64 : VOPC_Real_gfx11_gfx12<0x053>; 1961defm V_CMP_GT_I64 : VOPC_Real_gfx11_gfx12<0x054>; 1962defm V_CMP_NE_I64 : VOPC_Real_gfx11_gfx12<0x055>; 1963defm V_CMP_GE_I64 : VOPC_Real_gfx11_gfx12<0x056>; 1964defm V_CMP_T_I64 : VOPC_Real_gfx11<0x057>; 1965defm V_CMP_F_U64 : VOPC_Real_gfx11<0x058>; 1966defm V_CMP_LT_U64 : VOPC_Real_gfx11_gfx12<0x059>; 1967defm V_CMP_EQ_U64 : VOPC_Real_gfx11_gfx12<0x05a>; 1968defm V_CMP_LE_U64 : VOPC_Real_gfx11_gfx12<0x05b>; 1969defm V_CMP_GT_U64 : VOPC_Real_gfx11_gfx12<0x05c>; 1970defm V_CMP_NE_U64 : VOPC_Real_gfx11_gfx12<0x05d>; 1971defm V_CMP_GE_U64 : VOPC_Real_gfx11_gfx12<0x05e>; 1972defm V_CMP_T_U64 : VOPC_Real_gfx11<0x05f>; 1973 1974defm V_CMP_CLASS_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x07d, "v_cmp_class_f16">; 1975defm V_CMP_CLASS_F32 : VOPC_Real_gfx11_gfx12<0x07e>; 1976defm V_CMP_CLASS_F64 : VOPC_Real_gfx11_gfx12<0x07f>; 1977 1978defm V_CMPX_F_F16 : VOPCX_Real_t16_and_fake16_gfx11<0x080, "v_cmpx_f_f16">; 1979defm V_CMPX_LT_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x081, "v_cmpx_lt_f16">; 1980defm V_CMPX_EQ_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x082, "v_cmpx_eq_f16">; 1981defm V_CMPX_LE_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x083, "v_cmpx_le_f16">; 1982defm V_CMPX_GT_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x084, "v_cmpx_gt_f16">; 1983defm V_CMPX_LG_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x085, "v_cmpx_lg_f16">; 1984defm V_CMPX_GE_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x086, "v_cmpx_ge_f16">; 1985defm V_CMPX_O_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x087, "v_cmpx_o_f16">; 1986defm V_CMPX_U_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x088, "v_cmpx_u_f16">; 1987defm V_CMPX_NGE_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x089, "v_cmpx_nge_f16">; 1988defm V_CMPX_NLG_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x08a, "v_cmpx_nlg_f16">; 1989defm V_CMPX_NGT_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x08b, "v_cmpx_ngt_f16">; 1990defm V_CMPX_NLE_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x08c, "v_cmpx_nle_f16">; 1991defm V_CMPX_NEQ_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x08d, "v_cmpx_neq_f16">; 1992defm V_CMPX_NLT_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x08e, "v_cmpx_nlt_f16">; 1993defm V_CMPX_T_F16 : VOPCX_Real_t16_and_fake16_gfx11<0x08f, "v_cmpx_t_f16", "V_CMPX_TRU_F16", "v_cmpx_tru_f16">; 1994 1995defm V_CMPX_F_F32 : VOPCX_Real_gfx11<0x090>; 1996defm V_CMPX_LT_F32 : VOPCX_Real_gfx11_gfx12<0x091>; 1997defm V_CMPX_EQ_F32 : VOPCX_Real_gfx11_gfx12<0x092>; 1998defm V_CMPX_LE_F32 : VOPCX_Real_gfx11_gfx12<0x093>; 1999defm V_CMPX_GT_F32 : VOPCX_Real_gfx11_gfx12<0x094>; 2000defm V_CMPX_LG_F32 : VOPCX_Real_gfx11_gfx12<0x095>; 2001defm V_CMPX_GE_F32 : VOPCX_Real_gfx11_gfx12<0x096>; 2002defm V_CMPX_O_F32 : VOPCX_Real_gfx11_gfx12<0x097>; 2003defm V_CMPX_U_F32 : VOPCX_Real_gfx11_gfx12<0x098>; 2004defm V_CMPX_NGE_F32 : VOPCX_Real_gfx11_gfx12<0x099>; 2005defm V_CMPX_NLG_F32 : VOPCX_Real_gfx11_gfx12<0x09a>; 2006defm V_CMPX_NGT_F32 : VOPCX_Real_gfx11_gfx12<0x09b>; 2007defm V_CMPX_NLE_F32 : VOPCX_Real_gfx11_gfx12<0x09c>; 2008defm V_CMPX_NEQ_F32 : VOPCX_Real_gfx11_gfx12<0x09d>; 2009defm V_CMPX_NLT_F32 : VOPCX_Real_gfx11_gfx12<0x09e>; 2010defm V_CMPX_T_F32 : VOPCX_Real_with_name_gfx11<0x09f, "V_CMPX_TRU_F32", "v_cmpx_t_f32">; 2011 2012defm V_CMPX_F_F64 : VOPCX_Real_gfx11<0x0a0>; 2013defm V_CMPX_LT_F64 : VOPCX_Real_gfx11_gfx12<0x0a1>; 2014defm V_CMPX_EQ_F64 : VOPCX_Real_gfx11_gfx12<0x0a2>; 2015defm V_CMPX_LE_F64 : VOPCX_Real_gfx11_gfx12<0x0a3>; 2016defm V_CMPX_GT_F64 : VOPCX_Real_gfx11_gfx12<0x0a4>; 2017defm V_CMPX_LG_F64 : VOPCX_Real_gfx11_gfx12<0x0a5>; 2018defm V_CMPX_GE_F64 : VOPCX_Real_gfx11_gfx12<0x0a6>; 2019defm V_CMPX_O_F64 : VOPCX_Real_gfx11_gfx12<0x0a7>; 2020defm V_CMPX_U_F64 : VOPCX_Real_gfx11_gfx12<0x0a8>; 2021defm V_CMPX_NGE_F64 : VOPCX_Real_gfx11_gfx12<0x0a9>; 2022defm V_CMPX_NLG_F64 : VOPCX_Real_gfx11_gfx12<0x0aa>; 2023defm V_CMPX_NGT_F64 : VOPCX_Real_gfx11_gfx12<0x0ab>; 2024defm V_CMPX_NLE_F64 : VOPCX_Real_gfx11_gfx12<0x0ac>; 2025defm V_CMPX_NEQ_F64 : VOPCX_Real_gfx11_gfx12<0x0ad>; 2026defm V_CMPX_NLT_F64 : VOPCX_Real_gfx11_gfx12<0x0ae>; 2027defm V_CMPX_T_F64 : VOPCX_Real_with_name_gfx11<0x0af, "V_CMPX_TRU_F64", "v_cmpx_t_f64">; 2028 2029defm V_CMPX_LT_I16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0b1, "v_cmpx_lt_i16">; 2030defm V_CMPX_EQ_I16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0b2, "v_cmpx_eq_i16">; 2031defm V_CMPX_LE_I16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0b3, "v_cmpx_le_i16">; 2032defm V_CMPX_GT_I16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0b4, "v_cmpx_gt_i16">; 2033defm V_CMPX_NE_I16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0b5, "v_cmpx_ne_i16">; 2034defm V_CMPX_GE_I16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0b6, "v_cmpx_ge_i16">; 2035defm V_CMPX_LT_U16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0b9, "v_cmpx_lt_u16">; 2036defm V_CMPX_EQ_U16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0ba, "v_cmpx_eq_u16">; 2037defm V_CMPX_LE_U16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0bb, "v_cmpx_le_u16">; 2038defm V_CMPX_GT_U16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0bc, "v_cmpx_gt_u16">; 2039defm V_CMPX_NE_U16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0bd, "v_cmpx_ne_u16">; 2040defm V_CMPX_GE_U16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0be, "v_cmpx_ge_u16">; 2041 2042defm V_CMPX_F_I32 : VOPCX_Real_gfx11<0x0c0>; 2043defm V_CMPX_LT_I32 : VOPCX_Real_gfx11_gfx12<0x0c1>; 2044defm V_CMPX_EQ_I32 : VOPCX_Real_gfx11_gfx12<0x0c2>; 2045defm V_CMPX_LE_I32 : VOPCX_Real_gfx11_gfx12<0x0c3>; 2046defm V_CMPX_GT_I32 : VOPCX_Real_gfx11_gfx12<0x0c4>; 2047defm V_CMPX_NE_I32 : VOPCX_Real_gfx11_gfx12<0x0c5>; 2048defm V_CMPX_GE_I32 : VOPCX_Real_gfx11_gfx12<0x0c6>; 2049defm V_CMPX_T_I32 : VOPCX_Real_gfx11<0x0c7>; 2050defm V_CMPX_F_U32 : VOPCX_Real_gfx11<0x0c8>; 2051defm V_CMPX_LT_U32 : VOPCX_Real_gfx11_gfx12<0x0c9>; 2052defm V_CMPX_EQ_U32 : VOPCX_Real_gfx11_gfx12<0x0ca>; 2053defm V_CMPX_LE_U32 : VOPCX_Real_gfx11_gfx12<0x0cb>; 2054defm V_CMPX_GT_U32 : VOPCX_Real_gfx11_gfx12<0x0cc>; 2055defm V_CMPX_NE_U32 : VOPCX_Real_gfx11_gfx12<0x0cd>; 2056defm V_CMPX_GE_U32 : VOPCX_Real_gfx11_gfx12<0x0ce>; 2057defm V_CMPX_T_U32 : VOPCX_Real_gfx11<0x0cf>; 2058 2059defm V_CMPX_F_I64 : VOPCX_Real_gfx11<0x0d0>; 2060defm V_CMPX_LT_I64 : VOPCX_Real_gfx11_gfx12<0x0d1>; 2061defm V_CMPX_EQ_I64 : VOPCX_Real_gfx11_gfx12<0x0d2>; 2062defm V_CMPX_LE_I64 : VOPCX_Real_gfx11_gfx12<0x0d3>; 2063defm V_CMPX_GT_I64 : VOPCX_Real_gfx11_gfx12<0x0d4>; 2064defm V_CMPX_NE_I64 : VOPCX_Real_gfx11_gfx12<0x0d5>; 2065defm V_CMPX_GE_I64 : VOPCX_Real_gfx11_gfx12<0x0d6>; 2066defm V_CMPX_T_I64 : VOPCX_Real_gfx11<0x0d7>; 2067defm V_CMPX_F_U64 : VOPCX_Real_gfx11<0x0d8>; 2068defm V_CMPX_LT_U64 : VOPCX_Real_gfx11_gfx12<0x0d9>; 2069defm V_CMPX_EQ_U64 : VOPCX_Real_gfx11_gfx12<0x0da>; 2070defm V_CMPX_LE_U64 : VOPCX_Real_gfx11_gfx12<0x0db>; 2071defm V_CMPX_GT_U64 : VOPCX_Real_gfx11_gfx12<0x0dc>; 2072defm V_CMPX_NE_U64 : VOPCX_Real_gfx11_gfx12<0x0dd>; 2073defm V_CMPX_GE_U64 : VOPCX_Real_gfx11_gfx12<0x0de>; 2074defm V_CMPX_T_U64 : VOPCX_Real_gfx11<0x0df>; 2075defm V_CMPX_CLASS_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0fd, "v_cmpx_class_f16">; 2076defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx11_gfx12<0x0fe>; 2077defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx11_gfx12<0x0ff>; 2078 2079let AssemblerPredicate = isGFX11Only in { 2080 def : AMDGPUMnemonicAlias<"v_cmp_tru_i32", "v_cmp_t_i32">; 2081 def : AMDGPUMnemonicAlias<"v_cmp_tru_u32", "v_cmp_t_u32">; 2082 def : AMDGPUMnemonicAlias<"v_cmp_tru_i64", "v_cmp_t_i64">; 2083 def : AMDGPUMnemonicAlias<"v_cmp_tru_u64", "v_cmp_t_u64">; 2084 def : AMDGPUMnemonicAlias<"v_cmpx_tru_i32", "v_cmpx_t_i32">; 2085 def : AMDGPUMnemonicAlias<"v_cmpx_tru_u32", "v_cmpx_t_u32">; 2086 def : AMDGPUMnemonicAlias<"v_cmpx_tru_i64", "v_cmpx_t_i64">; 2087 def : AMDGPUMnemonicAlias<"v_cmpx_tru_u64", "v_cmpx_t_u64">; 2088} 2089 2090//===----------------------------------------------------------------------===// 2091// GFX10. 2092//===----------------------------------------------------------------------===// 2093 2094let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in { 2095 multiclass VOPC_Real_gfx10<bits<9> op> { 2096 def _e32_gfx10 : 2097 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>, 2098 VOPCe<op{7-0}>; 2099 def _e64_gfx10 : 2100 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 2101 VOP3a_gfx10<{0, op}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 2102 // Encoding used for VOPC instructions encoded as VOP3 differs from 2103 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 2104 bits<8> sdst; 2105 let Inst{7-0} = sdst; 2106 } 2107 2108 if !cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then 2109 def _sdwa_gfx10 : 2110 VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>, 2111 VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 2112 2113 defm : VOPCInstAliases<NAME, "gfx10">; 2114 } 2115 2116 multiclass VOPCX_Real_gfx10<bits<9> op> { 2117 def _e32_gfx10 : 2118 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32"), SIEncodingFamily.GFX10>, 2119 VOPCe<op{7-0}> { 2120 let AsmString = !subst("_nosdst", "", !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").PseudoInstr) 2121 # " " # !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").AsmOperands; 2122 } 2123 2124 def _e64_gfx10 : 2125 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_nosdst_e64"), SIEncodingFamily.GFX10>, 2126 VOP3a_gfx10<{0, op}, !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Pfl> { 2127 let Inst{7-0} = ?; // sdst 2128 let AsmString = !subst("_nosdst", "", !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Mnemonic) 2129 # "{_e64} " # !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").AsmOperands; 2130 } 2131 2132 if !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").Pfl.HasExtSDWA9 then 2133 def _sdwa_gfx10 : 2134 VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa")>, 2135 VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Pfl> { 2136 let AsmString = !subst("_nosdst", "", !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Mnemonic) 2137 # "{_sdwa} " # !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").AsmOperands9; 2138 } 2139 2140 defm : VOPCXInstAliases<NAME, "gfx10">; 2141 } 2142} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" 2143 2144defm V_CMP_LT_I16 : VOPC_Real_gfx10<0x089>; 2145defm V_CMP_EQ_I16 : VOPC_Real_gfx10<0x08a>; 2146defm V_CMP_LE_I16 : VOPC_Real_gfx10<0x08b>; 2147defm V_CMP_GT_I16 : VOPC_Real_gfx10<0x08c>; 2148defm V_CMP_NE_I16 : VOPC_Real_gfx10<0x08d>; 2149defm V_CMP_GE_I16 : VOPC_Real_gfx10<0x08e>; 2150defm V_CMP_CLASS_F16 : VOPC_Real_gfx10<0x08f>; 2151defm V_CMPX_LT_I16 : VOPCX_Real_gfx10<0x099>; 2152defm V_CMPX_EQ_I16 : VOPCX_Real_gfx10<0x09a>; 2153defm V_CMPX_LE_I16 : VOPCX_Real_gfx10<0x09b>; 2154defm V_CMPX_GT_I16 : VOPCX_Real_gfx10<0x09c>; 2155defm V_CMPX_NE_I16 : VOPCX_Real_gfx10<0x09d>; 2156defm V_CMPX_GE_I16 : VOPCX_Real_gfx10<0x09e>; 2157defm V_CMPX_CLASS_F16 : VOPCX_Real_gfx10<0x09f>; 2158defm V_CMP_LT_U16 : VOPC_Real_gfx10<0x0a9>; 2159defm V_CMP_EQ_U16 : VOPC_Real_gfx10<0x0aa>; 2160defm V_CMP_LE_U16 : VOPC_Real_gfx10<0x0ab>; 2161defm V_CMP_GT_U16 : VOPC_Real_gfx10<0x0ac>; 2162defm V_CMP_NE_U16 : VOPC_Real_gfx10<0x0ad>; 2163defm V_CMP_GE_U16 : VOPC_Real_gfx10<0x0ae>; 2164defm V_CMPX_LT_U16 : VOPCX_Real_gfx10<0x0b9>; 2165defm V_CMPX_EQ_U16 : VOPCX_Real_gfx10<0x0ba>; 2166defm V_CMPX_LE_U16 : VOPCX_Real_gfx10<0x0bb>; 2167defm V_CMPX_GT_U16 : VOPCX_Real_gfx10<0x0bc>; 2168defm V_CMPX_NE_U16 : VOPCX_Real_gfx10<0x0bd>; 2169defm V_CMPX_GE_U16 : VOPCX_Real_gfx10<0x0be>; 2170defm V_CMP_F_F16 : VOPC_Real_gfx10<0x0c8>; 2171defm V_CMP_LT_F16 : VOPC_Real_gfx10<0x0c9>; 2172defm V_CMP_EQ_F16 : VOPC_Real_gfx10<0x0ca>; 2173defm V_CMP_LE_F16 : VOPC_Real_gfx10<0x0cb>; 2174defm V_CMP_GT_F16 : VOPC_Real_gfx10<0x0cc>; 2175defm V_CMP_LG_F16 : VOPC_Real_gfx10<0x0cd>; 2176defm V_CMP_GE_F16 : VOPC_Real_gfx10<0x0ce>; 2177defm V_CMP_O_F16 : VOPC_Real_gfx10<0x0cf>; 2178defm V_CMPX_F_F16 : VOPCX_Real_gfx10<0x0d8>; 2179defm V_CMPX_LT_F16 : VOPCX_Real_gfx10<0x0d9>; 2180defm V_CMPX_EQ_F16 : VOPCX_Real_gfx10<0x0da>; 2181defm V_CMPX_LE_F16 : VOPCX_Real_gfx10<0x0db>; 2182defm V_CMPX_GT_F16 : VOPCX_Real_gfx10<0x0dc>; 2183defm V_CMPX_LG_F16 : VOPCX_Real_gfx10<0x0dd>; 2184defm V_CMPX_GE_F16 : VOPCX_Real_gfx10<0x0de>; 2185defm V_CMPX_O_F16 : VOPCX_Real_gfx10<0x0df>; 2186defm V_CMP_U_F16 : VOPC_Real_gfx10<0x0e8>; 2187defm V_CMP_NGE_F16 : VOPC_Real_gfx10<0x0e9>; 2188defm V_CMP_NLG_F16 : VOPC_Real_gfx10<0x0ea>; 2189defm V_CMP_NGT_F16 : VOPC_Real_gfx10<0x0eb>; 2190defm V_CMP_NLE_F16 : VOPC_Real_gfx10<0x0ec>; 2191defm V_CMP_NEQ_F16 : VOPC_Real_gfx10<0x0ed>; 2192defm V_CMP_NLT_F16 : VOPC_Real_gfx10<0x0ee>; 2193defm V_CMP_TRU_F16 : VOPC_Real_gfx10<0x0ef>; 2194defm V_CMPX_U_F16 : VOPCX_Real_gfx10<0x0f8>; 2195defm V_CMPX_NGE_F16 : VOPCX_Real_gfx10<0x0f9>; 2196defm V_CMPX_NLG_F16 : VOPCX_Real_gfx10<0x0fa>; 2197defm V_CMPX_NGT_F16 : VOPCX_Real_gfx10<0x0fb>; 2198defm V_CMPX_NLE_F16 : VOPCX_Real_gfx10<0x0fc>; 2199defm V_CMPX_NEQ_F16 : VOPCX_Real_gfx10<0x0fd>; 2200defm V_CMPX_NLT_F16 : VOPCX_Real_gfx10<0x0fe>; 2201defm V_CMPX_TRU_F16 : VOPCX_Real_gfx10<0x0ff>; 2202 2203//===----------------------------------------------------------------------===// 2204// GFX6, GFX7, GFX10. 2205//===----------------------------------------------------------------------===// 2206 2207let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 2208 multiclass VOPC_Real_gfx6_gfx7<bits<9> op> { 2209 def _e32_gfx6_gfx7 : 2210 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>, 2211 VOPCe<op{7-0}>; 2212 def _e64_gfx6_gfx7 : 2213 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 2214 VOP3a_gfx6_gfx7<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 2215 // Encoding used for VOPC instructions encoded as VOP3 differs from 2216 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 2217 bits<8> sdst; 2218 let Inst{7-0} = sdst; 2219 } 2220 2221 defm : VOPCInstAliases<NAME, "gfx6_gfx7">; 2222 } 2223} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 2224 2225multiclass VOPC_Real_gfx6_gfx7_gfx10<bits<9> op> : 2226 VOPC_Real_gfx6_gfx7<op>, VOPC_Real_gfx10<op>; 2227 2228multiclass VOPCX_Real_gfx6_gfx7<bits<9> op> : 2229 VOPC_Real_gfx6_gfx7<op>; 2230 2231multiclass VOPCX_Real_gfx6_gfx7_gfx10 <bits<9> op> : 2232 VOPC_Real_gfx6_gfx7<op>, VOPCX_Real_gfx10<op>; 2233 2234multiclass VOPC_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> : 2235 VOPC_Real_gfx6_gfx7_gfx10<op>, VOPC_Real_Base<GFX11Gen, op>; 2236 2237multiclass VOPCX_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> : 2238 VOPCX_Real_gfx6_gfx7_gfx10<op>, VOPCX_Real<GFX11Gen, op>; 2239 2240multiclass VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<9> op> : 2241 VOPC_Real_gfx6_gfx7_gfx10_gfx11<op>, VOPC_Real_Base<GFX12Gen, op>; 2242 2243defm V_CMP_F_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x000>; 2244defm V_CMP_LT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x001>; 2245defm V_CMP_EQ_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x002>; 2246defm V_CMP_LE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x003>; 2247defm V_CMP_GT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x004>; 2248defm V_CMP_LG_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x005>; 2249defm V_CMP_GE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x006>; 2250defm V_CMP_O_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x007>; 2251defm V_CMP_U_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x008>; 2252defm V_CMP_NGE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x009>; 2253defm V_CMP_NLG_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00a>; 2254defm V_CMP_NGT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00b>; 2255defm V_CMP_NLE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00c>; 2256defm V_CMP_NEQ_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00d>; 2257defm V_CMP_NLT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00e>; 2258defm V_CMP_TRU_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00f>; 2259defm V_CMPX_F_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x010>; 2260defm V_CMPX_LT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x011>; 2261defm V_CMPX_EQ_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x012>; 2262defm V_CMPX_LE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x013>; 2263defm V_CMPX_GT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x014>; 2264defm V_CMPX_LG_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x015>; 2265defm V_CMPX_GE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x016>; 2266defm V_CMPX_O_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x017>; 2267defm V_CMPX_U_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x018>; 2268defm V_CMPX_NGE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x019>; 2269defm V_CMPX_NLG_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01a>; 2270defm V_CMPX_NGT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01b>; 2271defm V_CMPX_NLE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01c>; 2272defm V_CMPX_NEQ_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01d>; 2273defm V_CMPX_NLT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01e>; 2274defm V_CMPX_TRU_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01f>; 2275defm V_CMP_F_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x020>; 2276defm V_CMP_LT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x021>; 2277defm V_CMP_EQ_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x022>; 2278defm V_CMP_LE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x023>; 2279defm V_CMP_GT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x024>; 2280defm V_CMP_LG_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x025>; 2281defm V_CMP_GE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x026>; 2282defm V_CMP_O_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x027>; 2283defm V_CMP_U_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x028>; 2284defm V_CMP_NGE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x029>; 2285defm V_CMP_NLG_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02a>; 2286defm V_CMP_NGT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02b>; 2287defm V_CMP_NLE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02c>; 2288defm V_CMP_NEQ_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02d>; 2289defm V_CMP_NLT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02e>; 2290defm V_CMP_TRU_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x02f>; 2291defm V_CMPX_F_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x030>; 2292defm V_CMPX_LT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x031>; 2293defm V_CMPX_EQ_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x032>; 2294defm V_CMPX_LE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x033>; 2295defm V_CMPX_GT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x034>; 2296defm V_CMPX_LG_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x035>; 2297defm V_CMPX_GE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x036>; 2298defm V_CMPX_O_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x037>; 2299defm V_CMPX_U_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x038>; 2300defm V_CMPX_NGE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x039>; 2301defm V_CMPX_NLG_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03a>; 2302defm V_CMPX_NGT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03b>; 2303defm V_CMPX_NLE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03c>; 2304defm V_CMPX_NEQ_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03d>; 2305defm V_CMPX_NLT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03e>; 2306defm V_CMPX_TRU_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03f>; 2307defm V_CMPS_F_F32 : VOPC_Real_gfx6_gfx7<0x040>; 2308defm V_CMPS_LT_F32 : VOPC_Real_gfx6_gfx7<0x041>; 2309defm V_CMPS_EQ_F32 : VOPC_Real_gfx6_gfx7<0x042>; 2310defm V_CMPS_LE_F32 : VOPC_Real_gfx6_gfx7<0x043>; 2311defm V_CMPS_GT_F32 : VOPC_Real_gfx6_gfx7<0x044>; 2312defm V_CMPS_LG_F32 : VOPC_Real_gfx6_gfx7<0x045>; 2313defm V_CMPS_GE_F32 : VOPC_Real_gfx6_gfx7<0x046>; 2314defm V_CMPS_O_F32 : VOPC_Real_gfx6_gfx7<0x047>; 2315defm V_CMPS_U_F32 : VOPC_Real_gfx6_gfx7<0x048>; 2316defm V_CMPS_NGE_F32 : VOPC_Real_gfx6_gfx7<0x049>; 2317defm V_CMPS_NLG_F32 : VOPC_Real_gfx6_gfx7<0x04a>; 2318defm V_CMPS_NGT_F32 : VOPC_Real_gfx6_gfx7<0x04b>; 2319defm V_CMPS_NLE_F32 : VOPC_Real_gfx6_gfx7<0x04c>; 2320defm V_CMPS_NEQ_F32 : VOPC_Real_gfx6_gfx7<0x04d>; 2321defm V_CMPS_NLT_F32 : VOPC_Real_gfx6_gfx7<0x04e>; 2322defm V_CMPS_TRU_F32 : VOPC_Real_gfx6_gfx7<0x04f>; 2323defm V_CMPSX_F_F32 : VOPCX_Real_gfx6_gfx7<0x050>; 2324defm V_CMPSX_LT_F32 : VOPCX_Real_gfx6_gfx7<0x051>; 2325defm V_CMPSX_EQ_F32 : VOPCX_Real_gfx6_gfx7<0x052>; 2326defm V_CMPSX_LE_F32 : VOPCX_Real_gfx6_gfx7<0x053>; 2327defm V_CMPSX_GT_F32 : VOPCX_Real_gfx6_gfx7<0x054>; 2328defm V_CMPSX_LG_F32 : VOPCX_Real_gfx6_gfx7<0x055>; 2329defm V_CMPSX_GE_F32 : VOPCX_Real_gfx6_gfx7<0x056>; 2330defm V_CMPSX_O_F32 : VOPCX_Real_gfx6_gfx7<0x057>; 2331defm V_CMPSX_U_F32 : VOPCX_Real_gfx6_gfx7<0x058>; 2332defm V_CMPSX_NGE_F32 : VOPCX_Real_gfx6_gfx7<0x059>; 2333defm V_CMPSX_NLG_F32 : VOPCX_Real_gfx6_gfx7<0x05a>; 2334defm V_CMPSX_NGT_F32 : VOPCX_Real_gfx6_gfx7<0x05b>; 2335defm V_CMPSX_NLE_F32 : VOPCX_Real_gfx6_gfx7<0x05c>; 2336defm V_CMPSX_NEQ_F32 : VOPCX_Real_gfx6_gfx7<0x05d>; 2337defm V_CMPSX_NLT_F32 : VOPCX_Real_gfx6_gfx7<0x05e>; 2338defm V_CMPSX_TRU_F32 : VOPCX_Real_gfx6_gfx7<0x05f>; 2339defm V_CMPS_F_F64 : VOPC_Real_gfx6_gfx7<0x060>; 2340defm V_CMPS_LT_F64 : VOPC_Real_gfx6_gfx7<0x061>; 2341defm V_CMPS_EQ_F64 : VOPC_Real_gfx6_gfx7<0x062>; 2342defm V_CMPS_LE_F64 : VOPC_Real_gfx6_gfx7<0x063>; 2343defm V_CMPS_GT_F64 : VOPC_Real_gfx6_gfx7<0x064>; 2344defm V_CMPS_LG_F64 : VOPC_Real_gfx6_gfx7<0x065>; 2345defm V_CMPS_GE_F64 : VOPC_Real_gfx6_gfx7<0x066>; 2346defm V_CMPS_O_F64 : VOPC_Real_gfx6_gfx7<0x067>; 2347defm V_CMPS_U_F64 : VOPC_Real_gfx6_gfx7<0x068>; 2348defm V_CMPS_NGE_F64 : VOPC_Real_gfx6_gfx7<0x069>; 2349defm V_CMPS_NLG_F64 : VOPC_Real_gfx6_gfx7<0x06a>; 2350defm V_CMPS_NGT_F64 : VOPC_Real_gfx6_gfx7<0x06b>; 2351defm V_CMPS_NLE_F64 : VOPC_Real_gfx6_gfx7<0x06c>; 2352defm V_CMPS_NEQ_F64 : VOPC_Real_gfx6_gfx7<0x06d>; 2353defm V_CMPS_NLT_F64 : VOPC_Real_gfx6_gfx7<0x06e>; 2354defm V_CMPS_TRU_F64 : VOPC_Real_gfx6_gfx7<0x06f>; 2355defm V_CMPSX_F_F64 : VOPCX_Real_gfx6_gfx7<0x070>; 2356defm V_CMPSX_LT_F64 : VOPCX_Real_gfx6_gfx7<0x071>; 2357defm V_CMPSX_EQ_F64 : VOPCX_Real_gfx6_gfx7<0x072>; 2358defm V_CMPSX_LE_F64 : VOPCX_Real_gfx6_gfx7<0x073>; 2359defm V_CMPSX_GT_F64 : VOPCX_Real_gfx6_gfx7<0x074>; 2360defm V_CMPSX_LG_F64 : VOPCX_Real_gfx6_gfx7<0x075>; 2361defm V_CMPSX_GE_F64 : VOPCX_Real_gfx6_gfx7<0x076>; 2362defm V_CMPSX_O_F64 : VOPCX_Real_gfx6_gfx7<0x077>; 2363defm V_CMPSX_U_F64 : VOPCX_Real_gfx6_gfx7<0x078>; 2364defm V_CMPSX_NGE_F64 : VOPCX_Real_gfx6_gfx7<0x079>; 2365defm V_CMPSX_NLG_F64 : VOPCX_Real_gfx6_gfx7<0x07a>; 2366defm V_CMPSX_NGT_F64 : VOPCX_Real_gfx6_gfx7<0x07b>; 2367defm V_CMPSX_NLE_F64 : VOPCX_Real_gfx6_gfx7<0x07c>; 2368defm V_CMPSX_NEQ_F64 : VOPCX_Real_gfx6_gfx7<0x07d>; 2369defm V_CMPSX_NLT_F64 : VOPCX_Real_gfx6_gfx7<0x07e>; 2370defm V_CMPSX_TRU_F64 : VOPCX_Real_gfx6_gfx7<0x07f>; 2371defm V_CMP_F_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x080>; 2372defm V_CMP_LT_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x081>; 2373defm V_CMP_EQ_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x082>; 2374defm V_CMP_LE_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x083>; 2375defm V_CMP_GT_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x084>; 2376defm V_CMP_NE_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x085>; 2377defm V_CMP_GE_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x086>; 2378defm V_CMP_T_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x087>; 2379defm V_CMP_CLASS_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x088>; 2380defm V_CMPX_F_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x090>; 2381defm V_CMPX_LT_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x091>; 2382defm V_CMPX_EQ_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x092>; 2383defm V_CMPX_LE_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x093>; 2384defm V_CMPX_GT_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x094>; 2385defm V_CMPX_NE_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x095>; 2386defm V_CMPX_GE_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x096>; 2387defm V_CMPX_T_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x097>; 2388defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x098>; 2389defm V_CMP_F_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a0>; 2390defm V_CMP_LT_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a1>; 2391defm V_CMP_EQ_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a2>; 2392defm V_CMP_LE_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a3>; 2393defm V_CMP_GT_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a4>; 2394defm V_CMP_NE_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a5>; 2395defm V_CMP_GE_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a6>; 2396defm V_CMP_T_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a7>; 2397defm V_CMP_CLASS_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a8>; 2398defm V_CMPX_F_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b0>; 2399defm V_CMPX_LT_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b1>; 2400defm V_CMPX_EQ_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b2>; 2401defm V_CMPX_LE_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b3>; 2402defm V_CMPX_GT_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b4>; 2403defm V_CMPX_NE_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b5>; 2404defm V_CMPX_GE_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b6>; 2405defm V_CMPX_T_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b7>; 2406defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b8>; 2407defm V_CMP_F_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c0>; 2408defm V_CMP_LT_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c1>; 2409defm V_CMP_EQ_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c2>; 2410defm V_CMP_LE_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c3>; 2411defm V_CMP_GT_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c4>; 2412defm V_CMP_NE_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c5>; 2413defm V_CMP_GE_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c6>; 2414defm V_CMP_T_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c7>; 2415defm V_CMPX_F_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d0>; 2416defm V_CMPX_LT_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d1>; 2417defm V_CMPX_EQ_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d2>; 2418defm V_CMPX_LE_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d3>; 2419defm V_CMPX_GT_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d4>; 2420defm V_CMPX_NE_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d5>; 2421defm V_CMPX_GE_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d6>; 2422defm V_CMPX_T_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d7>; 2423defm V_CMP_F_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e0>; 2424defm V_CMP_LT_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e1>; 2425defm V_CMP_EQ_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e2>; 2426defm V_CMP_LE_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e3>; 2427defm V_CMP_GT_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e4>; 2428defm V_CMP_NE_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e5>; 2429defm V_CMP_GE_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e6>; 2430defm V_CMP_T_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e7>; 2431defm V_CMPX_F_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f0>; 2432defm V_CMPX_LT_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f1>; 2433defm V_CMPX_EQ_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f2>; 2434defm V_CMPX_LE_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f3>; 2435defm V_CMPX_GT_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f4>; 2436defm V_CMPX_NE_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f5>; 2437defm V_CMPX_GE_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f6>; 2438defm V_CMPX_T_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f7>; 2439 2440//===----------------------------------------------------------------------===// 2441// GFX8, GFX9 (VI). 2442//===----------------------------------------------------------------------===// 2443 2444multiclass VOPC_Real_vi <bits<10> op> { 2445 let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 2446 def _e32_vi : 2447 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, 2448 VOPCe<op{7-0}>; 2449 2450 def _e64_vi : 2451 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 2452 VOP3a_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 2453 // Encoding used for VOPC instructions encoded as VOP3 2454 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst 2455 bits<8> sdst; 2456 let Inst{7-0} = sdst; 2457 } 2458 } 2459 2460 if !cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA then 2461 def _sdwa_vi : 2462 VOP_SDWA8_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>, 2463 VOPC_SDWAe <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 2464 2465 if !cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then 2466 def _sdwa_gfx9 : 2467 VOP_SDWA9_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>, 2468 VOPC_SDWA9e <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 2469 2470 let AssemblerPredicate = isGFX8GFX9 in { 2471 defm : VOPCInstAliases<NAME, "vi">; 2472 } 2473} 2474 2475defm V_CMP_CLASS_F32 : VOPC_Real_vi <0x10>; 2476defm V_CMPX_CLASS_F32 : VOPC_Real_vi <0x11>; 2477defm V_CMP_CLASS_F64 : VOPC_Real_vi <0x12>; 2478defm V_CMPX_CLASS_F64 : VOPC_Real_vi <0x13>; 2479defm V_CMP_CLASS_F16 : VOPC_Real_vi <0x14>; 2480defm V_CMPX_CLASS_F16 : VOPC_Real_vi <0x15>; 2481 2482defm V_CMP_F_F16 : VOPC_Real_vi <0x20>; 2483defm V_CMP_LT_F16 : VOPC_Real_vi <0x21>; 2484defm V_CMP_EQ_F16 : VOPC_Real_vi <0x22>; 2485defm V_CMP_LE_F16 : VOPC_Real_vi <0x23>; 2486defm V_CMP_GT_F16 : VOPC_Real_vi <0x24>; 2487defm V_CMP_LG_F16 : VOPC_Real_vi <0x25>; 2488defm V_CMP_GE_F16 : VOPC_Real_vi <0x26>; 2489defm V_CMP_O_F16 : VOPC_Real_vi <0x27>; 2490defm V_CMP_U_F16 : VOPC_Real_vi <0x28>; 2491defm V_CMP_NGE_F16 : VOPC_Real_vi <0x29>; 2492defm V_CMP_NLG_F16 : VOPC_Real_vi <0x2a>; 2493defm V_CMP_NGT_F16 : VOPC_Real_vi <0x2b>; 2494defm V_CMP_NLE_F16 : VOPC_Real_vi <0x2c>; 2495defm V_CMP_NEQ_F16 : VOPC_Real_vi <0x2d>; 2496defm V_CMP_NLT_F16 : VOPC_Real_vi <0x2e>; 2497defm V_CMP_TRU_F16 : VOPC_Real_vi <0x2f>; 2498 2499defm V_CMPX_F_F16 : VOPC_Real_vi <0x30>; 2500defm V_CMPX_LT_F16 : VOPC_Real_vi <0x31>; 2501defm V_CMPX_EQ_F16 : VOPC_Real_vi <0x32>; 2502defm V_CMPX_LE_F16 : VOPC_Real_vi <0x33>; 2503defm V_CMPX_GT_F16 : VOPC_Real_vi <0x34>; 2504defm V_CMPX_LG_F16 : VOPC_Real_vi <0x35>; 2505defm V_CMPX_GE_F16 : VOPC_Real_vi <0x36>; 2506defm V_CMPX_O_F16 : VOPC_Real_vi <0x37>; 2507defm V_CMPX_U_F16 : VOPC_Real_vi <0x38>; 2508defm V_CMPX_NGE_F16 : VOPC_Real_vi <0x39>; 2509defm V_CMPX_NLG_F16 : VOPC_Real_vi <0x3a>; 2510defm V_CMPX_NGT_F16 : VOPC_Real_vi <0x3b>; 2511defm V_CMPX_NLE_F16 : VOPC_Real_vi <0x3c>; 2512defm V_CMPX_NEQ_F16 : VOPC_Real_vi <0x3d>; 2513defm V_CMPX_NLT_F16 : VOPC_Real_vi <0x3e>; 2514defm V_CMPX_TRU_F16 : VOPC_Real_vi <0x3f>; 2515 2516defm V_CMP_F_F32 : VOPC_Real_vi <0x40>; 2517defm V_CMP_LT_F32 : VOPC_Real_vi <0x41>; 2518defm V_CMP_EQ_F32 : VOPC_Real_vi <0x42>; 2519defm V_CMP_LE_F32 : VOPC_Real_vi <0x43>; 2520defm V_CMP_GT_F32 : VOPC_Real_vi <0x44>; 2521defm V_CMP_LG_F32 : VOPC_Real_vi <0x45>; 2522defm V_CMP_GE_F32 : VOPC_Real_vi <0x46>; 2523defm V_CMP_O_F32 : VOPC_Real_vi <0x47>; 2524defm V_CMP_U_F32 : VOPC_Real_vi <0x48>; 2525defm V_CMP_NGE_F32 : VOPC_Real_vi <0x49>; 2526defm V_CMP_NLG_F32 : VOPC_Real_vi <0x4a>; 2527defm V_CMP_NGT_F32 : VOPC_Real_vi <0x4b>; 2528defm V_CMP_NLE_F32 : VOPC_Real_vi <0x4c>; 2529defm V_CMP_NEQ_F32 : VOPC_Real_vi <0x4d>; 2530defm V_CMP_NLT_F32 : VOPC_Real_vi <0x4e>; 2531defm V_CMP_TRU_F32 : VOPC_Real_vi <0x4f>; 2532 2533defm V_CMPX_F_F32 : VOPC_Real_vi <0x50>; 2534defm V_CMPX_LT_F32 : VOPC_Real_vi <0x51>; 2535defm V_CMPX_EQ_F32 : VOPC_Real_vi <0x52>; 2536defm V_CMPX_LE_F32 : VOPC_Real_vi <0x53>; 2537defm V_CMPX_GT_F32 : VOPC_Real_vi <0x54>; 2538defm V_CMPX_LG_F32 : VOPC_Real_vi <0x55>; 2539defm V_CMPX_GE_F32 : VOPC_Real_vi <0x56>; 2540defm V_CMPX_O_F32 : VOPC_Real_vi <0x57>; 2541defm V_CMPX_U_F32 : VOPC_Real_vi <0x58>; 2542defm V_CMPX_NGE_F32 : VOPC_Real_vi <0x59>; 2543defm V_CMPX_NLG_F32 : VOPC_Real_vi <0x5a>; 2544defm V_CMPX_NGT_F32 : VOPC_Real_vi <0x5b>; 2545defm V_CMPX_NLE_F32 : VOPC_Real_vi <0x5c>; 2546defm V_CMPX_NEQ_F32 : VOPC_Real_vi <0x5d>; 2547defm V_CMPX_NLT_F32 : VOPC_Real_vi <0x5e>; 2548defm V_CMPX_TRU_F32 : VOPC_Real_vi <0x5f>; 2549 2550defm V_CMP_F_F64 : VOPC_Real_vi <0x60>; 2551defm V_CMP_LT_F64 : VOPC_Real_vi <0x61>; 2552defm V_CMP_EQ_F64 : VOPC_Real_vi <0x62>; 2553defm V_CMP_LE_F64 : VOPC_Real_vi <0x63>; 2554defm V_CMP_GT_F64 : VOPC_Real_vi <0x64>; 2555defm V_CMP_LG_F64 : VOPC_Real_vi <0x65>; 2556defm V_CMP_GE_F64 : VOPC_Real_vi <0x66>; 2557defm V_CMP_O_F64 : VOPC_Real_vi <0x67>; 2558defm V_CMP_U_F64 : VOPC_Real_vi <0x68>; 2559defm V_CMP_NGE_F64 : VOPC_Real_vi <0x69>; 2560defm V_CMP_NLG_F64 : VOPC_Real_vi <0x6a>; 2561defm V_CMP_NGT_F64 : VOPC_Real_vi <0x6b>; 2562defm V_CMP_NLE_F64 : VOPC_Real_vi <0x6c>; 2563defm V_CMP_NEQ_F64 : VOPC_Real_vi <0x6d>; 2564defm V_CMP_NLT_F64 : VOPC_Real_vi <0x6e>; 2565defm V_CMP_TRU_F64 : VOPC_Real_vi <0x6f>; 2566 2567defm V_CMPX_F_F64 : VOPC_Real_vi <0x70>; 2568defm V_CMPX_LT_F64 : VOPC_Real_vi <0x71>; 2569defm V_CMPX_EQ_F64 : VOPC_Real_vi <0x72>; 2570defm V_CMPX_LE_F64 : VOPC_Real_vi <0x73>; 2571defm V_CMPX_GT_F64 : VOPC_Real_vi <0x74>; 2572defm V_CMPX_LG_F64 : VOPC_Real_vi <0x75>; 2573defm V_CMPX_GE_F64 : VOPC_Real_vi <0x76>; 2574defm V_CMPX_O_F64 : VOPC_Real_vi <0x77>; 2575defm V_CMPX_U_F64 : VOPC_Real_vi <0x78>; 2576defm V_CMPX_NGE_F64 : VOPC_Real_vi <0x79>; 2577defm V_CMPX_NLG_F64 : VOPC_Real_vi <0x7a>; 2578defm V_CMPX_NGT_F64 : VOPC_Real_vi <0x7b>; 2579defm V_CMPX_NLE_F64 : VOPC_Real_vi <0x7c>; 2580defm V_CMPX_NEQ_F64 : VOPC_Real_vi <0x7d>; 2581defm V_CMPX_NLT_F64 : VOPC_Real_vi <0x7e>; 2582defm V_CMPX_TRU_F64 : VOPC_Real_vi <0x7f>; 2583 2584defm V_CMP_F_I16 : VOPC_Real_vi <0xa0>; 2585defm V_CMP_LT_I16 : VOPC_Real_vi <0xa1>; 2586defm V_CMP_EQ_I16 : VOPC_Real_vi <0xa2>; 2587defm V_CMP_LE_I16 : VOPC_Real_vi <0xa3>; 2588defm V_CMP_GT_I16 : VOPC_Real_vi <0xa4>; 2589defm V_CMP_NE_I16 : VOPC_Real_vi <0xa5>; 2590defm V_CMP_GE_I16 : VOPC_Real_vi <0xa6>; 2591defm V_CMP_T_I16 : VOPC_Real_vi <0xa7>; 2592 2593defm V_CMP_F_U16 : VOPC_Real_vi <0xa8>; 2594defm V_CMP_LT_U16 : VOPC_Real_vi <0xa9>; 2595defm V_CMP_EQ_U16 : VOPC_Real_vi <0xaa>; 2596defm V_CMP_LE_U16 : VOPC_Real_vi <0xab>; 2597defm V_CMP_GT_U16 : VOPC_Real_vi <0xac>; 2598defm V_CMP_NE_U16 : VOPC_Real_vi <0xad>; 2599defm V_CMP_GE_U16 : VOPC_Real_vi <0xae>; 2600defm V_CMP_T_U16 : VOPC_Real_vi <0xaf>; 2601 2602defm V_CMPX_F_I16 : VOPC_Real_vi <0xb0>; 2603defm V_CMPX_LT_I16 : VOPC_Real_vi <0xb1>; 2604defm V_CMPX_EQ_I16 : VOPC_Real_vi <0xb2>; 2605defm V_CMPX_LE_I16 : VOPC_Real_vi <0xb3>; 2606defm V_CMPX_GT_I16 : VOPC_Real_vi <0xb4>; 2607defm V_CMPX_NE_I16 : VOPC_Real_vi <0xb5>; 2608defm V_CMPX_GE_I16 : VOPC_Real_vi <0xb6>; 2609defm V_CMPX_T_I16 : VOPC_Real_vi <0xb7>; 2610 2611defm V_CMPX_F_U16 : VOPC_Real_vi <0xb8>; 2612defm V_CMPX_LT_U16 : VOPC_Real_vi <0xb9>; 2613defm V_CMPX_EQ_U16 : VOPC_Real_vi <0xba>; 2614defm V_CMPX_LE_U16 : VOPC_Real_vi <0xbb>; 2615defm V_CMPX_GT_U16 : VOPC_Real_vi <0xbc>; 2616defm V_CMPX_NE_U16 : VOPC_Real_vi <0xbd>; 2617defm V_CMPX_GE_U16 : VOPC_Real_vi <0xbe>; 2618defm V_CMPX_T_U16 : VOPC_Real_vi <0xbf>; 2619 2620defm V_CMP_F_I32 : VOPC_Real_vi <0xc0>; 2621defm V_CMP_LT_I32 : VOPC_Real_vi <0xc1>; 2622defm V_CMP_EQ_I32 : VOPC_Real_vi <0xc2>; 2623defm V_CMP_LE_I32 : VOPC_Real_vi <0xc3>; 2624defm V_CMP_GT_I32 : VOPC_Real_vi <0xc4>; 2625defm V_CMP_NE_I32 : VOPC_Real_vi <0xc5>; 2626defm V_CMP_GE_I32 : VOPC_Real_vi <0xc6>; 2627defm V_CMP_T_I32 : VOPC_Real_vi <0xc7>; 2628 2629defm V_CMPX_F_I32 : VOPC_Real_vi <0xd0>; 2630defm V_CMPX_LT_I32 : VOPC_Real_vi <0xd1>; 2631defm V_CMPX_EQ_I32 : VOPC_Real_vi <0xd2>; 2632defm V_CMPX_LE_I32 : VOPC_Real_vi <0xd3>; 2633defm V_CMPX_GT_I32 : VOPC_Real_vi <0xd4>; 2634defm V_CMPX_NE_I32 : VOPC_Real_vi <0xd5>; 2635defm V_CMPX_GE_I32 : VOPC_Real_vi <0xd6>; 2636defm V_CMPX_T_I32 : VOPC_Real_vi <0xd7>; 2637 2638defm V_CMP_F_I64 : VOPC_Real_vi <0xe0>; 2639defm V_CMP_LT_I64 : VOPC_Real_vi <0xe1>; 2640defm V_CMP_EQ_I64 : VOPC_Real_vi <0xe2>; 2641defm V_CMP_LE_I64 : VOPC_Real_vi <0xe3>; 2642defm V_CMP_GT_I64 : VOPC_Real_vi <0xe4>; 2643defm V_CMP_NE_I64 : VOPC_Real_vi <0xe5>; 2644defm V_CMP_GE_I64 : VOPC_Real_vi <0xe6>; 2645defm V_CMP_T_I64 : VOPC_Real_vi <0xe7>; 2646 2647defm V_CMPX_F_I64 : VOPC_Real_vi <0xf0>; 2648defm V_CMPX_LT_I64 : VOPC_Real_vi <0xf1>; 2649defm V_CMPX_EQ_I64 : VOPC_Real_vi <0xf2>; 2650defm V_CMPX_LE_I64 : VOPC_Real_vi <0xf3>; 2651defm V_CMPX_GT_I64 : VOPC_Real_vi <0xf4>; 2652defm V_CMPX_NE_I64 : VOPC_Real_vi <0xf5>; 2653defm V_CMPX_GE_I64 : VOPC_Real_vi <0xf6>; 2654defm V_CMPX_T_I64 : VOPC_Real_vi <0xf7>; 2655 2656defm V_CMP_F_U32 : VOPC_Real_vi <0xc8>; 2657defm V_CMP_LT_U32 : VOPC_Real_vi <0xc9>; 2658defm V_CMP_EQ_U32 : VOPC_Real_vi <0xca>; 2659defm V_CMP_LE_U32 : VOPC_Real_vi <0xcb>; 2660defm V_CMP_GT_U32 : VOPC_Real_vi <0xcc>; 2661defm V_CMP_NE_U32 : VOPC_Real_vi <0xcd>; 2662defm V_CMP_GE_U32 : VOPC_Real_vi <0xce>; 2663defm V_CMP_T_U32 : VOPC_Real_vi <0xcf>; 2664 2665defm V_CMPX_F_U32 : VOPC_Real_vi <0xd8>; 2666defm V_CMPX_LT_U32 : VOPC_Real_vi <0xd9>; 2667defm V_CMPX_EQ_U32 : VOPC_Real_vi <0xda>; 2668defm V_CMPX_LE_U32 : VOPC_Real_vi <0xdb>; 2669defm V_CMPX_GT_U32 : VOPC_Real_vi <0xdc>; 2670defm V_CMPX_NE_U32 : VOPC_Real_vi <0xdd>; 2671defm V_CMPX_GE_U32 : VOPC_Real_vi <0xde>; 2672defm V_CMPX_T_U32 : VOPC_Real_vi <0xdf>; 2673 2674defm V_CMP_F_U64 : VOPC_Real_vi <0xe8>; 2675defm V_CMP_LT_U64 : VOPC_Real_vi <0xe9>; 2676defm V_CMP_EQ_U64 : VOPC_Real_vi <0xea>; 2677defm V_CMP_LE_U64 : VOPC_Real_vi <0xeb>; 2678defm V_CMP_GT_U64 : VOPC_Real_vi <0xec>; 2679defm V_CMP_NE_U64 : VOPC_Real_vi <0xed>; 2680defm V_CMP_GE_U64 : VOPC_Real_vi <0xee>; 2681defm V_CMP_T_U64 : VOPC_Real_vi <0xef>; 2682 2683defm V_CMPX_F_U64 : VOPC_Real_vi <0xf8>; 2684defm V_CMPX_LT_U64 : VOPC_Real_vi <0xf9>; 2685defm V_CMPX_EQ_U64 : VOPC_Real_vi <0xfa>; 2686defm V_CMPX_LE_U64 : VOPC_Real_vi <0xfb>; 2687defm V_CMPX_GT_U64 : VOPC_Real_vi <0xfc>; 2688defm V_CMPX_NE_U64 : VOPC_Real_vi <0xfd>; 2689defm V_CMPX_GE_U64 : VOPC_Real_vi <0xfe>; 2690defm V_CMPX_T_U64 : VOPC_Real_vi <0xff>; 2691