1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Basic SystemZ instruction definition 11//===----------------------------------------------------------------------===// 12 13class InstSystemZ<int size, dag outs, dag ins, string asmstr, 14 list<dag> pattern> : Instruction { 15 let Namespace = "SystemZ"; 16 17 dag OutOperandList = outs; 18 dag InOperandList = ins; 19 let Size = size; 20 let Pattern = pattern; 21 // Convert tabs to spaces, and remove space after comma for HLASM syntax 22 let AsmString = !subst("\t", "{\t| }", !subst(", ", "{, |,}", asmstr)); 23 24 let hasSideEffects = 0; 25 let mayLoad = 0; 26 let mayStore = 0; 27 28 // Some instructions come in pairs, one having a 12-bit displacement 29 // and the other having a 20-bit displacement. Both instructions in 30 // the pair have the same DispKey and their DispSizes are "12" and "20" 31 // respectively. 32 string DispKey = ""; 33 string DispSize = "none"; 34 35 // Many register-based <INSN>R instructions have a memory-based <INSN> 36 // counterpart. OpKey uniquely identifies <INSN>R, while OpType is 37 // "reg" for <INSN>R and "mem" for <INSN>. 38 string OpKey = ""; 39 string OpType = "none"; 40 41 // MemKey identifies a targe reg-mem opcode, while MemType can be either 42 // "pseudo" or "target". This is used to map a pseduo memory instruction to 43 // its corresponding target opcode. See comment at MemFoldPseudo. 44 string MemKey = ""; 45 string MemType = "none"; 46 47 // Many distinct-operands instructions have older 2-operand equivalents. 48 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs, 49 // with NumOpsValue being "2" or "3" as appropriate. 50 string NumOpsKey = ""; 51 string NumOpsValue = "none"; 52 53 // True if this instruction is a simple D(X,B) load of a register 54 // (with no sign or zero extension). 55 bit SimpleBDXLoad = 0; 56 57 // True if this instruction is a simple D(X,B) store of a register 58 // (with no truncation). 59 bit SimpleBDXStore = 0; 60 61 // True if this instruction has a 20-bit displacement field. 62 bit Has20BitOffset = 0; 63 64 // True if addresses in this instruction have an index register. 65 bit HasIndex = 0; 66 67 // True if this is a 128-bit pseudo instruction that combines two 64-bit 68 // operations. 69 bit Is128Bit = 0; 70 71 // The access size of all memory operands in bytes, or 0 if not known. 72 bits<5> AccessBytes = 0; 73 74 // If the instruction sets CC to a useful value, this gives the mask 75 // of all possible CC results. The mask has the same form as 76 // SystemZ::CCMASK_*. 77 bits<4> CCValues = 0; 78 79 // The subset of CCValues that have the same meaning as they would after a 80 // comparison of the first operand against zero. "Logical" instructions 81 // leave this blank as they set CC in a different way. 82 bits<4> CompareZeroCCMask = 0; 83 84 // True if the instruction is conditional and if the CC mask operand 85 // comes first (as for BRC, etc.). 86 bit CCMaskFirst = 0; 87 88 // Similar, but true if the CC mask operand comes last (as for LOC, etc.). 89 bit CCMaskLast = 0; 90 91 // True if the instruction is the "logical" rather than "arithmetic" form, 92 // in cases where a distinction exists. Except for logical compares, if the 93 // instruction sets this flag along with a non-zero CCValues field, it is 94 // assumed to set CC to either CCMASK_LOGICAL_ZERO or 95 // CCMASK_LOGICAL_NONZERO. 96 bit IsLogical = 0; 97 98 // True if the (add or sub) instruction sets CC like a compare of the 99 // result against zero, but only if the 'nsw' flag is set. 100 bit CCIfNoSignedWrap = 0; 101 102 let TSFlags{0} = SimpleBDXLoad; 103 let TSFlags{1} = SimpleBDXStore; 104 let TSFlags{2} = Has20BitOffset; 105 let TSFlags{3} = HasIndex; 106 let TSFlags{4} = Is128Bit; 107 let TSFlags{9-5} = AccessBytes; 108 let TSFlags{13-10} = CCValues; 109 let TSFlags{17-14} = CompareZeroCCMask; 110 let TSFlags{18} = CCMaskFirst; 111 let TSFlags{19} = CCMaskLast; 112 let TSFlags{20} = IsLogical; 113 let TSFlags{21} = CCIfNoSignedWrap; 114} 115 116//===----------------------------------------------------------------------===// 117// Mappings between instructions 118//===----------------------------------------------------------------------===// 119 120// Return the version of an instruction that has an unsigned 12-bit 121// displacement. 122def getDisp12Opcode : InstrMapping { 123 let FilterClass = "InstSystemZ"; 124 let RowFields = ["DispKey"]; 125 let ColFields = ["DispSize"]; 126 let KeyCol = ["20"]; 127 let ValueCols = [["12"]]; 128} 129 130// Return the version of an instruction that has a signed 20-bit displacement. 131def getDisp20Opcode : InstrMapping { 132 let FilterClass = "InstSystemZ"; 133 let RowFields = ["DispKey"]; 134 let ColFields = ["DispSize"]; 135 let KeyCol = ["12"]; 136 let ValueCols = [["20"]]; 137} 138 139// Return the memory form of a register instruction. Note that this may 140// return a MemFoldPseudo instruction (see below). 141def getMemOpcode : InstrMapping { 142 let FilterClass = "InstSystemZ"; 143 let RowFields = ["OpKey"]; 144 let ColFields = ["OpType"]; 145 let KeyCol = ["reg"]; 146 let ValueCols = [["mem"]]; 147} 148 149// Return the target memory instruction for a MemFoldPseudo. 150def getTargetMemOpcode : InstrMapping { 151 let FilterClass = "InstSystemZ"; 152 let RowFields = ["MemKey"]; 153 let ColFields = ["MemType"]; 154 let KeyCol = ["pseudo"]; 155 let ValueCols = [["target"]]; 156} 157 158// Return the 2-operand form of a 3-operand instruction. 159def getTwoOperandOpcode : InstrMapping { 160 let FilterClass = "InstSystemZ"; 161 let RowFields = ["NumOpsKey"]; 162 let ColFields = ["NumOpsValue"]; 163 let KeyCol = ["3"]; 164 let ValueCols = [["2"]]; 165} 166 167//===----------------------------------------------------------------------===// 168// Instruction formats 169//===----------------------------------------------------------------------===// 170// 171// Formats are specified using operand field declarations of the form: 172// 173// bits<4> Rn : register input or output for operand n 174// bits<5> Vn : vector register input or output for operand n 175// bits<m> In : immediate value of width m for operand n 176// bits<4> Bn : base register for address operand n 177// bits<m> Dn : displacement for address operand n 178// bits<5> Vn : vector index for address operand n 179// bits<4> Xn : index register for address operand n 180// bits<4> Mn : mode value for operand n 181// 182// The operand numbers ("n" in the list above) follow the architecture manual. 183// Assembly operands sometimes have a different order; in particular, R3 often 184// is often written between operands 1 and 2. 185// 186//===----------------------------------------------------------------------===// 187 188class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 189 : InstSystemZ<2, outs, ins, asmstr, pattern> { 190 field bits<16> Inst; 191 field bits<16> SoftFail = 0; 192 193 let Inst = op; 194} 195 196class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 197 : InstSystemZ<2, outs, ins, asmstr, pattern> { 198 field bits<16> Inst; 199 field bits<16> SoftFail = 0; 200 201 bits<8> I1; 202 203 let Inst{15-8} = op; 204 let Inst{7-0} = I1; 205} 206 207class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 208 : InstSystemZ<4, outs, ins, asmstr, pattern> { 209 field bits<32> Inst; 210 field bits<32> SoftFail = 0; 211 212 bits<4> I1; 213 bits<4> I2; 214 215 let Inst{31-16} = op; 216 let Inst{15-8} = 0; 217 let Inst{7-4} = I1; 218 let Inst{3-0} = I2; 219} 220 221class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 222 : InstSystemZ<6, outs, ins, asmstr, pattern> { 223 field bits<48> Inst; 224 field bits<48> SoftFail = 0; 225 226 bits<4> M1; 227 bits<12> RI2; 228 bits<24> RI3; 229 230 let Inst{47-40} = op; 231 let Inst{39-36} = M1; 232 let Inst{35-24} = RI2; 233 let Inst{23-0} = RI3; 234} 235 236class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 237 : InstSystemZ<4, outs, ins, asmstr, pattern> { 238 field bits<32> Inst; 239 field bits<32> SoftFail = 0; 240 241 bits<4> R1; 242 bits<16> I2; 243 244 let Inst{31-24} = op{11-4}; 245 let Inst{23-20} = R1; 246 let Inst{19-16} = op{3-0}; 247 let Inst{15-0} = I2; 248} 249 250class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 251 : InstSystemZ<4, outs, ins, asmstr, pattern> { 252 field bits<32> Inst; 253 field bits<32> SoftFail = 0; 254 255 bits<4> R1; 256 bits<16> RI2; 257 258 let Inst{31-24} = op{11-4}; 259 let Inst{23-20} = R1; 260 let Inst{19-16} = op{3-0}; 261 let Inst{15-0} = RI2; 262} 263 264class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 265 : InstSystemZ<4, outs, ins, asmstr, pattern> { 266 field bits<32> Inst; 267 field bits<32> SoftFail = 0; 268 269 bits<4> M1; 270 bits<16> RI2; 271 272 let Inst{31-24} = op{11-4}; 273 let Inst{23-20} = M1; 274 let Inst{19-16} = op{3-0}; 275 let Inst{15-0} = RI2; 276} 277 278class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 279 : InstSystemZ<6, outs, ins, asmstr, pattern> { 280 field bits<48> Inst; 281 field bits<48> SoftFail = 0; 282 283 bits<4> R1; 284 bits<16> I2; 285 bits<4> M3; 286 287 let Inst{47-40} = op{15-8}; 288 let Inst{39-36} = R1; 289 let Inst{35-32} = 0; 290 let Inst{31-16} = I2; 291 let Inst{15-12} = M3; 292 let Inst{11-8} = 0; 293 let Inst{7-0} = op{7-0}; 294} 295 296class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 297 : InstSystemZ<6, outs, ins, asmstr, pattern> { 298 field bits<48> Inst; 299 field bits<48> SoftFail = 0; 300 301 bits<4> R1; 302 bits<4> R2; 303 bits<4> M3; 304 bits<16> RI4; 305 306 let Inst{47-40} = op{15-8}; 307 let Inst{39-36} = R1; 308 let Inst{35-32} = R2; 309 let Inst{31-16} = RI4; 310 let Inst{15-12} = M3; 311 let Inst{11-8} = 0; 312 let Inst{7-0} = op{7-0}; 313} 314 315class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 316 : InstSystemZ<6, outs, ins, asmstr, pattern> { 317 field bits<48> Inst; 318 field bits<48> SoftFail = 0; 319 320 bits<4> R1; 321 bits<8> I2; 322 bits<4> M3; 323 bits<16> RI4; 324 325 let Inst{47-40} = op{15-8}; 326 let Inst{39-36} = R1; 327 let Inst{35-32} = M3; 328 let Inst{31-16} = RI4; 329 let Inst{15-8} = I2; 330 let Inst{7-0} = op{7-0}; 331} 332 333class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 334 : InstSystemZ<6, outs, ins, asmstr, pattern> { 335 field bits<48> Inst; 336 field bits<48> SoftFail = 0; 337 338 bits<4> R1; 339 bits<4> R3; 340 bits<16> I2; 341 342 let Inst{47-40} = op{15-8}; 343 let Inst{39-36} = R1; 344 let Inst{35-32} = R3; 345 let Inst{31-16} = I2; 346 let Inst{15-8} = 0; 347 let Inst{7-0} = op{7-0}; 348} 349 350class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 351 : InstSystemZ<6, outs, ins, asmstr, pattern> { 352 field bits<48> Inst; 353 field bits<48> SoftFail = 0; 354 355 bits<4> R1; 356 bits<4> R3; 357 bits<16> RI2; 358 359 let Inst{47-40} = op{15-8}; 360 let Inst{39-36} = R1; 361 let Inst{35-32} = R3; 362 let Inst{31-16} = RI2; 363 let Inst{15-8} = 0; 364 let Inst{7-0} = op{7-0}; 365} 366 367class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 368 bits<8> I3Or = 0, bits<8> I4Or = 0> 369 : InstSystemZ<6, outs, ins, asmstr, pattern> { 370 field bits<48> Inst; 371 field bits<48> SoftFail = 0; 372 373 bits<4> R1; 374 bits<4> R2; 375 bits<8> I3; 376 bits<8> I4; 377 bits<8> I5; 378 379 let Inst{47-40} = op{15-8}; 380 let Inst{39-36} = R1; 381 let Inst{35-32} = R2; 382 let Inst{31} = !if(I3Or{7}, 1, I3{7}); 383 let Inst{30} = !if(I3Or{6}, 1, I3{6}); 384 let Inst{29} = !if(I3Or{5}, 1, I3{5}); 385 let Inst{28} = !if(I3Or{4}, 1, I3{4}); 386 let Inst{27} = !if(I3Or{3}, 1, I3{3}); 387 let Inst{26} = !if(I3Or{2}, 1, I3{2}); 388 let Inst{25} = !if(I3Or{1}, 1, I3{1}); 389 let Inst{24} = !if(I3Or{0}, 1, I3{0}); 390 let Inst{23} = !if(I4Or{7}, 1, I4{7}); 391 let Inst{22} = !if(I4Or{6}, 1, I4{6}); 392 let Inst{21} = !if(I4Or{5}, 1, I4{5}); 393 let Inst{20} = !if(I4Or{4}, 1, I4{4}); 394 let Inst{19} = !if(I4Or{3}, 1, I4{3}); 395 let Inst{18} = !if(I4Or{2}, 1, I4{2}); 396 let Inst{17} = !if(I4Or{1}, 1, I4{1}); 397 let Inst{16} = !if(I4Or{0}, 1, I4{0}); 398 let Inst{15-8} = I5; 399 let Inst{7-0} = op{7-0}; 400} 401 402class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 403 : InstSystemZ<6, outs, ins, asmstr, pattern> { 404 field bits<48> Inst; 405 field bits<48> SoftFail = 0; 406 407 bits<4> R1; 408 bits<4> M3; 409 bits<16> I2; 410 411 let Inst{47-40} = op{15-8}; 412 let Inst{39-36} = R1; 413 let Inst{35-32} = M3; 414 let Inst{31-16} = I2; 415 let Inst{15-8} = 0; 416 let Inst{7-0} = op{7-0}; 417} 418 419class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 420 : InstSystemZ<6, outs, ins, asmstr, pattern> { 421 field bits<48> Inst; 422 field bits<48> SoftFail = 0; 423 424 bits<4> R1; 425 bits<32> I2; 426 427 let Inst{47-40} = op{11-4}; 428 let Inst{39-36} = R1; 429 let Inst{35-32} = op{3-0}; 430 let Inst{31-0} = I2; 431} 432 433class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 434 : InstSystemZ<6, outs, ins, asmstr, pattern> { 435 field bits<48> Inst; 436 field bits<48> SoftFail = 0; 437 438 bits<4> R1; 439 bits<32> RI2; 440 441 let Inst{47-40} = op{11-4}; 442 let Inst{39-36} = R1; 443 let Inst{35-32} = op{3-0}; 444 let Inst{31-0} = RI2; 445} 446 447class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 448 : InstSystemZ<6, outs, ins, asmstr, pattern> { 449 field bits<48> Inst; 450 field bits<48> SoftFail = 0; 451 452 bits<4> M1; 453 bits<32> RI2; 454 455 let Inst{47-40} = op{11-4}; 456 let Inst{39-36} = M1; 457 let Inst{35-32} = op{3-0}; 458 let Inst{31-0} = RI2; 459} 460 461class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 462 : InstSystemZ<6, outs, ins, asmstr, pattern> { 463 field bits<48> Inst; 464 field bits<48> SoftFail = 0; 465 466 bits<4> R1; 467 bits<8> I2; 468 bits<4> M3; 469 bits<4> B4; 470 bits<12> D4; 471 472 let Inst{47-40} = op{15-8}; 473 let Inst{39-36} = R1; 474 let Inst{35-32} = M3; 475 let Inst{31-28} = B4; 476 let Inst{27-16} = D4; 477 let Inst{15-8} = I2; 478 let Inst{7-0} = op{7-0}; 479} 480 481class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 482 : InstSystemZ<2, outs, ins, asmstr, pattern> { 483 field bits<16> Inst; 484 field bits<16> SoftFail = 0; 485 486 bits<4> R1; 487 bits<4> R2; 488 489 let Inst{15-8} = op; 490 let Inst{7-4} = R1; 491 let Inst{3-0} = R2; 492} 493 494class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 495 : InstSystemZ<4, outs, ins, asmstr, pattern> { 496 field bits<32> Inst; 497 field bits<32> SoftFail = 0; 498 499 bits<4> R1; 500 bits<4> R3; 501 bits<4> R2; 502 503 let Inst{31-16} = op; 504 let Inst{15-12} = R1; 505 let Inst{11-8} = 0; 506 let Inst{7-4} = R3; 507 let Inst{3-0} = R2; 508} 509 510class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 511 : InstSystemZ<4, outs, ins, asmstr, pattern> { 512 field bits<32> Inst; 513 field bits<32> SoftFail = 0; 514 515 bits<4> R1; 516 bits<4> R2; 517 518 let Inst{31-16} = op; 519 let Inst{15-8} = 0; 520 let Inst{7-4} = R1; 521 let Inst{3-0} = R2; 522} 523 524class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 525 : InstSystemZ<4, outs, ins, asmstr, pattern> { 526 field bits<32> Inst; 527 field bits<32> SoftFail = 0; 528 529 bits<4> R1; 530 bits<4> R2; 531 bits<4> R3; 532 bits<4> M4; 533 534 let Inst{31-16} = op; 535 let Inst{15-12} = R3; 536 let Inst{11-8} = M4; 537 let Inst{7-4} = R1; 538 let Inst{3-0} = R2; 539} 540 541class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 542 : InstSystemZ<4, outs, ins, asmstr, pattern> { 543 field bits<32> Inst; 544 field bits<32> SoftFail = 0; 545 546 bits<4> R1; 547 bits<4> R2; 548 bits<4> R3; 549 bits<4> M4; 550 551 let Inst{31-16} = op; 552 let Inst{15-12} = R3; 553 let Inst{11-8} = M4; 554 let Inst{7-4} = R1; 555 let Inst{3-0} = R2; 556} 557 558class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 559 : InstSystemZ<4, outs, ins, asmstr, pattern> { 560 field bits<32> Inst; 561 field bits<32> SoftFail = 0; 562 563 bits<4> R1; 564 bits<4> R2; 565 bits<4> M3; 566 567 let Inst{31-16} = op; 568 let Inst{15-12} = M3; 569 let Inst{11-8} = 0; 570 let Inst{7-4} = R1; 571 let Inst{3-0} = R2; 572} 573 574class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 575 : InstSystemZ<4, outs, ins, asmstr, pattern> { 576 field bits<32> Inst; 577 field bits<32> SoftFail = 0; 578 579 bits<4> R1; 580 bits<4> R2; 581 bits<4> M4; 582 583 let Inst{31-16} = op; 584 let Inst{15-12} = 0; 585 let Inst{11-8} = M4; 586 let Inst{7-4} = R1; 587 let Inst{3-0} = R2; 588} 589 590class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 591 : InstSystemZ<4, outs, ins, asmstr, pattern> { 592 field bits<32> Inst; 593 field bits<32> SoftFail = 0; 594 595 bits<4> R1; 596 bits<4> R2; 597 bits<4> M3; 598 bits<4> M4; 599 600 let Inst{31-16} = op; 601 let Inst{15-12} = M3; 602 let Inst{11-8} = M4; 603 let Inst{7-4} = R1; 604 let Inst{3-0} = R2; 605} 606 607class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 608 : InstSystemZ<6, outs, ins, asmstr, pattern> { 609 field bits<48> Inst; 610 field bits<48> SoftFail = 0; 611 612 bits<4> R1; 613 bits<4> R2; 614 bits<4> M3; 615 bits<4> B4; 616 bits<12> D4; 617 618 let Inst{47-40} = op{15-8}; 619 let Inst{39-36} = R1; 620 let Inst{35-32} = R2; 621 let Inst{31-28} = B4; 622 let Inst{27-16} = D4; 623 let Inst{15-12} = M3; 624 let Inst{11-8} = 0; 625 let Inst{7-0} = op{7-0}; 626} 627 628class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 629 : InstSystemZ<4, outs, ins, asmstr, pattern> { 630 field bits<32> Inst; 631 field bits<32> SoftFail = 0; 632 633 bits<4> R1; 634 bits<4> X2; 635 bits<4> B2; 636 bits<12> D2; 637 638 let Inst{31-24} = op; 639 let Inst{23-20} = R1; 640 let Inst{19-16} = X2; 641 let Inst{15-12} = B2; 642 let Inst{11-0} = D2; 643 644 let HasIndex = 1; 645} 646 647class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 648 : InstSystemZ<4, outs, ins, asmstr, pattern> { 649 field bits<32> Inst; 650 field bits<32> SoftFail = 0; 651 652 bits<4> M1; 653 bits<4> X2; 654 bits<4> B2; 655 bits<12> D2; 656 657 let Inst{31-24} = op; 658 let Inst{23-20} = M1; 659 let Inst{19-16} = X2; 660 let Inst{15-12} = B2; 661 let Inst{11-0} = D2; 662 663 let HasIndex = 1; 664} 665 666class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 667 : InstSystemZ<6, outs, ins, asmstr, pattern> { 668 field bits<48> Inst; 669 field bits<48> SoftFail = 0; 670 671 bits<4> R1; 672 bits<4> X2; 673 bits<4> B2; 674 bits<12> D2; 675 bits<4> M3; 676 677 let Inst{47-40} = op{15-8}; 678 let Inst{39-36} = R1; 679 let Inst{35-32} = X2; 680 let Inst{31-28} = B2; 681 let Inst{27-16} = D2; 682 let Inst{15-12} = M3; 683 let Inst{11-8} = 0; 684 let Inst{7-0} = op{7-0}; 685 686 let HasIndex = 1; 687} 688 689class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 690 : InstSystemZ<6, outs, ins, asmstr, pattern> { 691 field bits<48> Inst; 692 field bits<48> SoftFail = 0; 693 694 bits<4> R1; 695 bits<4> R3; 696 bits<4> X2; 697 bits<4> B2; 698 bits<12> D2; 699 700 let Inst{47-40} = op{15-8}; 701 let Inst{39-36} = R3; 702 let Inst{35-32} = X2; 703 let Inst{31-28} = B2; 704 let Inst{27-16} = D2; 705 let Inst{15-12} = R1; 706 let Inst{11-8} = 0; 707 let Inst{7-0} = op{7-0}; 708 709 let HasIndex = 1; 710} 711 712class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 713 : InstSystemZ<6, outs, ins, asmstr, pattern> { 714 field bits<48> Inst; 715 field bits<48> SoftFail = 0; 716 717 bits<4> R1; 718 bits<4> X2; 719 bits<4> B2; 720 bits<20> D2; 721 722 let Inst{47-40} = op{15-8}; 723 let Inst{39-36} = R1; 724 let Inst{35-32} = X2; 725 let Inst{31-28} = B2; 726 let Inst{27-16} = D2{11-0}; 727 let Inst{15-8} = D2{19-12}; 728 let Inst{7-0} = op{7-0}; 729 730 let Has20BitOffset = 1; 731 let HasIndex = 1; 732} 733 734class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 735 : InstSystemZ<6, outs, ins, asmstr, pattern> { 736 field bits<48> Inst; 737 field bits<48> SoftFail = 0; 738 739 bits<4> M1; 740 bits<4> X2; 741 bits<4> B2; 742 bits<20> D2; 743 744 let Inst{47-40} = op{15-8}; 745 let Inst{39-36} = M1; 746 let Inst{35-32} = X2; 747 let Inst{31-28} = B2; 748 let Inst{27-16} = D2{11-0}; 749 let Inst{15-8} = D2{19-12}; 750 let Inst{7-0} = op{7-0}; 751 752 let Has20BitOffset = 1; 753 let HasIndex = 1; 754} 755 756class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 757 : InstSystemZ<4, outs, ins, asmstr, pattern> { 758 field bits<32> Inst; 759 field bits<32> SoftFail = 0; 760 761 bits<4> R1; 762 bits<4> R3; 763 bits<4> B2; 764 bits<12> D2; 765 766 let Inst{31-24} = op; 767 let Inst{23-20} = R1; 768 let Inst{19-16} = R3; 769 let Inst{15-12} = B2; 770 let Inst{11-0} = D2; 771} 772 773class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 774 : InstSystemZ<4, outs, ins, asmstr, pattern> { 775 field bits<32> Inst; 776 field bits<32> SoftFail = 0; 777 778 bits<4> R1; 779 bits<4> M3; 780 bits<4> B2; 781 bits<12> D2; 782 783 let Inst{31-24} = op; 784 let Inst{23-20} = R1; 785 let Inst{19-16} = M3; 786 let Inst{15-12} = B2; 787 let Inst{11-0} = D2; 788} 789 790class InstRSEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 791 : InstSystemZ<6, outs, ins, asmstr, pattern> { 792 field bits<48> Inst; 793 field bits<48> SoftFail = 0; 794 795 bits<4> R1; 796 bits<4> R3; 797 bits<4> B2; 798 bits<12> D2; 799 800 let Inst{47-40} = op{15-8}; 801 let Inst{39-36} = R1; 802 let Inst{35-32} = R3; 803 let Inst{31-28} = B2; 804 let Inst{27-16} = D2; 805 let Inst{15-8} = 0; 806 let Inst{7-0} = op{7-0}; 807} 808 809class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 810 : InstSystemZ<4, outs, ins, asmstr, pattern> { 811 field bits<32> Inst; 812 field bits<32> SoftFail = 0; 813 814 bits<4> R1; 815 bits<4> R3; 816 bits<16> RI2; 817 818 let Inst{31-24} = op; 819 let Inst{23-20} = R1; 820 let Inst{19-16} = R3; 821 let Inst{15-0} = RI2; 822} 823 824class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 825 : InstSystemZ<6, outs, ins, asmstr, pattern> { 826 field bits<48> Inst; 827 field bits<48> SoftFail = 0; 828 829 bits<4> B1; 830 bits<12> D1; 831 bits<4> L1; 832 833 let Inst{47-40} = op{15-8}; 834 let Inst{39-36} = L1; 835 let Inst{35-32} = 0; 836 let Inst{31-28} = B1; 837 let Inst{27-16} = D1; 838 let Inst{15-8} = 0; 839 let Inst{7-0} = op{7-0}; 840} 841 842class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 843 : InstSystemZ<6, outs, ins, asmstr, pattern> { 844 field bits<48> Inst; 845 field bits<48> SoftFail = 0; 846 847 bits<4> R1; 848 bits<4> B2; 849 bits<12> D2; 850 bits<8> L2; 851 bits<4> M3; 852 853 let Inst{47-40} = op{15-8}; 854 let Inst{39-32} = L2; 855 let Inst{31-28} = B2; 856 let Inst{27-16} = D2; 857 let Inst{15-12} = R1; 858 let Inst{11-8} = M3; 859 let Inst{7-0} = op{7-0}; 860} 861 862class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 863 : InstSystemZ<6, outs, ins, asmstr, pattern> { 864 field bits<48> Inst; 865 field bits<48> SoftFail = 0; 866 867 bits<4> R1; 868 bits<4> R3; 869 bits<4> B2; 870 bits<20> D2; 871 872 let Inst{47-40} = op{15-8}; 873 let Inst{39-36} = R1; 874 let Inst{35-32} = R3; 875 let Inst{31-28} = B2; 876 let Inst{27-16} = D2{11-0}; 877 let Inst{15-8} = D2{19-12}; 878 let Inst{7-0} = op{7-0}; 879 880 let Has20BitOffset = 1; 881} 882 883class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 884 : InstSystemZ<6, outs, ins, asmstr, pattern> { 885 field bits<48> Inst; 886 field bits<48> SoftFail = 0; 887 888 bits<4> R1; 889 bits<4> M3; 890 bits<4> B2; 891 bits<20> D2; 892 893 let Inst{47-40} = op{15-8}; 894 let Inst{39-36} = R1; 895 let Inst{35-32} = M3; 896 let Inst{31-28} = B2; 897 let Inst{27-16} = D2{11-0}; 898 let Inst{15-8} = D2{19-12}; 899 let Inst{7-0} = op{7-0}; 900 901 let Has20BitOffset = 1; 902} 903 904class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 905 : InstSystemZ<4, outs, ins, asmstr, pattern> { 906 field bits<32> Inst; 907 field bits<32> SoftFail = 0; 908 909 bits<4> B1; 910 bits<12> D1; 911 bits<8> I2; 912 913 let Inst{31-24} = op; 914 let Inst{23-16} = I2; 915 let Inst{15-12} = B1; 916 let Inst{11-0} = D1; 917} 918 919class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 920 : InstSystemZ<6, outs, ins, asmstr, pattern> { 921 field bits<48> Inst; 922 field bits<48> SoftFail = 0; 923 924 bits<4> B1; 925 bits<12> D1; 926 bits<16> I2; 927 928 let Inst{47-32} = op; 929 let Inst{31-28} = B1; 930 let Inst{27-16} = D1; 931 let Inst{15-0} = I2; 932} 933 934class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 935 : InstSystemZ<6, outs, ins, asmstr, pattern> { 936 field bits<48> Inst; 937 field bits<48> SoftFail = 0; 938 939 bits<4> B1; 940 bits<20> D1; 941 bits<8> I2; 942 943 let Inst{47-40} = op{15-8}; 944 let Inst{39-32} = I2; 945 let Inst{31-28} = B1; 946 let Inst{27-16} = D1{11-0}; 947 let Inst{15-8} = D1{19-12}; 948 let Inst{7-0} = op{7-0}; 949 950 let Has20BitOffset = 1; 951} 952 953class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 954 : InstSystemZ<6, outs, ins, asmstr, pattern> { 955 field bits<48> Inst; 956 field bits<48> SoftFail = 0; 957 958 bits<4> M1; 959 bits<16> RI2; 960 bits<4> B3; 961 bits<12> D3; 962 963 let Inst{47-40} = op; 964 let Inst{39-36} = M1; 965 let Inst{35-32} = 0; 966 let Inst{31-28} = B3; 967 let Inst{27-16} = D3; 968 let Inst{15-0} = RI2; 969} 970 971class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 972 : InstSystemZ<6, outs, ins, asmstr, pattern> { 973 field bits<48> Inst; 974 field bits<48> SoftFail = 0; 975 976 bits<4> B1; 977 bits<12> D1; 978 bits<8> L1; 979 bits<4> B2; 980 bits<12> D2; 981 982 let Inst{47-40} = op; 983 let Inst{39-32} = L1; 984 let Inst{31-28} = B1; 985 let Inst{27-16} = D1; 986 let Inst{15-12} = B2; 987 let Inst{11-0} = D2; 988} 989 990class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 991 : InstSystemZ<6, outs, ins, asmstr, pattern> { 992 field bits<48> Inst; 993 field bits<48> SoftFail = 0; 994 995 bits<4> B1; 996 bits<12> D1; 997 bits<4> L1; 998 bits<4> B2; 999 bits<12> D2; 1000 bits<4> L2; 1001 1002 let Inst{47-40} = op; 1003 let Inst{39-36} = L1; 1004 let Inst{35-32} = L2; 1005 let Inst{31-28} = B1; 1006 let Inst{27-16} = D1; 1007 let Inst{15-12} = B2; 1008 let Inst{11-0} = D2; 1009} 1010 1011class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1012 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1013 field bits<48> Inst; 1014 field bits<48> SoftFail = 0; 1015 1016 bits<4> B1; 1017 bits<12> D1; 1018 bits<4> L1; 1019 bits<4> B2; 1020 bits<12> D2; 1021 bits<4> I3; 1022 1023 let Inst{47-40} = op; 1024 let Inst{39-36} = L1; 1025 let Inst{35-32} = I3; 1026 let Inst{31-28} = B1; 1027 let Inst{27-16} = D1; 1028 let Inst{15-12} = B2; 1029 let Inst{11-0} = D2; 1030} 1031 1032class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1033 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1034 field bits<48> Inst; 1035 field bits<48> SoftFail = 0; 1036 1037 bits<4> R1; 1038 bits<4> B1; 1039 bits<12> D1; 1040 bits<4> B2; 1041 bits<12> D2; 1042 bits<4> R3; 1043 1044 let Inst{47-40} = op; 1045 let Inst{39-36} = R1; 1046 let Inst{35-32} = R3; 1047 let Inst{31-28} = B1; 1048 let Inst{27-16} = D1; 1049 let Inst{15-12} = B2; 1050 let Inst{11-0} = D2; 1051} 1052 1053class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1054 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1055 field bits<48> Inst; 1056 field bits<48> SoftFail = 0; 1057 1058 bits<4> R1; 1059 bits<4> B2; 1060 bits<12> D2; 1061 bits<4> R3; 1062 bits<4> B4; 1063 bits<12> D4; 1064 1065 let Inst{47-40} = op; 1066 let Inst{39-36} = R1; 1067 let Inst{35-32} = R3; 1068 let Inst{31-28} = B2; 1069 let Inst{27-16} = D2; 1070 let Inst{15-12} = B4; 1071 let Inst{11-0} = D4; 1072} 1073 1074class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1075 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1076 field bits<48> Inst; 1077 field bits<48> SoftFail = 0; 1078 1079 bits<4> B1; 1080 bits<12> D1; 1081 bits<4> B2; 1082 bits<12> D2; 1083 bits<8> L2; 1084 1085 let Inst{47-40} = op; 1086 let Inst{39-32} = L2; 1087 let Inst{31-28} = B1; 1088 let Inst{27-16} = D1; 1089 let Inst{15-12} = B2; 1090 let Inst{11-0} = D2; 1091} 1092 1093class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1094 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1095 field bits<48> Inst; 1096 field bits<48> SoftFail = 0; 1097 1098 bits<4> B1; 1099 bits<12> D1; 1100 bits<4> B2; 1101 bits<12> D2; 1102 1103 let Inst{47-32} = op; 1104 let Inst{31-28} = B1; 1105 let Inst{27-16} = D1; 1106 let Inst{15-12} = B2; 1107 let Inst{11-0} = D2; 1108} 1109 1110class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1111 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1112 field bits<48> Inst; 1113 field bits<48> SoftFail = 0; 1114 1115 bits<4> B1; 1116 bits<12> D1; 1117 bits<4> B2; 1118 bits<12> D2; 1119 bits<4> R3; 1120 1121 let Inst{47-40} = op{11-4}; 1122 let Inst{39-36} = R3; 1123 let Inst{35-32} = op{3-0}; 1124 let Inst{31-28} = B1; 1125 let Inst{27-16} = D1; 1126 let Inst{15-12} = B2; 1127 let Inst{11-0} = D2; 1128} 1129 1130class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1131 : InstSystemZ<4, outs, ins, asmstr, pattern> { 1132 field bits<32> Inst; 1133 field bits<32> SoftFail = 0; 1134 1135 bits<4> B2; 1136 bits<12> D2; 1137 1138 let Inst{31-16} = op; 1139 let Inst{15-12} = B2; 1140 let Inst{11-0} = D2; 1141} 1142 1143class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1144 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1145 field bits<48> Inst; 1146 field bits<48> SoftFail = 0; 1147 1148 bits<5> V1; 1149 bits<16> I2; 1150 bits<4> M3; 1151 1152 let Inst{47-40} = op{15-8}; 1153 let Inst{39-36} = V1{3-0}; 1154 let Inst{35-32} = 0; 1155 let Inst{31-16} = I2; 1156 let Inst{15-12} = M3; 1157 let Inst{11} = V1{4}; 1158 let Inst{10-8} = 0; 1159 let Inst{7-0} = op{7-0}; 1160} 1161 1162class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1163 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1164 field bits<48> Inst; 1165 field bits<48> SoftFail = 0; 1166 1167 bits<5> V1; 1168 bits<8> I2; 1169 bits<8> I3; 1170 bits<4> M4; 1171 1172 let Inst{47-40} = op{15-8}; 1173 let Inst{39-36} = V1{3-0}; 1174 let Inst{35-32} = 0; 1175 let Inst{31-24} = I2; 1176 let Inst{23-16} = I3; 1177 let Inst{15-12} = M4; 1178 let Inst{11} = V1{4}; 1179 let Inst{10-8} = 0; 1180 let Inst{7-0} = op{7-0}; 1181} 1182 1183class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1184 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1185 field bits<48> Inst; 1186 field bits<48> SoftFail = 0; 1187 1188 bits<5> V1; 1189 bits<5> V3; 1190 bits<16> I2; 1191 bits<4> M4; 1192 1193 let Inst{47-40} = op{15-8}; 1194 let Inst{39-36} = V1{3-0}; 1195 let Inst{35-32} = V3{3-0}; 1196 let Inst{31-16} = I2; 1197 let Inst{15-12} = M4; 1198 let Inst{11} = V1{4}; 1199 let Inst{10} = V3{4}; 1200 let Inst{9-8} = 0; 1201 let Inst{7-0} = op{7-0}; 1202} 1203 1204class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1205 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1206 field bits<48> Inst; 1207 field bits<48> SoftFail = 0; 1208 1209 bits<5> V1; 1210 bits<5> V2; 1211 bits<5> V3; 1212 bits<8> I4; 1213 bits<4> M5; 1214 1215 let Inst{47-40} = op{15-8}; 1216 let Inst{39-36} = V1{3-0}; 1217 let Inst{35-32} = V2{3-0}; 1218 let Inst{31-28} = V3{3-0}; 1219 let Inst{27-24} = 0; 1220 let Inst{23-16} = I4; 1221 let Inst{15-12} = M5; 1222 let Inst{11} = V1{4}; 1223 let Inst{10} = V2{4}; 1224 let Inst{9} = V3{4}; 1225 let Inst{8} = 0; 1226 let Inst{7-0} = op{7-0}; 1227} 1228 1229class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1230 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1231 field bits<48> Inst; 1232 field bits<48> SoftFail = 0; 1233 1234 bits<5> V1; 1235 bits<5> V2; 1236 bits<12> I3; 1237 bits<4> M4; 1238 bits<4> M5; 1239 1240 let Inst{47-40} = op{15-8}; 1241 let Inst{39-36} = V1{3-0}; 1242 let Inst{35-32} = V2{3-0}; 1243 let Inst{31-20} = I3; 1244 let Inst{19-16} = M5; 1245 let Inst{15-12} = M4; 1246 let Inst{11} = V1{4}; 1247 let Inst{10} = V2{4}; 1248 let Inst{9-8} = 0; 1249 let Inst{7-0} = op{7-0}; 1250} 1251 1252class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1253 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1254 field bits<48> Inst; 1255 field bits<48> SoftFail = 0; 1256 1257 bits<5> V1; 1258 bits<5> V2; 1259 bits<5> V3; 1260 bits<8> I4; 1261 bits<4> M5; 1262 1263 let Inst{47-40} = op{15-8}; 1264 let Inst{39-36} = V1{3-0}; 1265 let Inst{35-32} = V2{3-0}; 1266 let Inst{31-28} = V3{3-0}; 1267 let Inst{27-24} = 0; 1268 let Inst{23-20} = M5; 1269 let Inst{19-12} = I4; 1270 let Inst{11} = V1{4}; 1271 let Inst{10} = V2{4}; 1272 let Inst{9} = V3{4}; 1273 let Inst{8} = 0; 1274 let Inst{7-0} = op{7-0}; 1275} 1276 1277class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1278 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1279 field bits<48> Inst; 1280 field bits<48> SoftFail = 0; 1281 1282 bits<5> V1; 1283 bits<5> V2; 1284 bits<8> I3; 1285 bits<8> I4; 1286 bits<4> M5; 1287 1288 let Inst{47-40} = op{15-8}; 1289 let Inst{39-36} = V1{3-0}; 1290 let Inst{35-32} = V2{3-0}; 1291 let Inst{31-24} = I4; 1292 let Inst{23-20} = M5; 1293 let Inst{19-12} = I3; 1294 let Inst{11} = V1{4}; 1295 let Inst{10} = V2{4}; 1296 let Inst{9-8} = 0; 1297 let Inst{7-0} = op{7-0}; 1298} 1299 1300class InstVRIh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1301 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1302 field bits<48> Inst; 1303 field bits<48> SoftFail = 0; 1304 1305 bits<5> V1; 1306 bits<16> I2; 1307 bits<4> I3; 1308 1309 let Inst{47-40} = op{15-8}; 1310 let Inst{39-36} = V1{3-0}; 1311 let Inst{35-32} = 0; 1312 let Inst{31-16} = I2; 1313 let Inst{15-12} = I3; 1314 let Inst{11} = V1{4}; 1315 let Inst{10-8} = 0; 1316 let Inst{7-0} = op{7-0}; 1317} 1318 1319class InstVRIi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1320 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1321 field bits<48> Inst; 1322 field bits<48> SoftFail = 0; 1323 1324 bits<5> V1; 1325 bits<4> R2; 1326 bits<8> I3; 1327 bits<4> M4; 1328 1329 let Inst{47-40} = op{15-8}; 1330 let Inst{39-36} = V1{3-0}; 1331 let Inst{35-32} = R2; 1332 let Inst{31-24} = 0; 1333 let Inst{23-20} = M4; 1334 let Inst{19-12} = I3; 1335 let Inst{11} = V1{4}; 1336 let Inst{10-8} = 0; 1337 let Inst{7-0} = op{7-0}; 1338} 1339 1340class InstVRIj<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1341 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1342 field bits<48> Inst; 1343 field bits<48> SoftFail = 0; 1344 1345 bits<5> V1; 1346 bits<5> V2; 1347 bits<8> I3; 1348 bits<4> M4; 1349 1350 let Inst{47-40} = op{15-8}; 1351 let Inst{39-36} = V1{3-0}; 1352 let Inst{35-32} = V2{3-0}; 1353 let Inst{31-24} = 0; 1354 let Inst{23-20} = M4; 1355 let Inst{19-12} = I3; 1356 let Inst{11} = V1{4}; 1357 let Inst{10} = V2{4}; 1358 let Inst{9-8} = 0; 1359 let Inst{7-0} = op{7-0}; 1360} 1361 1362class InstVRIk<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1363 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1364 field bits<48> Inst; 1365 field bits<48> SoftFail = 0; 1366 1367 bits<5> V1; 1368 bits<5> V2; 1369 bits<5> V3; 1370 bits<5> V4; 1371 bits<8> I5; 1372 1373 let Inst{47-40} = op{15-8}; 1374 let Inst{39-36} = V1{3-0}; 1375 let Inst{35-32} = V2{3-0}; 1376 let Inst{31-28} = V3{3-0}; 1377 let Inst{27-24} = 0; 1378 let Inst{23-16} = I5; 1379 let Inst{15-12} = V4{3-0}; 1380 let Inst{11} = V1{4}; 1381 let Inst{10} = V2{4}; 1382 let Inst{9} = V3{4}; 1383 let Inst{8} = V4{4}; 1384 let Inst{7-0} = op{7-0}; 1385} 1386 1387class InstVRIl<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1388 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1389 field bits<48> Inst; 1390 field bits<48> SoftFail = 0; 1391 1392 bits<5> V1; 1393 bits<5> V2; 1394 bits<16> I3; 1395 1396 let Inst{47-40} = op{15-8}; 1397 let Inst{39-36} = 0; 1398 let Inst{35-32} = V1{3-0}; 1399 let Inst{31-28} = V2{3-0}; 1400 let Inst{27-12} = I3; 1401 let Inst{11} = 0; 1402 let Inst{10} = V1{4}; 1403 let Inst{9} = V2{4}; 1404 let Inst{8} = 0; 1405 let Inst{7-0} = op{7-0}; 1406} 1407 1408// Depending on the instruction mnemonic, certain bits may be or-ed into 1409// the M4 value provided as explicit operand. These are passed as m4or. 1410class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 1411 bits<4> m4or = 0> 1412 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1413 field bits<48> Inst; 1414 field bits<48> SoftFail = 0; 1415 1416 bits<5> V1; 1417 bits<5> V2; 1418 bits<4> M3; 1419 bits<4> M4; 1420 bits<4> M5; 1421 1422 let Inst{47-40} = op{15-8}; 1423 let Inst{39-36} = V1{3-0}; 1424 let Inst{35-32} = V2{3-0}; 1425 let Inst{31-24} = 0; 1426 let Inst{23-20} = M5; 1427 let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3}); 1428 let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2}); 1429 let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1}); 1430 let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0}); 1431 let Inst{15-12} = M3; 1432 let Inst{11} = V1{4}; 1433 let Inst{10} = V2{4}; 1434 let Inst{9-8} = 0; 1435 let Inst{7-0} = op{7-0}; 1436} 1437 1438// Depending on the instruction mnemonic, certain bits may be or-ed into 1439// the M5 value provided as explicit operand. These are passed as m5or. 1440class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 1441 bits<4> m5or = 0> 1442 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1443 field bits<48> Inst; 1444 field bits<48> SoftFail = 0; 1445 1446 bits<5> V1; 1447 bits<5> V2; 1448 bits<5> V3; 1449 bits<4> M4; 1450 bits<4> M5; 1451 1452 let Inst{47-40} = op{15-8}; 1453 let Inst{39-36} = V1{3-0}; 1454 let Inst{35-32} = V2{3-0}; 1455 let Inst{31-28} = V3{3-0}; 1456 let Inst{27-24} = 0; 1457 let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3}); 1458 let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2}); 1459 let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1}); 1460 let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0}); 1461 let Inst{19-16} = 0; 1462 let Inst{15-12} = M4; 1463 let Inst{11} = V1{4}; 1464 let Inst{10} = V2{4}; 1465 let Inst{9} = V3{4}; 1466 let Inst{8} = 0; 1467 let Inst{7-0} = op{7-0}; 1468} 1469 1470class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1471 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1472 field bits<48> Inst; 1473 field bits<48> SoftFail = 0; 1474 1475 bits<5> V1; 1476 bits<5> V2; 1477 bits<5> V3; 1478 bits<4> M4; 1479 bits<4> M5; 1480 bits<4> M6; 1481 1482 let Inst{47-40} = op{15-8}; 1483 let Inst{39-36} = V1{3-0}; 1484 let Inst{35-32} = V2{3-0}; 1485 let Inst{31-28} = V3{3-0}; 1486 let Inst{27-24} = 0; 1487 let Inst{23-20} = M6; 1488 let Inst{19-16} = M5; 1489 let Inst{15-12} = M4; 1490 let Inst{11} = V1{4}; 1491 let Inst{10} = V2{4}; 1492 let Inst{9} = V3{4}; 1493 let Inst{8} = 0; 1494 let Inst{7-0} = op{7-0}; 1495} 1496 1497// Depending on the instruction mnemonic, certain bits may be or-ed into 1498// the M6 value provided as explicit operand. These are passed as m6or. 1499class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 1500 bits<4> m6or = 0> 1501 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1502 field bits<48> Inst; 1503 field bits<48> SoftFail = 0; 1504 1505 bits<5> V1; 1506 bits<5> V2; 1507 bits<5> V3; 1508 bits<5> V4; 1509 bits<4> M5; 1510 bits<4> M6; 1511 1512 let Inst{47-40} = op{15-8}; 1513 let Inst{39-36} = V1{3-0}; 1514 let Inst{35-32} = V2{3-0}; 1515 let Inst{31-28} = V3{3-0}; 1516 let Inst{27-24} = M5; 1517 let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3}); 1518 let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2}); 1519 let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1}); 1520 let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0}); 1521 let Inst{19-16} = 0; 1522 let Inst{15-12} = V4{3-0}; 1523 let Inst{11} = V1{4}; 1524 let Inst{10} = V2{4}; 1525 let Inst{9} = V3{4}; 1526 let Inst{8} = V4{4}; 1527 let Inst{7-0} = op{7-0}; 1528} 1529 1530class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1531 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1532 field bits<48> Inst; 1533 field bits<48> SoftFail = 0; 1534 1535 bits<5> V1; 1536 bits<5> V2; 1537 bits<5> V3; 1538 bits<5> V4; 1539 bits<4> M5; 1540 bits<4> M6; 1541 1542 let Inst{47-40} = op{15-8}; 1543 let Inst{39-36} = V1{3-0}; 1544 let Inst{35-32} = V2{3-0}; 1545 let Inst{31-28} = V3{3-0}; 1546 let Inst{27-24} = M6; 1547 let Inst{23-20} = 0; 1548 let Inst{19-16} = M5; 1549 let Inst{15-12} = V4{3-0}; 1550 let Inst{11} = V1{4}; 1551 let Inst{10} = V2{4}; 1552 let Inst{9} = V3{4}; 1553 let Inst{8} = V4{4}; 1554 let Inst{7-0} = op{7-0}; 1555} 1556 1557class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1558 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1559 field bits<48> Inst; 1560 field bits<48> SoftFail = 0; 1561 1562 bits<5> V1; 1563 bits<4> R2; 1564 bits<4> R3; 1565 1566 let Inst{47-40} = op{15-8}; 1567 let Inst{39-36} = V1{3-0}; 1568 let Inst{35-32} = R2; 1569 let Inst{31-28} = R3; 1570 let Inst{27-12} = 0; 1571 let Inst{11} = V1{4}; 1572 let Inst{10-8} = 0; 1573 let Inst{7-0} = op{7-0}; 1574} 1575 1576class InstVRRg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1577 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1578 field bits<48> Inst; 1579 field bits<48> SoftFail = 0; 1580 1581 bits<5> V1; 1582 bits<16> I2; 1583 1584 let Inst{47-40} = op{15-8}; 1585 let Inst{39-36} = 0; 1586 let Inst{35-32} = V1{3-0}; 1587 let Inst{31-28} = 0; 1588 let Inst{27-12} = I2; 1589 let Inst{11} = 0; 1590 let Inst{10} = V1{4}; 1591 let Inst{9-8} = 0; 1592 let Inst{7-0} = op{7-0}; 1593} 1594 1595class InstVRRh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1596 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1597 field bits<48> Inst; 1598 field bits<48> SoftFail = 0; 1599 1600 bits<5> V1; 1601 bits<5> V2; 1602 bits<4> M3; 1603 1604 let Inst{47-40} = op{15-8}; 1605 let Inst{39-36} = 0; 1606 let Inst{35-32} = V1{3-0}; 1607 let Inst{31-28} = V2{3-0}; 1608 let Inst{27-24} = 0; 1609 let Inst{23-20} = M3; 1610 let Inst{19-12} = 0; 1611 let Inst{11} = 0; 1612 let Inst{10} = V1{4}; 1613 let Inst{9} = V2{4}; 1614 let Inst{8} = 0; 1615 let Inst{7-0} = op{7-0}; 1616} 1617 1618class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1619 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1620 field bits<48> Inst; 1621 field bits<48> SoftFail = 0; 1622 1623 bits<4> R1; 1624 bits<5> V2; 1625 bits<4> M3; 1626 bits<4> M4; 1627 1628 let Inst{47-40} = op{15-8}; 1629 let Inst{39-36} = R1; 1630 let Inst{35-32} = V2{3-0}; 1631 let Inst{31-24} = 0; 1632 let Inst{23-20} = M3; 1633 let Inst{19-16} = M4; 1634 let Inst{15-12} = 0; 1635 let Inst{11} = 0; 1636 let Inst{10} = V2{4}; 1637 let Inst{9-8} = 0; 1638 let Inst{7-0} = op{7-0}; 1639} 1640 1641class InstVRRj<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1642 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1643 field bits<48> Inst; 1644 field bits<48> SoftFail = 0; 1645 1646 bits<5> V1; 1647 bits<5> V2; 1648 bits<5> V3; 1649 bits<4> M4; 1650 1651 let Inst{47-40} = op{15-8}; 1652 let Inst{39-36} = V1{3-0}; 1653 let Inst{35-32} = V2{3-0}; 1654 let Inst{31-28} = V3{3-0}; 1655 let Inst{27-24} = 0; 1656 let Inst{23-20} = M4; 1657 let Inst{19-16} = 0; 1658 let Inst{15-12} = 0; 1659 let Inst{11} = V1{4}; 1660 let Inst{10} = V2{4}; 1661 let Inst{9} = V3{4}; 1662 let Inst{8} = 0; 1663 let Inst{7-0} = op{7-0}; 1664} 1665 1666class InstVRRk<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1667 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1668 field bits<48> Inst; 1669 field bits<48> SoftFail = 0; 1670 1671 bits<5> V1; 1672 bits<5> V2; 1673 bits<4> M3; 1674 1675 let Inst{47-40} = op{15-8}; 1676 let Inst{39-36} = V1{3-0}; 1677 let Inst{35-32} = V2{3-0}; 1678 let Inst{31-28} = 0; 1679 let Inst{27-24} = 0; 1680 let Inst{23-20} = M3; 1681 let Inst{19-16} = 0; 1682 let Inst{15-12} = 0; 1683 let Inst{11} = V1{4}; 1684 let Inst{10} = V2{4}; 1685 let Inst{9} = 0; 1686 let Inst{8} = 0; 1687 let Inst{7-0} = op{7-0}; 1688} 1689 1690class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1691 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1692 field bits<48> Inst; 1693 field bits<48> SoftFail = 0; 1694 1695 bits<5> V1; 1696 bits<4> B2; 1697 bits<12> D2; 1698 bits<5> V3; 1699 bits<4> M4; 1700 1701 let Inst{47-40} = op{15-8}; 1702 let Inst{39-36} = V1{3-0}; 1703 let Inst{35-32} = V3{3-0}; 1704 let Inst{31-28} = B2; 1705 let Inst{27-16} = D2; 1706 let Inst{15-12} = M4; 1707 let Inst{11} = V1{4}; 1708 let Inst{10} = V3{4}; 1709 let Inst{9-8} = 0; 1710 let Inst{7-0} = op{7-0}; 1711} 1712 1713class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1714 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1715 field bits<48> Inst; 1716 field bits<48> SoftFail = 0; 1717 1718 bits<5> V1; 1719 bits<4> B2; 1720 bits<12> D2; 1721 bits<4> R3; 1722 bits<4> M4; 1723 1724 let Inst{47-40} = op{15-8}; 1725 let Inst{39-36} = V1{3-0}; 1726 let Inst{35-32} = R3; 1727 let Inst{31-28} = B2; 1728 let Inst{27-16} = D2; 1729 let Inst{15-12} = M4; 1730 let Inst{11} = V1{4}; 1731 let Inst{10-8} = 0; 1732 let Inst{7-0} = op{7-0}; 1733} 1734 1735class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1736 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1737 field bits<48> Inst; 1738 field bits<48> SoftFail = 0; 1739 1740 bits<4> R1; 1741 bits<4> B2; 1742 bits<12> D2; 1743 bits<5> V3; 1744 bits<4> M4; 1745 1746 let Inst{47-40} = op{15-8}; 1747 let Inst{39-36} = R1; 1748 let Inst{35-32} = V3{3-0}; 1749 let Inst{31-28} = B2; 1750 let Inst{27-16} = D2; 1751 let Inst{15-12} = M4; 1752 let Inst{11} = 0; 1753 let Inst{10} = V3{4}; 1754 let Inst{9-8} = 0; 1755 let Inst{7-0} = op{7-0}; 1756} 1757 1758class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1759 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1760 field bits<48> Inst; 1761 field bits<48> SoftFail = 0; 1762 1763 bits<5> V1; 1764 bits<4> B2; 1765 bits<12> D2; 1766 bits<4> R3; 1767 1768 let Inst{47-40} = op{15-8}; 1769 let Inst{39-36} = 0; 1770 let Inst{35-32} = R3; 1771 let Inst{31-28} = B2; 1772 let Inst{27-16} = D2; 1773 let Inst{15-12} = V1{3-0}; 1774 let Inst{11-9} = 0; 1775 let Inst{8} = V1{4}; 1776 let Inst{7-0} = op{7-0}; 1777} 1778 1779class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1780 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1781 field bits<48> Inst; 1782 field bits<48> SoftFail = 0; 1783 1784 bits<5> V1; 1785 bits<5> V2; 1786 bits<4> B2; 1787 bits<12> D2; 1788 bits<4> M3; 1789 1790 let Inst{47-40} = op{15-8}; 1791 let Inst{39-36} = V1{3-0}; 1792 let Inst{35-32} = V2{3-0}; 1793 let Inst{31-28} = B2; 1794 let Inst{27-16} = D2; 1795 let Inst{15-12} = M3; 1796 let Inst{11} = V1{4}; 1797 let Inst{10} = V2{4}; 1798 let Inst{9-8} = 0; 1799 let Inst{7-0} = op{7-0}; 1800} 1801 1802class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1803 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1804 field bits<48> Inst; 1805 field bits<48> SoftFail = 0; 1806 1807 bits<5> V1; 1808 bits<4> X2; 1809 bits<4> B2; 1810 bits<12> D2; 1811 bits<4> M3; 1812 1813 let Inst{47-40} = op{15-8}; 1814 let Inst{39-36} = V1{3-0}; 1815 let Inst{35-32} = X2; 1816 let Inst{31-28} = B2; 1817 let Inst{27-16} = D2; 1818 let Inst{15-12} = M3; 1819 let Inst{11} = V1{4}; 1820 let Inst{10-8} = 0; 1821 let Inst{7-0} = op{7-0}; 1822} 1823 1824class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1825 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1826 field bits<48> Inst; 1827 field bits<48> SoftFail = 0; 1828 1829 bits<5> V1; 1830 bits<4> B2; 1831 bits<12> D2; 1832 bits<8> I3; 1833 1834 let Inst{47-40} = op{15-8}; 1835 let Inst{39-32} = I3; 1836 let Inst{31-28} = B2; 1837 let Inst{27-16} = D2; 1838 let Inst{15-12} = V1{3-0}; 1839 let Inst{11-9} = 0; 1840 let Inst{8} = V1{4}; 1841 let Inst{7-0} = op{7-0}; 1842} 1843 1844//===----------------------------------------------------------------------===// 1845// Instruction classes for .insn directives 1846//===----------------------------------------------------------------------===// 1847 1848class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern> 1849 : InstE<0, outs, ins, asmstr, pattern> { 1850 bits<16> enc; 1851 1852 let Inst = enc; 1853} 1854 1855class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern> 1856 : InstRIa<0, outs, ins, asmstr, pattern> { 1857 bits<32> enc; 1858 1859 let Inst{31-24} = enc{31-24}; 1860 let Inst{19-16} = enc{19-16}; 1861} 1862 1863class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern> 1864 : InstRIEd<0, outs, ins, asmstr, pattern> { 1865 bits<48> enc; 1866 1867 let Inst{47-40} = enc{47-40}; 1868 let Inst{7-0} = enc{7-0}; 1869} 1870 1871class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern> 1872 : InstRILa<0, outs, ins, asmstr, pattern> { 1873 bits<48> enc; 1874 string type; 1875 1876 let Inst{47-40} = enc{47-40}; 1877 let Inst{35-32} = enc{35-32}; 1878} 1879 1880class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern> 1881 : InstRIS<0, outs, ins, asmstr, pattern> { 1882 bits<48> enc; 1883 1884 let Inst{47-40} = enc{47-40}; 1885 let Inst{7-0} = enc{7-0}; 1886} 1887 1888class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern> 1889 : InstRR<0, outs, ins, asmstr, pattern> { 1890 bits<16> enc; 1891 1892 let Inst{15-8} = enc{15-8}; 1893} 1894 1895class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern> 1896 : InstRRE<0, outs, ins, asmstr, pattern> { 1897 bits<32> enc; 1898 1899 let Inst{31-16} = enc{31-16}; 1900} 1901 1902class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern> 1903 : InstRRFa<0, outs, ins, asmstr, pattern> { 1904 bits<32> enc; 1905 1906 let Inst{31-16} = enc{31-16}; 1907} 1908 1909class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern> 1910 : InstRRS<0, outs, ins, asmstr, pattern> { 1911 bits<48> enc; 1912 1913 let Inst{47-40} = enc{47-40}; 1914 let Inst{7-0} = enc{7-0}; 1915} 1916 1917class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern> 1918 : InstRSa<0, outs, ins, asmstr, pattern> { 1919 bits<32> enc; 1920 1921 let Inst{31-24} = enc{31-24}; 1922} 1923 1924class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern> 1925 : InstRSEa<6, outs, ins, asmstr, pattern> { 1926 bits <48> enc; 1927 1928 let Inst{47-40} = enc{47-40}; 1929 let Inst{7-0} = enc{7-0}; 1930} 1931 1932class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern> 1933 : InstRSI<0, outs, ins, asmstr, pattern> { 1934 bits<32> enc; 1935 1936 let Inst{31-24} = enc{31-24}; 1937} 1938 1939class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern> 1940 : InstRSYa<0, outs, ins, asmstr, pattern> { 1941 bits<48> enc; 1942 1943 let Inst{47-40} = enc{47-40}; 1944 let Inst{7-0} = enc{7-0}; 1945} 1946 1947class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern> 1948 : InstRXa<0, outs, ins, asmstr, pattern> { 1949 bits<32> enc; 1950 1951 let Inst{31-24} = enc{31-24}; 1952} 1953 1954class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern> 1955 : InstRXE<0, outs, ins, asmstr, pattern> { 1956 bits<48> enc; 1957 1958 let M3 = 0; 1959 1960 let Inst{47-40} = enc{47-40}; 1961 let Inst{7-0} = enc{7-0}; 1962} 1963 1964class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern> 1965 : InstRXF<0, outs, ins, asmstr, pattern> { 1966 bits<48> enc; 1967 1968 let Inst{47-40} = enc{47-40}; 1969 let Inst{7-0} = enc{7-0}; 1970} 1971 1972class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern> 1973 : InstRXYa<0, outs, ins, asmstr, pattern> { 1974 bits<48> enc; 1975 1976 let Inst{47-40} = enc{47-40}; 1977 let Inst{7-0} = enc{7-0}; 1978} 1979 1980class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern> 1981 : InstS<0, outs, ins, asmstr, pattern> { 1982 bits<32> enc; 1983 1984 let Inst{31-16} = enc{31-16}; 1985} 1986 1987class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern> 1988 : InstSI<0, outs, ins, asmstr, pattern> { 1989 bits<32> enc; 1990 1991 let Inst{31-24} = enc{31-24}; 1992} 1993 1994class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern> 1995 : InstSIY<0, outs, ins, asmstr, pattern> { 1996 bits<48> enc; 1997 1998 let Inst{47-40} = enc{47-40}; 1999 let Inst{7-0} = enc{7-0}; 2000} 2001 2002class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern> 2003 : InstSIL<0, outs, ins, asmstr, pattern> { 2004 bits<48> enc; 2005 2006 let Inst{47-32} = enc{47-32}; 2007} 2008 2009class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern> 2010 : InstSSd<0, outs, ins, asmstr, pattern> { 2011 bits<48> enc; 2012 2013 let Inst{47-40} = enc{47-40}; 2014} 2015 2016class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern> 2017 : InstSSE<0, outs, ins, asmstr, pattern> { 2018 bits<48> enc; 2019 2020 let Inst{47-32} = enc{47-32}; 2021} 2022 2023class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern> 2024 : InstSSF<0, outs, ins, asmstr, pattern> { 2025 bits<48> enc; 2026 2027 let Inst{47-40} = enc{47-40}; 2028 let Inst{35-32} = enc{35-32}; 2029} 2030 2031class DirectiveInsnVRI<dag outs, dag ins, string asmstr, list<dag> pattern> 2032 : InstVRIe<0, outs, ins, asmstr, pattern> { 2033 bits<48> enc; 2034 2035 let Inst{47-40} = enc{47-40}; 2036 let Inst{7-0} = enc{7-0}; 2037} 2038 2039class DirectiveInsnVRR<dag outs, dag ins, string asmstr, list<dag> pattern> 2040 : InstVRRc<0, outs, ins, asmstr, pattern> { 2041 bits<48> enc; 2042 2043 let Inst{47-40} = enc{47-40}; 2044 let Inst{7-0} = enc{7-0}; 2045} 2046 2047class DirectiveInsnVRS<dag outs, dag ins, string asmstr, list<dag> pattern> 2048 : InstVRSc<0, outs, ins, asmstr, pattern> { 2049 bits<48> enc; 2050 2051 let Inst{47-40} = enc{47-40}; 2052 let Inst{7-0} = enc{7-0}; 2053} 2054 2055class DirectiveInsnVRV<dag outs, dag ins, string asmstr, list<dag> pattern> 2056 : InstVRV<0, outs, ins, asmstr, pattern> { 2057 bits<48> enc; 2058 2059 let Inst{47-40} = enc{47-40}; 2060 let Inst{7-0} = enc{7-0}; 2061} 2062 2063class DirectiveInsnVRX<dag outs, dag ins, string asmstr, list<dag> pattern> 2064 : InstVRX<0, outs, ins, asmstr, pattern> { 2065 bits<48> enc; 2066 2067 let Inst{47-40} = enc{47-40}; 2068 let Inst{7-0} = enc{7-0}; 2069} 2070 2071class DirectiveInsnVSI<dag outs, dag ins, string asmstr, list<dag> pattern> 2072 : InstVSI<0, outs, ins, asmstr, pattern> { 2073 bits<48> enc; 2074 2075 let Inst{47-40} = enc{47-40}; 2076 let Inst{7-0} = enc{7-0}; 2077} 2078 2079 2080//===----------------------------------------------------------------------===// 2081// Variants of instructions with condition mask 2082//===----------------------------------------------------------------------===// 2083// 2084// For instructions using a condition mask (e.g. conditional branches, 2085// compare-and-branch instructions, or conditional move instructions), 2086// we generally need to create multiple instruction patterns: 2087// 2088// - One used for code generation, which encodes the condition mask as an 2089// MI operand, but writes out an extended mnemonic for better readability. 2090// - One pattern for the base form of the instruction with an explicit 2091// condition mask (encoded as a plain integer MI operand). 2092// - Specific patterns for each extended mnemonic, where the condition mask 2093// is implied by the pattern name and not otherwise encoded at all. 2094// 2095// We need the latter primarily for the assembler and disassembler, since the 2096// assembler parser is not able to decode part of an instruction mnemonic 2097// into an operand. Thus we provide separate patterns for each mnemonic. 2098// 2099// Note that in some cases there are two different mnemonics for the same 2100// condition mask. In this case we cannot have both instructions available 2101// to the disassembler at the same time since the encodings are not distinct. 2102// Therefore the alternate forms are marked isAsmParserOnly. 2103// 2104// We don't make one of the two names an alias of the other because 2105// we need the custom parsing routines to select the correct register class. 2106// 2107// This section provides helpers for generating the specific forms. 2108// 2109//===----------------------------------------------------------------------===// 2110 2111// A class to describe a variant of an instruction with condition mask. 2112class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein, 2113 string asmvariantin = ""> { 2114 // The fixed condition mask to use. 2115 bits<4> ccmask = ccmaskin; 2116 2117 // The suffix to use for the extended assembler mnemonic. 2118 string suffix = suffixin; 2119 2120 // Whether this is an alternate that needs to be marked isAsmParserOnly. 2121 bit alternate = alternatein; 2122 2123 // Whether this needs be to restricted to a specific dialect. 2124 // Valid values are "gnu" and "hlasm", which when passed in 2125 // will set AsmVariantName. 2126 string asmvariant = asmvariantin; 2127} 2128 2129// Condition mask 15 means "always true", which is used to define 2130// unconditional branches as a variant of conditional branches. 2131def CondAlways : CondVariant<15, "", 0>; 2132 2133// Condition masks for general instructions that can set all 4 bits. 2134def CondVariantO : CondVariant<1, "o", 0>; 2135def CondVariantH : CondVariant<2, "h", 0>; 2136def CondVariantP : CondVariant<2, "p", 1>; 2137def CondVariantNLE : CondVariant<3, "nle", 0, "gnu">; 2138def CondVariantL : CondVariant<4, "l", 0>; 2139def CondVariantM : CondVariant<4, "m", 1>; 2140def CondVariantNHE : CondVariant<5, "nhe", 0, "gnu">; 2141def CondVariantLH : CondVariant<6, "lh", 0, "gnu">; 2142def CondVariantNE : CondVariant<7, "ne", 0>; 2143def CondVariantNZ : CondVariant<7, "nz", 1>; 2144def CondVariantE : CondVariant<8, "e", 0>; 2145def CondVariantZ : CondVariant<8, "z", 1>; 2146def CondVariantNLH : CondVariant<9, "nlh", 0, "gnu">; 2147def CondVariantHE : CondVariant<10, "he", 0, "gnu">; 2148def CondVariantNL : CondVariant<11, "nl", 0>; 2149def CondVariantNM : CondVariant<11, "nm", 1>; 2150def CondVariantLE : CondVariant<12, "le", 0, "gnu">; 2151def CondVariantNH : CondVariant<13, "nh", 0>; 2152def CondVariantNP : CondVariant<13, "np", 1>; 2153def CondVariantNO : CondVariant<14, "no", 0>; 2154 2155// A helper class to look up one of the above by name. 2156class CV<string name> 2157 : CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask, 2158 !cast<CondVariant>("CondVariant"#name).suffix, 2159 !cast<CondVariant>("CondVariant"#name).alternate, 2160 !cast<CondVariant>("CondVariant"#name).asmvariant>; 2161 2162// Condition masks for integer instructions (e.g. compare-and-branch). 2163// This is like the list above, except that condition 3 is not possible 2164// and that the low bit of the mask is therefore always 0. This means 2165// that each condition has two names. Conditions "o" and "no" are not used. 2166def IntCondVariantH : CondVariant<2, "h", 0>; 2167def IntCondVariantNLE : CondVariant<2, "nle", 1, "gnu">; 2168def IntCondVariantL : CondVariant<4, "l", 0>; 2169def IntCondVariantNHE : CondVariant<4, "nhe", 1, "gnu">; 2170def IntCondVariantLH : CondVariant<6, "lh", 0, "gnu">; 2171def IntCondVariantNE : CondVariant<6, "ne", 1>; 2172def IntCondVariantE : CondVariant<8, "e", 0>; 2173def IntCondVariantNLH : CondVariant<8, "nlh", 1, "gnu">; 2174def IntCondVariantHE : CondVariant<10, "he", 0, "gnu">; 2175def IntCondVariantNL : CondVariant<10, "nl", 1>; 2176def IntCondVariantLE : CondVariant<12, "le", 0, "gnu">; 2177def IntCondVariantNH : CondVariant<12, "nh", 1>; 2178 2179// A helper class to look up one of the above by name. 2180class ICV<string name> 2181 : CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask, 2182 !cast<CondVariant>("IntCondVariant"#name).suffix, 2183 !cast<CondVariant>("IntCondVariant"#name).alternate, 2184 !cast<CondVariant>("IntCondVariant"#name).asmvariant>; 2185 2186// Defines a class that makes it easier to define 2187// a MnemonicAlias when CondVariant's are involved. 2188multiclass MnemonicCondBranchAlias<CondVariant V, string from, string to, 2189 string asmvariant = V.asmvariant> { 2190 if !or(!eq(V.asmvariant, ""), !eq(V.asmvariant, asmvariant)) then 2191 def "" : MnemonicAlias<!subst("#", V.suffix, from), 2192 !subst("#", V.suffix, to), 2193 asmvariant>; 2194} 2195 2196//===----------------------------------------------------------------------===// 2197// Instruction definitions with semantics 2198//===----------------------------------------------------------------------===// 2199// 2200// These classes have the form [Cond]<Category><Format>, where <Format> is one 2201// of the formats defined above and where <Category> describes the inputs 2202// and outputs. "Cond" is used if the instruction is conditional, 2203// in which case the 4-bit condition-code mask is added as a final operand. 2204// <Category> can be one of: 2205// 2206// Inherent: 2207// One register output operand and no input operands. 2208// 2209// InherentDual: 2210// Two register output operands and no input operands. 2211// 2212// StoreInherent: 2213// One address operand. The instruction stores to the address. 2214// 2215// SideEffectInherent: 2216// No input or output operands, but causes some side effect. 2217// 2218// Branch: 2219// One branch target. The instruction branches to the target. 2220// 2221// Call: 2222// One output operand and one branch target. The instruction stores 2223// the return address to the output operand and branches to the target. 2224// 2225// CmpBranch: 2226// Two input operands and one optional branch target. The instruction 2227// compares the two input operands and branches or traps on the result. 2228// 2229// BranchUnary: 2230// One register output operand, one register input operand and one branch 2231// target. The instructions stores a modified form of the source register 2232// in the destination register and branches on the result. 2233// 2234// BranchBinary: 2235// One register output operand, two register input operands and one branch 2236// target. The instructions stores a modified form of one of the source 2237// registers in the destination register and branches on the result. 2238// 2239// LoadMultiple: 2240// One address input operand and two explicit output operands. 2241// The instruction loads a range of registers from the address, 2242// with the explicit operands giving the first and last register 2243// to load. Other loaded registers are added as implicit definitions. 2244// 2245// StoreMultiple: 2246// Two explicit input register operands and an address operand. 2247// The instruction stores a range of registers to the address, 2248// with the explicit operands giving the first and last register 2249// to store. Other stored registers are added as implicit uses. 2250// 2251// StoreLength: 2252// One value operand, one length operand and one address operand. 2253// The instruction stores the value operand to the address but 2254// doesn't write more than the number of bytes specified by the 2255// length operand. 2256// 2257// LoadAddress: 2258// One register output operand and one address operand. 2259// 2260// LoadIndexedAddress: 2261// One register output operand and one indexed address operand. 2262// 2263// SideEffectAddress: 2264// One address operand. No output operands, but causes some side effect. 2265// 2266// Unary: 2267// One register output operand and one input operand. 2268// 2269// Store: 2270// One address operand and one other input operand. The instruction 2271// stores to the address. 2272// 2273// SideEffectUnary: 2274// One input operand. No output operands, but causes some side effect. 2275// 2276// Binary: 2277// One register output operand and two input operands. 2278// 2279// StoreBinary: 2280// One address operand and two other input operands. The instruction 2281// stores to the address. 2282// 2283// SideEffectBinary: 2284// Two input operands. No output operands, but causes some side effect. 2285// 2286// Compare: 2287// Two input operands and an implicit CC output operand. 2288// 2289// Test: 2290// One or two input operands and an implicit CC output operand. If 2291// present, the second input operand is an "address" operand used as 2292// a test class mask. 2293// 2294// Ternary: 2295// One register output operand and three input operands. 2296// 2297// SideEffectTernary: 2298// Three input operands. No output operands, but causes some side effect. 2299// 2300// Quaternary: 2301// One register output operand and four input operands. 2302// 2303// LoadAndOp: 2304// One output operand and two input operands, one of which is an address. 2305// The instruction both reads from and writes to the address. 2306// 2307// CmpSwap: 2308// One output operand and three input operands, one of which is an address. 2309// The instruction both reads from and writes to the address. 2310// 2311// RotateSelect: 2312// One output operand and five input operands. The first two operands 2313// are registers and the other three are immediates. 2314// 2315// Prefetch: 2316// One 4-bit immediate operand and one address operand. The immediate 2317// operand is 1 for a load prefetch and 2 for a store prefetch. 2318// 2319// BranchPreload: 2320// One 4-bit immediate operand and two address operands. 2321// 2322// The format determines which input operands are tied to output operands, 2323// and also determines the shape of any address operand. 2324// 2325// Multiclasses of the form <Category><Format>Pair define two instructions, 2326// one with <Category><Format> and one with <Category><Format>Y. The name 2327// of the first instruction has no suffix, the name of the second has 2328// an extra "y". 2329// 2330//===----------------------------------------------------------------------===// 2331 2332class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, 2333 SDPatternOperator operator> 2334 : InstRRE<opcode, (outs cls:$R1), (ins), 2335 mnemonic#"\t$R1", 2336 [(set cls:$R1, (operator))]> { 2337 let R2 = 0; 2338} 2339 2340class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls> 2341 : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins), 2342 mnemonic#"\t$R1, $R2", []>; 2343 2344class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value> 2345 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> { 2346 let I2 = value; 2347 let M3 = 0; 2348} 2349 2350class StoreInherentS<string mnemonic, bits<16> opcode, 2351 SDPatternOperator operator, bits<5> bytes> 2352 : InstS<opcode, (outs), (ins (bdaddr12only $B2, $D2):$BD2), 2353 mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> { 2354 let mayStore = 1; 2355 let AccessBytes = bytes; 2356} 2357 2358class SideEffectInherentE<string mnemonic, bits<16>opcode> 2359 : InstE<opcode, (outs), (ins), mnemonic, []>; 2360 2361class SideEffectInherentS<string mnemonic, bits<16> opcode, 2362 SDPatternOperator operator> 2363 : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> { 2364 let B2 = 0; 2365 let D2 = 0; 2366} 2367 2368class SideEffectInherentRRE<string mnemonic, bits<16> opcode> 2369 : InstRRE<opcode, (outs), (ins), mnemonic, []> { 2370 let R1 = 0; 2371 let R2 = 0; 2372} 2373 2374// Allow an optional TLS marker symbol to generate TLS call relocations. 2375class CallRI<string mnemonic, bits<12> opcode> 2376 : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2), 2377 mnemonic#"\t$R1, $RI2", []>; 2378 2379// Allow an optional TLS marker symbol to generate TLS call relocations. 2380class CallRIL<string mnemonic, bits<12> opcode> 2381 : InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2), 2382 mnemonic#"\t$R1, $RI2", []>; 2383 2384class CallRR<string mnemonic, bits<8> opcode> 2385 : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2), 2386 mnemonic#"\t$R1, $R2", []>; 2387 2388class CallRX<string mnemonic, bits<8> opcode> 2389 : InstRXa<opcode, (outs), (ins GR64:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2390 mnemonic#"\t$R1, $XBD2", []>; 2391 2392class CondBranchRI<string mnemonic, bits<12> opcode, 2393 SDPatternOperator operator = null_frag> 2394 : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2), 2395 !subst("#", "${M1}", mnemonic)#"\t$RI2", 2396 [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> { 2397 let CCMaskFirst = 1; 2398} 2399 2400class AsmCondBranchRI<string mnemonic, bits<12> opcode> 2401 : InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2), 2402 mnemonic#"\t$M1, $RI2", []>; 2403 2404class NeverCondBranchRI<string mnemonic, bits<12> opcode> 2405 : InstRIc<opcode, (outs), (ins brtarget16:$RI2), 2406 mnemonic#"\t$RI2", []> { 2407 let M1 = 0; 2408} 2409 2410class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode, 2411 SDPatternOperator operator = null_frag> 2412 : InstRIc<opcode, (outs), (ins brtarget16:$RI2), 2413 !subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> { 2414 let isAsmParserOnly = V.alternate; 2415 let AsmVariantName = V.asmvariant; 2416 let M1 = V.ccmask; 2417} 2418 2419class CondBranchRIL<string mnemonic, bits<12> opcode> 2420 : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2), 2421 !subst("#", "${M1}", mnemonic)#"\t$RI2", []> { 2422 let CCMaskFirst = 1; 2423} 2424 2425class AsmCondBranchRIL<string mnemonic, bits<12> opcode> 2426 : InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2), 2427 mnemonic#"\t$M1, $RI2", []>; 2428 2429class NeverCondBranchRIL<string mnemonic, bits<12> opcode> 2430 : InstRILc<opcode, (outs), (ins brtarget32:$RI2), 2431 mnemonic#"\t$RI2", []> { 2432 let M1 = 0; 2433} 2434 2435class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode> 2436 : InstRILc<opcode, (outs), (ins brtarget32:$RI2), 2437 !subst("#", V.suffix, mnemonic)#"\t$RI2", []> { 2438 let isAsmParserOnly = V.alternate; 2439 let AsmVariantName = V.asmvariant; 2440 let M1 = V.ccmask; 2441} 2442 2443class CondBranchRR<string mnemonic, bits<8> opcode> 2444 : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2), 2445 !subst("#", "${R1}", mnemonic)#"\t$R2", []> { 2446 let CCMaskFirst = 1; 2447} 2448 2449class AsmCondBranchRR<string mnemonic, bits<8> opcode> 2450 : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2), 2451 mnemonic#"\t$R1, $R2", []>; 2452 2453multiclass NeverCondBranchRR<string mnemonic, bits<8> opcode> { 2454 // For the no-op (always false) branch, the target is optional. 2455 def "" : InstRR<opcode, (outs), (ins GR64:$R2), 2456 mnemonic#"\t$R2", []> { 2457 let R1 = 0; 2458 } 2459 def Opt : InstRR<opcode, (outs), (ins), mnemonic, []> { 2460 let R1 = 0; 2461 let R2 = 0; 2462 } 2463} 2464 2465class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode, 2466 SDPatternOperator operator = null_frag> 2467 : InstRR<opcode, (outs), (ins ADDR64:$R2), 2468 !subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> { 2469 let isAsmParserOnly = V.alternate; 2470 let AsmVariantName = V.asmvariant; 2471 let R1 = V.ccmask; 2472} 2473 2474class CondBranchRX<string mnemonic, bits<8> opcode> 2475 : InstRXb<opcode, (outs), 2476 (ins cond4:$valid, cond4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2477 !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> { 2478 let CCMaskFirst = 1; 2479} 2480 2481class AsmCondBranchRX<string mnemonic, bits<8> opcode> 2482 : InstRXb<opcode, (outs), 2483 (ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2484 mnemonic#"\t$M1, $XBD2", []>; 2485 2486multiclass NeverCondBranchRX<string mnemonic, bits<8> opcode> { 2487 // For the no-op (always false) branch, the target is optional. 2488 def "" : InstRXb<opcode, (outs), 2489 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2), 2490 mnemonic#"\t$XBD2", []> { 2491 let M1 = 0; 2492 } 2493 def Opt : InstRXb<opcode, (outs), (ins), mnemonic, []> { 2494 let M1 = 0; 2495 let B2 = 0; 2496 let D2 = 0; 2497 let X2 = 0; 2498 } 2499} 2500 2501class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode> 2502 : InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2), 2503 !subst("#", V.suffix, mnemonic)#"\t$XBD2", []> { 2504 let isAsmParserOnly = V.alternate; 2505 let AsmVariantName = V.asmvariant; 2506 let M1 = V.ccmask; 2507} 2508 2509class CondBranchRXY<string mnemonic, bits<16> opcode> 2510 : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, 2511 (bdxaddr20only $B2, $D2, $X2):$XBD2), 2512 !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> { 2513 let CCMaskFirst = 1; 2514 let mayLoad = 1; 2515} 2516 2517class AsmCondBranchRXY<string mnemonic, bits<16> opcode> 2518 : InstRXYb<opcode, (outs), 2519 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2), 2520 mnemonic#"\t$M1, $XBD2", []> { 2521 let mayLoad = 1; 2522} 2523 2524class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode, 2525 SDPatternOperator operator = null_frag> 2526 : InstRXYb<opcode, (outs), (ins (bdxaddr20only $B2, $D2, $X2):$XBD2), 2527 !subst("#", V.suffix, mnemonic)#"\t$XBD2", 2528 [(operator (load bdxaddr20only:$XBD2))]> { 2529 let isAsmParserOnly = V.alternate; 2530 let AsmVariantName = V.asmvariant; 2531 let M1 = V.ccmask; 2532 let mayLoad = 1; 2533} 2534 2535class CmpBranchRIEa<string mnemonic, bits<16> opcode, 2536 RegisterOperand cls, ImmOpWithPattern imm> 2537 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3), 2538 mnemonic#"$M3\t$R1, $I2", []>; 2539 2540class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode, 2541 RegisterOperand cls, ImmOpWithPattern imm> 2542 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3), 2543 mnemonic#"\t$R1, $I2, $M3", []>; 2544 2545class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode, 2546 RegisterOperand cls, ImmOpWithPattern imm> 2547 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2), 2548 mnemonic#V.suffix#"\t$R1, $I2", []> { 2549 let isAsmParserOnly = V.alternate; 2550 let AsmVariantName = V.asmvariant; 2551 let M3 = V.ccmask; 2552} 2553 2554multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode, 2555 RegisterOperand cls, ImmOpWithPattern imm> { 2556 let isCodeGenOnly = 1 in 2557 def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>; 2558 def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>; 2559} 2560 2561class CmpBranchRIEb<string mnemonic, bits<16> opcode, 2562 RegisterOperand cls> 2563 : InstRIEb<opcode, (outs), 2564 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4), 2565 mnemonic#"$M3\t$R1, $R2, $RI4", []>; 2566 2567class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode, 2568 RegisterOperand cls> 2569 : InstRIEb<opcode, (outs), 2570 (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4), 2571 mnemonic#"\t$R1, $R2, $M3, $RI4", []>; 2572 2573class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode, 2574 RegisterOperand cls> 2575 : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4), 2576 mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> { 2577 let isAsmParserOnly = V.alternate; 2578 let AsmVariantName = V.asmvariant; 2579 let M3 = V.ccmask; 2580} 2581 2582multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode, 2583 RegisterOperand cls> { 2584 let isCodeGenOnly = 1 in 2585 def "" : CmpBranchRIEb<mnemonic, opcode, cls>; 2586 def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>; 2587} 2588 2589class CmpBranchRIEc<string mnemonic, bits<16> opcode, 2590 RegisterOperand cls, ImmOpWithPattern imm> 2591 : InstRIEc<opcode, (outs), 2592 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4), 2593 mnemonic#"$M3\t$R1, $I2, $RI4", []>; 2594 2595class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode, 2596 RegisterOperand cls, ImmOpWithPattern imm> 2597 : InstRIEc<opcode, (outs), 2598 (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4), 2599 mnemonic#"\t$R1, $I2, $M3, $RI4", []>; 2600 2601class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode, 2602 RegisterOperand cls, ImmOpWithPattern imm> 2603 : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4), 2604 mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> { 2605 let isAsmParserOnly = V.alternate; 2606 let AsmVariantName = V.asmvariant; 2607 let M3 = V.ccmask; 2608} 2609 2610multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode, 2611 RegisterOperand cls, ImmOpWithPattern imm> { 2612 let isCodeGenOnly = 1 in 2613 def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>; 2614 def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>; 2615} 2616 2617class CmpBranchRRFc<string mnemonic, bits<16> opcode, 2618 RegisterOperand cls> 2619 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3), 2620 mnemonic#"$M3\t$R1, $R2", []>; 2621 2622class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode, 2623 RegisterOperand cls> 2624 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3), 2625 mnemonic#"\t$R1, $R2, $M3", []>; 2626 2627multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode, 2628 RegisterOperand cls> { 2629 let isCodeGenOnly = 1 in 2630 def "" : CmpBranchRRFc<mnemonic, opcode, cls>; 2631 def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>; 2632} 2633 2634class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode, 2635 RegisterOperand cls> 2636 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2), 2637 mnemonic#V.suffix#"\t$R1, $R2", []> { 2638 let isAsmParserOnly = V.alternate; 2639 let AsmVariantName = V.asmvariant; 2640 let M3 = V.ccmask; 2641} 2642 2643class CmpBranchRRS<string mnemonic, bits<16> opcode, 2644 RegisterOperand cls> 2645 : InstRRS<opcode, (outs), 2646 (ins cls:$R1, cls:$R2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4), 2647 mnemonic#"$M3\t$R1, $R2, $BD4", []>; 2648 2649class AsmCmpBranchRRS<string mnemonic, bits<16> opcode, 2650 RegisterOperand cls> 2651 : InstRRS<opcode, (outs), 2652 (ins cls:$R1, cls:$R2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4), 2653 mnemonic#"\t$R1, $R2, $M3, $BD4", []>; 2654 2655class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode, 2656 RegisterOperand cls> 2657 : InstRRS<opcode, (outs), 2658 (ins cls:$R1, cls:$R2, (bdaddr12only $B4, $D4):$BD4), 2659 mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> { 2660 let isAsmParserOnly = V.alternate; 2661 let AsmVariantName = V.asmvariant; 2662 let M3 = V.ccmask; 2663} 2664 2665multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode, 2666 RegisterOperand cls> { 2667 let isCodeGenOnly = 1 in 2668 def "" : CmpBranchRRS<mnemonic, opcode, cls>; 2669 def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>; 2670} 2671 2672class CmpBranchRIS<string mnemonic, bits<16> opcode, 2673 RegisterOperand cls, ImmOpWithPattern imm> 2674 : InstRIS<opcode, (outs), 2675 (ins cls:$R1, imm:$I2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4), 2676 mnemonic#"$M3\t$R1, $I2, $BD4", []>; 2677 2678class AsmCmpBranchRIS<string mnemonic, bits<16> opcode, 2679 RegisterOperand cls, ImmOpWithPattern imm> 2680 : InstRIS<opcode, (outs), 2681 (ins cls:$R1, imm:$I2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4), 2682 mnemonic#"\t$R1, $I2, $M3, $BD4", []>; 2683 2684class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode, 2685 RegisterOperand cls, ImmOpWithPattern imm> 2686 : InstRIS<opcode, (outs), 2687 (ins cls:$R1, imm:$I2, (bdaddr12only $B4, $D4):$BD4), 2688 mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> { 2689 let isAsmParserOnly = V.alternate; 2690 let AsmVariantName = V.asmvariant; 2691 let M3 = V.ccmask; 2692} 2693 2694multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode, 2695 RegisterOperand cls, ImmOpWithPattern imm> { 2696 let isCodeGenOnly = 1 in 2697 def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>; 2698 def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>; 2699} 2700 2701class CmpBranchRSYb<string mnemonic, bits<16> opcode, 2702 RegisterOperand cls> 2703 : InstRSYb<opcode, (outs), 2704 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, cond4:$M3), 2705 mnemonic#"$M3\t$R1, $BD2", []>; 2706 2707class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode, 2708 RegisterOperand cls> 2709 : InstRSYb<opcode, (outs), 2710 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3), 2711 mnemonic#"\t$R1, $M3, $BD2", []>; 2712 2713multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode, 2714 RegisterOperand cls> { 2715 let isCodeGenOnly = 1 in 2716 def "" : CmpBranchRSYb<mnemonic, opcode, cls>; 2717 def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>; 2718} 2719 2720class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode, 2721 RegisterOperand cls> 2722 : InstRSYb<opcode, (outs), (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2), 2723 mnemonic#V.suffix#"\t$R1, $BD2", []> { 2724 let isAsmParserOnly = V.alternate; 2725 let AsmVariantName = V.asmvariant; 2726 let M3 = V.ccmask; 2727} 2728 2729class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls> 2730 : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2), 2731 mnemonic#"\t$R1, $RI2", []> { 2732 let Constraints = "$R1 = $R1src"; 2733 let DisableEncoding = "$R1src"; 2734} 2735 2736class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls> 2737 : InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2), 2738 mnemonic#"\t$R1, $RI2", []> { 2739 let Constraints = "$R1 = $R1src"; 2740 let DisableEncoding = "$R1src"; 2741} 2742 2743class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls> 2744 : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2), 2745 mnemonic#"\t$R1, $R2", []> { 2746 let Constraints = "$R1 = $R1src"; 2747 let DisableEncoding = "$R1src"; 2748} 2749 2750class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls> 2751 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2), 2752 mnemonic#"\t$R1, $R2", []> { 2753 let Constraints = "$R1 = $R1src"; 2754 let DisableEncoding = "$R1src"; 2755} 2756 2757class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls> 2758 : InstRXa<opcode, (outs cls:$R1), 2759 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2760 mnemonic#"\t$R1, $XBD2", []> { 2761 let Constraints = "$R1 = $R1src"; 2762 let DisableEncoding = "$R1src"; 2763} 2764 2765class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls> 2766 : InstRXYa<opcode, (outs cls:$R1), 2767 (ins cls:$R1src, (bdxaddr20only $B2, $D2, $X2):$XBD2), 2768 mnemonic#"\t$R1, $XBD2", []> { 2769 let Constraints = "$R1 = $R1src"; 2770 let DisableEncoding = "$R1src"; 2771} 2772 2773class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls> 2774 : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2), 2775 mnemonic#"\t$R1, $R3, $RI2", []> { 2776 let Constraints = "$R1 = $R1src"; 2777 let DisableEncoding = "$R1src"; 2778} 2779 2780class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls> 2781 : InstRIEe<opcode, (outs cls:$R1), 2782 (ins cls:$R1src, cls:$R3, brtarget16:$RI2), 2783 mnemonic#"\t$R1, $R3, $RI2", []> { 2784 let Constraints = "$R1 = $R1src"; 2785 let DisableEncoding = "$R1src"; 2786} 2787 2788class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls> 2789 : InstRSa<opcode, (outs cls:$R1), 2790 (ins cls:$R1src, cls:$R3, (bdaddr12only $B2, $D2):$BD2), 2791 mnemonic#"\t$R1, $R3, $BD2", []> { 2792 let Constraints = "$R1 = $R1src"; 2793 let DisableEncoding = "$R1src"; 2794} 2795 2796class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> 2797 : InstRSYa<opcode, 2798 (outs cls:$R1), 2799 (ins cls:$R1src, cls:$R3, (bdaddr20only $B2, $D2):$BD2), 2800 mnemonic#"\t$R1, $R3, $BD2", []> { 2801 let Constraints = "$R1 = $R1src"; 2802 let DisableEncoding = "$R1src"; 2803} 2804 2805class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 2806 AddressingMode mode = bdaddr12only> 2807 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2), 2808 mnemonic#"\t$R1, $R3, $BD2", []> { 2809 let mayLoad = 1; 2810} 2811 2812class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 2813 AddressingMode mode = bdaddr20only> 2814 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2), 2815 mnemonic#"\t$R1, $R3, $BD2", []> { 2816 let mayLoad = 1; 2817} 2818 2819multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode, 2820 bits<16> rsyOpcode, RegisterOperand cls> { 2821 let DispKey = mnemonic # cls in { 2822 let DispSize = "12" in 2823 def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>; 2824 let DispSize = "20" in 2825 def Y : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>; 2826 } 2827} 2828 2829class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls> 2830 : InstSSe<opcode, (outs cls:$R1, cls:$R3), 2831 (ins (bdaddr12only $B2, $D2):$BD2, (bdaddr12only $B4, $D4):$BD4), 2832 mnemonic#"\t$R1, $R3, $BD2, $BD4", []> { 2833 let mayLoad = 1; 2834} 2835 2836multiclass LoadMultipleVRSaAlign<string mnemonic, bits<16> opcode> { 2837 let mayLoad = 1 in { 2838 def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), 2839 (ins (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4), 2840 mnemonic#"\t$V1, $V3, $BD2, $M4", []>; 2841 let M4 = 0 in 2842 def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), 2843 (ins (bdaddr12only $B2, $D2):$BD2), 2844 mnemonic#"\t$V1, $V3, $BD2", []>; 2845 } 2846} 2847 2848class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 2849 RegisterOperand cls> 2850 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2), 2851 mnemonic#"\t$R1, $RI2", 2852 [(operator cls:$R1, pcrel32:$RI2)]> { 2853 let mayStore = 1; 2854 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 2855 // However, BDXs have two extra operands and are therefore 6 units more 2856 // complex. 2857 let AddedComplexity = 7; 2858} 2859 2860class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 2861 RegisterOperand cls, bits<5> bytes, 2862 AddressingMode mode = bdxaddr12only> 2863 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 2864 mnemonic#"\t$R1, $XBD2", 2865 [(operator cls:$R1, mode:$XBD2)]> { 2866 let OpKey = mnemonic#"r"#cls; 2867 let OpType = "mem"; 2868 let mayStore = 1; 2869 let AccessBytes = bytes; 2870} 2871 2872class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2873 RegisterOperand cls, bits<5> bytes, 2874 AddressingMode mode = bdxaddr20only> 2875 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 2876 mnemonic#"\t$R1, $XBD2", 2877 [(operator cls:$R1, mode:$XBD2)]> { 2878 let OpKey = mnemonic#"r"#cls; 2879 let OpType = "mem"; 2880 let mayStore = 1; 2881 let AccessBytes = bytes; 2882} 2883 2884multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 2885 SDPatternOperator operator, RegisterOperand cls, 2886 bits<5> bytes> { 2887 let DispKey = mnemonic # cls in { 2888 let DispSize = "12" in 2889 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 2890 let DispSize = "20" in 2891 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 2892 bdxaddr20pair>; 2893 } 2894} 2895 2896class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2897 TypedReg tr, bits<5> bytes, bits<4> type = 0> 2898 : InstVRX<opcode, (outs), 2899 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2900 mnemonic#"\t$V1, $XBD2", 2901 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2)]> { 2902 let M3 = type; 2903 let mayStore = 1; 2904 let AccessBytes = bytes; 2905} 2906 2907class StoreVRXGeneric<string mnemonic, bits<16> opcode> 2908 : InstVRX<opcode, (outs), 2909 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 2910 mnemonic#"\t$V1, $XBD2, $M3", []> { 2911 let mayStore = 1; 2912} 2913 2914multiclass StoreVRXAlign<string mnemonic, bits<16> opcode> { 2915 let mayStore = 1, AccessBytes = 16 in { 2916 def Align : InstVRX<opcode, (outs), 2917 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, 2918 imm32zx4:$M3), 2919 mnemonic#"\t$V1, $XBD2, $M3", []>; 2920 let M3 = 0 in 2921 def "" : InstVRX<opcode, (outs), 2922 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2923 mnemonic#"\t$V1, $XBD2", []>; 2924 } 2925} 2926 2927class StoreLengthVRSb<string mnemonic, bits<16> opcode, 2928 SDPatternOperator operator, bits<5> bytes> 2929 : InstVRSb<opcode, (outs), 2930 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2), 2931 mnemonic#"\t$V1, $R3, $BD2", 2932 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> { 2933 let M4 = 0; 2934 let mayStore = 1; 2935 let AccessBytes = bytes; 2936} 2937 2938class StoreLengthVRSd<string mnemonic, bits<16> opcode, 2939 SDPatternOperator operator, bits<5> bytes> 2940 : InstVRSd<opcode, (outs), 2941 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2), 2942 mnemonic#"\t$V1, $R3, $BD2", 2943 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> { 2944 let mayStore = 1; 2945 let AccessBytes = bytes; 2946} 2947 2948class StoreLengthVSI<string mnemonic, bits<16> opcode, 2949 SDPatternOperator operator, bits<5> bytes> 2950 : InstVSI<opcode, (outs), 2951 (ins VR128:$V1, (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3), 2952 mnemonic#"\t$V1, $BD2, $I3", 2953 [(operator VR128:$V1, imm32zx8:$I3, bdaddr12only:$BD2)]> { 2954 let mayStore = 1; 2955 let AccessBytes = bytes; 2956} 2957 2958class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 2959 AddressingMode mode = bdaddr12only> 2960 : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2), 2961 mnemonic#"\t$R1, $R3, $BD2", []> { 2962 let mayStore = 1; 2963} 2964 2965class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 2966 AddressingMode mode = bdaddr20only> 2967 : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2), 2968 mnemonic#"\t$R1, $R3, $BD2", []> { 2969 let mayStore = 1; 2970} 2971 2972multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode, 2973 bits<16> rsyOpcode, RegisterOperand cls> { 2974 let DispKey = mnemonic # cls in { 2975 let DispSize = "12" in 2976 def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>; 2977 let DispSize = "20" in 2978 def Y : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>; 2979 } 2980} 2981 2982multiclass StoreMultipleVRSaAlign<string mnemonic, bits<16> opcode> { 2983 let mayStore = 1 in { 2984 def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, 2985 (bdaddr12only $B2, $D2):$BD2, 2986 imm32zx4:$M4), 2987 mnemonic#"\t$V1, $V3, $BD2, $M4", []>; 2988 let M4 = 0 in 2989 def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, 2990 (bdaddr12only $B2, $D2):$BD2), 2991 mnemonic#"\t$V1, $V3, $BD2", []>; 2992 } 2993} 2994 2995// StoreSI* instructions are used to store an integer to memory, but the 2996// addresses are more restricted than for normal stores. If we are in the 2997// situation of having to force either the address into a register or the 2998// constant into a register, it's usually better to do the latter. 2999// We therefore match the address in the same way as a normal store and 3000// only use the StoreSI* instruction if the matched address is suitable. 3001class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3002 ImmOpWithPattern imm> 3003 : InstSI<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2), 3004 mnemonic#"\t$BD1, $I2", 3005 [(operator imm:$I2, mviaddr12pair:$BD1)]> { 3006 let mayStore = 1; 3007} 3008 3009class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3010 ImmOpWithPattern imm> 3011 : InstSIY<opcode, (outs), (ins (mviaddr20pair $B1, $D1):$BD1, imm:$I2), 3012 mnemonic#"\t$BD1, $I2", 3013 [(operator imm:$I2, mviaddr20pair:$BD1)]> { 3014 let mayStore = 1; 3015} 3016 3017class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3018 ImmOpWithPattern imm> 3019 : InstSIL<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2), 3020 mnemonic#"\t$BD1, $I2", 3021 [(operator imm:$I2, mviaddr12pair:$BD1)]> { 3022 let mayStore = 1; 3023} 3024 3025multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 3026 SDPatternOperator operator, ImmOpWithPattern imm> { 3027 let DispKey = mnemonic in { 3028 let DispSize = "12" in 3029 def "" : StoreSI<mnemonic, siOpcode, operator, imm>; 3030 let DispSize = "20" in 3031 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>; 3032 } 3033} 3034 3035class StoreSSE<string mnemonic, bits<16> opcode> 3036 : InstSSE<opcode, (outs), 3037 (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2), 3038 mnemonic#"\t$BD1, $BD2", []> { 3039 let mayStore = 1; 3040} 3041 3042class CondStoreRSY<string mnemonic, bits<16> opcode, 3043 RegisterOperand cls, bits<5> bytes, 3044 AddressingMode mode = bdaddr20only> 3045 : InstRSYb<opcode, (outs), 3046 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), 3047 mnemonic#"$M3\t$R1, $BD2", []> { 3048 let mayStore = 1; 3049 let AccessBytes = bytes; 3050 let CCMaskLast = 1; 3051} 3052 3053// Like CondStoreRSY, but used for the raw assembly form. The condition-code 3054// mask is the third operand rather than being part of the mnemonic. 3055class AsmCondStoreRSY<string mnemonic, bits<16> opcode, 3056 RegisterOperand cls, bits<5> bytes, 3057 AddressingMode mode = bdaddr20only> 3058 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2, imm32zx4:$M3), 3059 mnemonic#"\t$R1, $BD2, $M3", []> { 3060 let mayStore = 1; 3061 let AccessBytes = bytes; 3062} 3063 3064// Like CondStoreRSY, but with a fixed CC mask. 3065class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode, 3066 RegisterOperand cls, bits<5> bytes, 3067 AddressingMode mode = bdaddr20only> 3068 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2), 3069 mnemonic#V.suffix#"\t$R1, $BD2", []> { 3070 let mayStore = 1; 3071 let AccessBytes = bytes; 3072 let isAsmParserOnly = V.alternate; 3073 let AsmVariantName = V.asmvariant; 3074 let M3 = V.ccmask; 3075} 3076 3077multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode, 3078 RegisterOperand cls, bits<5> bytes, 3079 AddressingMode mode = bdaddr20only> { 3080 let isCodeGenOnly = 1 in 3081 def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>; 3082 def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>; 3083} 3084 3085class SideEffectUnaryI<string mnemonic, bits<8> opcode, ImmOpWithPattern imm> 3086 : InstI<opcode, (outs), (ins imm:$I1), 3087 mnemonic#"\t$I1", []>; 3088 3089class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls> 3090 : InstRR<opcode, (outs), (ins cls:$R1), 3091 mnemonic#"\t$R1", []> { 3092 let R2 = 0; 3093} 3094 3095class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, 3096 SDPatternOperator operator> 3097 : InstRRE<opcode, (outs), (ins cls:$R1), 3098 mnemonic#"\t$R1", [(operator cls:$R1)]> { 3099 let R2 = 0; 3100} 3101 3102class SideEffectUnaryS<string mnemonic, bits<16> opcode, 3103 SDPatternOperator operator, bits<5> bytes, 3104 AddressingMode mode = bdaddr12only> 3105 : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2), 3106 mnemonic#"\t$BD2", [(operator mode:$BD2)]> { 3107 let mayLoad = 1; 3108 let AccessBytes = bytes; 3109} 3110 3111class SideEffectUnarySIY<string mnemonic, bits<16> opcode, 3112 bits<5> bytes, 3113 AddressingMode mode = bdaddr20only> 3114 : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1), 3115 mnemonic#"\t$BD1", []> { 3116 let mayLoad = 1; 3117 let AccessBytes = bytes; 3118 let I2 = 0; 3119} 3120 3121class SideEffectAddressS<string mnemonic, bits<16> opcode, 3122 SDPatternOperator operator, 3123 AddressingMode mode = bdaddr12only> 3124 : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2), 3125 mnemonic#"\t$BD2", [(operator mode:$BD2)]>; 3126 3127class LoadAddressRX<string mnemonic, bits<8> opcode, 3128 SDPatternOperator operator, AddressingMode mode> 3129 : InstRXa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2), 3130 mnemonic#"\t$R1, $XBD2", 3131 [(set GR64:$R1, (operator mode:$XBD2))]>; 3132 3133class LoadAddressRXY<string mnemonic, bits<16> opcode, 3134 SDPatternOperator operator, AddressingMode mode> 3135 : InstRXYa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2), 3136 mnemonic#"\t$R1, $XBD2", 3137 [(set GR64:$R1, (operator mode:$XBD2))]>; 3138 3139multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode, 3140 bits<16> rxyOpcode, SDPatternOperator operator> { 3141 let DispKey = mnemonic in { 3142 let DispSize = "12" in 3143 def "" : LoadAddressRX<mnemonic, rxOpcode, operator, laaddr12pair>; 3144 let DispSize = "20" in 3145 def Y : LoadAddressRXY<mnemonic#"y", rxyOpcode, operator, laaddr20pair>; 3146 } 3147} 3148 3149class LoadAddressRIL<string mnemonic, bits<12> opcode, 3150 SDPatternOperator operator> 3151 : InstRILb<opcode, (outs GR64:$R1), (ins pcrel32:$RI2), 3152 mnemonic#"\t$R1, $RI2", 3153 [(set GR64:$R1, (operator pcrel32:$RI2))]>; 3154 3155multiclass LoadIndexedAddressRXY<string mnemonic, bits<16> opcode, 3156 SDPatternOperator ext, 3157 SDPatternOperator shift = bitconvert> { 3158 def "" : InstRXYa<opcode, (outs GR64:$R1), 3159 (ins (lxaaddr20only $B2, $D2, $X2):$XBD2), 3160 mnemonic#"\t$R1, $XBD2", []>; 3161 3162 // Patterns matching LXA with displacement. 3163 def : Pat<(add ADDR64:$base, 3164 (shift (i64 (ext (add ADDR32:$index, disp20imm32:$disp))))), 3165 (!cast<Instruction>(NAME) ADDR64:$base, imm32:$disp, ADDR32:$index)>; 3166 def : Pat<(shift (i64 (ext (add ADDR32:$index, disp20imm32:$disp)))), 3167 (!cast<Instruction>(NAME) zero_reg, imm32:$disp, ADDR32:$index)>; 3168 3169 // Patterns matching LXA without displacement. These are only beneficial 3170 // if we have a non-trivial shift. Also, we need to add some complexity 3171 // to account for the fact that the regular shift patterns have rather 3172 // high complexity values due to allowing base + displacement. 3173 if !ne(shift, bitconvert) then let AddedComplexity = 2 in { 3174 def : Pat<(add ADDR64:$base, (shift (i64 (ext ADDR32:$index)))), 3175 (!cast<Instruction>(NAME) ADDR64:$base, 0, ADDR32:$index)>; 3176 def : Pat<(shift (i64 (ext ADDR32:$index))), 3177 (!cast<Instruction>(NAME) zero_reg, 0, ADDR32:$index)>; 3178 } 3179} 3180 3181class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3182 RegisterOperand cls1, RegisterOperand cls2> 3183 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2), 3184 mnemonic#"\t$R1, $R2", 3185 [(set cls1:$R1, (operator cls2:$R2))]> { 3186 let OpKey = mnemonic#cls1; 3187 let OpType = "reg"; 3188} 3189 3190class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3191 RegisterOperand cls1, RegisterOperand cls2> 3192 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2), 3193 mnemonic#"\t$R1, $R2", 3194 [(set cls1:$R1, (operator cls2:$R2))]> { 3195 let OpKey = mnemonic#cls1; 3196 let OpType = "reg"; 3197} 3198 3199class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls> 3200 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src), 3201 mnemonic#"\t$R1", []> { 3202 let Constraints = "$R1 = $R1src"; 3203 let DisableEncoding = "$R1src"; 3204 let R2 = 0; 3205} 3206 3207class UnaryMemRRFc<string mnemonic, bits<16> opcode, 3208 RegisterOperand cls1, RegisterOperand cls2> 3209 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src), 3210 mnemonic#"\t$R1, $R2", []> { 3211 let Constraints = "$R1 = $R1src"; 3212 let DisableEncoding = "$R1src"; 3213 let M3 = 0; 3214} 3215 3216class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3217 RegisterOperand cls, ImmOpWithPattern imm> 3218 : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2), 3219 mnemonic#"\t$R1, $I2", 3220 [(set cls:$R1, (operator imm:$I2))]>; 3221 3222class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3223 RegisterOperand cls, ImmOpWithPattern imm> 3224 : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2), 3225 mnemonic#"\t$R1, $I2", 3226 [(set cls:$R1, (operator imm:$I2))]>; 3227 3228class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3229 RegisterOperand cls> 3230 : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2), 3231 mnemonic#"\t$R1, $RI2", 3232 [(set cls:$R1, (operator pcrel32:$RI2))]> { 3233 let mayLoad = 1; 3234 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 3235 // However, BDXs have two extra operands and are therefore 6 units more 3236 // complex. 3237 let AddedComplexity = 7; 3238} 3239 3240class CondUnaryRSY<string mnemonic, bits<16> opcode, 3241 SDPatternOperator operator, RegisterOperand cls, 3242 bits<5> bytes, AddressingMode mode = bdaddr20only> 3243 : InstRSYb<opcode, (outs cls:$R1), 3244 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), 3245 mnemonic#"$M3\t$R1, $BD2", 3246 [(set cls:$R1, 3247 (z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src, 3248 cond4:$valid, cond4:$M3))]> { 3249 let Constraints = "$R1 = $R1src"; 3250 let DisableEncoding = "$R1src"; 3251 let mayLoad = 1; 3252 let AccessBytes = bytes; 3253 let CCMaskLast = 1; 3254 let OpKey = mnemonic#"r"#cls; 3255 let OpType = "mem"; 3256 let MemKey = mnemonic#cls; 3257 let MemType = "target"; 3258} 3259 3260// Like CondUnaryRSY, but used for the raw assembly form. The condition-code 3261// mask is the third operand rather than being part of the mnemonic. 3262class AsmCondUnaryRSY<string mnemonic, bits<16> opcode, 3263 RegisterOperand cls, bits<5> bytes, 3264 AddressingMode mode = bdaddr20only> 3265 : InstRSYb<opcode, (outs cls:$R1), 3266 (ins cls:$R1src, (mode $B2, $D2):$BD2, imm32zx4:$M3), 3267 mnemonic#"\t$R1, $BD2, $M3", []> { 3268 let mayLoad = 1; 3269 let AccessBytes = bytes; 3270 let Constraints = "$R1 = $R1src"; 3271 let DisableEncoding = "$R1src"; 3272} 3273 3274// Like CondUnaryRSY, but with a fixed CC mask. 3275class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode, 3276 RegisterOperand cls, bits<5> bytes, 3277 AddressingMode mode = bdaddr20only> 3278 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2):$BD2), 3279 mnemonic#V.suffix#"\t$R1, $BD2", []> { 3280 let Constraints = "$R1 = $R1src"; 3281 let DisableEncoding = "$R1src"; 3282 let mayLoad = 1; 3283 let AccessBytes = bytes; 3284 let isAsmParserOnly = V.alternate; 3285 let AsmVariantName = V.asmvariant; 3286 let M3 = V.ccmask; 3287} 3288 3289multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode, 3290 SDPatternOperator operator, 3291 RegisterOperand cls, bits<5> bytes, 3292 AddressingMode mode = bdaddr20only> { 3293 let isCodeGenOnly = 1 in 3294 def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>; 3295 def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>; 3296} 3297 3298class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3299 RegisterOperand cls, bits<5> bytes, 3300 AddressingMode mode = bdxaddr12only> 3301 : InstRXa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2), 3302 mnemonic#"\t$R1, $XBD2", 3303 [(set cls:$R1, (operator mode:$XBD2))]> { 3304 let OpKey = mnemonic#"r"#cls; 3305 let OpType = "mem"; 3306 let mayLoad = 1; 3307 let AccessBytes = bytes; 3308} 3309 3310class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3311 RegisterOperand cls, bits<5> bytes> 3312 : InstRXE<opcode, (outs cls:$R1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2), 3313 mnemonic#"\t$R1, $XBD2", 3314 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> { 3315 let OpKey = mnemonic#"r"#cls; 3316 let OpType = "mem"; 3317 let mayLoad = 1; 3318 let AccessBytes = bytes; 3319 let M3 = 0; 3320} 3321 3322class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3323 RegisterOperand cls, bits<5> bytes, 3324 AddressingMode mode = bdxaddr20only> 3325 : InstRXYa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2), 3326 mnemonic#"\t$R1, $XBD2", 3327 [(set cls:$R1, (operator mode:$XBD2))]> { 3328 let OpKey = mnemonic#"r"#cls; 3329 let OpType = "mem"; 3330 let mayLoad = 1; 3331 let AccessBytes = bytes; 3332} 3333 3334multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 3335 SDPatternOperator operator, RegisterOperand cls, 3336 bits<5> bytes> { 3337 let DispKey = mnemonic # cls in { 3338 let DispSize = "12" in 3339 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 3340 let DispSize = "20" in 3341 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 3342 bdxaddr20pair>; 3343 } 3344} 3345 3346class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3347 TypedReg tr, ImmOpWithPattern imm, bits<4> type = 0> 3348 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2), 3349 mnemonic#"\t$V1, $I2", 3350 [(set (tr.vt tr.op:$V1), (operator (i32 timm:$I2)))]> { 3351 let M3 = type; 3352} 3353 3354class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, ImmOpWithPattern imm> 3355 : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3), 3356 mnemonic#"\t$V1, $I2, $M3", []>; 3357 3358class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3359 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0, 3360 bits<4> m5 = 0, string fp_mnemonic = ""> 3361 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2), 3362 mnemonic#"\t$V1, $V2", 3363 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]> { 3364 let M3 = type; 3365 let M4 = m4; 3366 let M5 = m5; 3367 let OpKey = fp_mnemonic#!subst("VR", "FP", !cast<string>(tr1.op)); 3368 let OpType = "reg"; 3369} 3370 3371class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0, 3372 bits<4> m5 = 0> 3373 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3), 3374 mnemonic#"\t$V1, $V2, $M3", []> { 3375 let M4 = m4; 3376 let M5 = m5; 3377} 3378 3379class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0> 3380 : InstVRRa<opcode, (outs VR128:$V1), 3381 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4), 3382 mnemonic#"\t$V1, $V2, $M3, $M4", []> { 3383 let M5 = m5; 3384} 3385 3386// Declare a pair of instructions, one which sets CC and one which doesn't. 3387// The CC-setting form ends with "S" and sets the low bit of M5. 3388// The form that does not set CC has an extra operand to optionally allow 3389// specifying arbitrary M5 values in assembler. 3390multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode, 3391 SDPatternOperator operator, 3392 SDPatternOperator operator_cc, 3393 TypedReg tr1, TypedReg tr2, bits<4> type> { 3394 let M3 = type, M4 = 0 in 3395 def "" : InstVRRa<opcode, (outs tr1.op:$V1), 3396 (ins tr2.op:$V2, imm32zx4:$M5), 3397 mnemonic#"\t$V1, $V2, $M5", []>; 3398 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))), 3399 (!cast<Instruction>(NAME) tr2.op:$V2, 0)>; 3400 def : InstAlias<mnemonic#"\t$V1, $V2", 3401 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>; 3402 let Defs = [CC] in 3403 def S : UnaryVRRa<mnemonic#"s", opcode, operator_cc, tr1, tr2, 3404 type, 0, 1>; 3405} 3406 3407multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> { 3408 let M4 = 0, Defs = [CC] in 3409 def "" : InstVRRa<opcode, (outs VR128:$V1), 3410 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5), 3411 mnemonic#"\t$V1, $V2, $M3, $M5", []>; 3412 def : InstAlias<mnemonic#"\t$V1, $V2, $M3", 3413 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, 3414 imm32zx4:$M3, 0)>; 3415} 3416 3417class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3418 TypedReg tr, bits<5> bytes, bits<4> type = 0> 3419 : InstVRX<opcode, (outs tr.op:$V1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2), 3420 mnemonic#"\t$V1, $XBD2", 3421 [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2))]> { 3422 let M3 = type; 3423 let mayLoad = 1; 3424 let AccessBytes = bytes; 3425} 3426 3427class UnaryVRXGeneric<string mnemonic, bits<16> opcode> 3428 : InstVRX<opcode, (outs VR128:$V1), 3429 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 3430 mnemonic#"\t$V1, $XBD2, $M3", []> { 3431 let mayLoad = 1; 3432} 3433 3434multiclass UnaryVRXAlign<string mnemonic, bits<16> opcode> { 3435 let mayLoad = 1, AccessBytes = 16 in { 3436 def Align : InstVRX<opcode, (outs VR128:$V1), 3437 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 3438 mnemonic#"\t$V1, $XBD2, $M3", []>; 3439 let M3 = 0 in 3440 def "" : InstVRX<opcode, (outs VR128:$V1), 3441 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2), 3442 mnemonic#"\t$V1, $XBD2", []>; 3443 } 3444} 3445 3446class SideEffectBinaryRX<string mnemonic, bits<8> opcode, 3447 RegisterOperand cls> 3448 : InstRXa<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 3449 mnemonic#"\t$R1, $XBD2", []>; 3450 3451class SideEffectBinaryRXY<string mnemonic, bits<16> opcode, 3452 RegisterOperand cls> 3453 : InstRXYa<opcode, (outs), (ins cls:$R1, (bdxaddr20only $B2, $D2, $X2):$XBD2), 3454 mnemonic#"\t$R1, $XBD2", []>; 3455 3456class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode, 3457 RegisterOperand cls> 3458 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2), 3459 mnemonic#"\t$R1, $RI2", []> { 3460 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 3461 // However, BDXs have two extra operands and are therefore 6 units more 3462 // complex. 3463 let AddedComplexity = 7; 3464} 3465 3466class SideEffectBinaryRRE<string mnemonic, bits<16> opcode, 3467 RegisterOperand cls1, RegisterOperand cls2> 3468 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2), 3469 mnemonic#"\t$R1, $R2", []>; 3470 3471class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode, 3472 RegisterOperand cls1, RegisterOperand cls2> 3473 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2), 3474 mnemonic#"\t$R1, $R2", []> { 3475 let R3 = 0; 3476 let M4 = 0; 3477} 3478 3479class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode, 3480 RegisterOperand cls1, RegisterOperand cls2> 3481 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2), 3482 mnemonic#"\t$R1, $R2", []> { 3483 let M3 = 0; 3484} 3485 3486class SideEffectBinaryIE<string mnemonic, bits<16> opcode, 3487 ImmOpWithPattern imm1, ImmOpWithPattern imm2> 3488 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2), 3489 mnemonic#"\t$I1, $I2", []>; 3490 3491class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm> 3492 : InstSI<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2), 3493 mnemonic#"\t$BD1, $I2", []>; 3494 3495class SideEffectBinarySIL<string mnemonic, bits<16> opcode, 3496 SDPatternOperator operator, ImmOpWithPattern imm> 3497 : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2), 3498 mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>; 3499 3500class SideEffectBinarySSa<string mnemonic, bits<8> opcode> 3501 : InstSSa<opcode, (outs), (ins (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1, 3502 (bdaddr12only $B2, $D2):$BD2), 3503 mnemonic#"\t$BDL1, $BD2", []>; 3504 3505class SideEffectBinarySSb<string mnemonic, bits<8> opcode> 3506 : InstSSb<opcode, 3507 (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1, 3508 (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2), 3509 mnemonic#"\t$BDL1, $BDL2", []>; 3510 3511class SideEffectBinarySSf<string mnemonic, bits<8> opcode> 3512 : InstSSf<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, 3513 (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2), 3514 mnemonic#"\t$BD1, $BDL2", []>; 3515 3516class SideEffectBinarySSE<string mnemonic, bits<16> opcode> 3517 : InstSSE<opcode, (outs), 3518 (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2), 3519 mnemonic#"\t$BD1, $BD2", []>; 3520 3521class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode, 3522 RegisterOperand cls1, RegisterOperand cls2> 3523 : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src), 3524 mnemonic#"\t$R1, $R2", []> { 3525 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 3526 let DisableEncoding = "$R1src, $R2src"; 3527} 3528 3529class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode, 3530 RegisterOperand cls1, RegisterOperand cls2> 3531 : InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src), 3532 mnemonic#"\t$R1, $R2", []> { 3533 let Constraints = "$R2 = $R2src"; 3534 let DisableEncoding = "$R2src"; 3535} 3536 3537class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode, 3538 RegisterOperand cls1, RegisterOperand cls2> 3539 : InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src), 3540 mnemonic#"\t$R1, $R2", []> { 3541 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 3542 let DisableEncoding = "$R1src, $R2src"; 3543} 3544 3545class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode, 3546 RegisterOperand cls1, RegisterOperand cls2> 3547 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src), 3548 mnemonic#"\t$R1, $R2", []> { 3549 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 3550 let DisableEncoding = "$R1src, $R2src"; 3551 let M3 = 0; 3552} 3553 3554class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3555 RegisterOperand cls1, RegisterOperand cls2> 3556 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 3557 mnemonic#"\t$R1, $R2", 3558 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 3559 let OpKey = mnemonic#cls1; 3560 let OpType = "reg"; 3561 let Constraints = "$R1 = $R1src"; 3562 let DisableEncoding = "$R1src"; 3563} 3564 3565class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3566 RegisterOperand cls1, RegisterOperand cls2> 3567 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 3568 mnemonic#"\t$R1, $R2", 3569 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 3570 let OpKey = mnemonic#cls1; 3571 let OpType = "reg"; 3572 let Constraints = "$R1 = $R1src"; 3573 let DisableEncoding = "$R1src"; 3574} 3575 3576class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3577 RegisterOperand cls1, RegisterOperand cls2> 3578 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2), 3579 mnemonic#"\t$R1, $R3, $R2", 3580 [(set cls1:$R1, (operator cls2:$R3, cls2:$R2))]> { 3581 let OpKey = mnemonic#cls; 3582 let OpType = "reg"; 3583} 3584 3585class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3586 RegisterOperand cls1, RegisterOperand cls2, 3587 RegisterOperand cls3> 3588 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3), 3589 mnemonic#"\t$R1, $R2, $R3", 3590 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> { 3591 let M4 = 0; 3592 let OpKey = mnemonic#cls1; 3593 let OpType = "reg"; 3594} 3595 3596 3597class UnaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3598 RegisterOperand cls1, RegisterOperand cls2> 3599 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls2:$R3), 3600 mnemonic#"\t$R1, $R2", 3601 [(set cls1:$R1, (operator cls2:$R2, cls2:$R3))]> { 3602 let R3 = R2; 3603 let M4 = 0; 3604 let OpKey = mnemonic#cls1; 3605 let OpType = "reg"; 3606} 3607 3608 3609multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 3610 SDPatternOperator operator, RegisterOperand cls1, 3611 RegisterOperand cls2> { 3612 let NumOpsKey = mnemonic in { 3613 let NumOpsValue = "3" in 3614 def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>, 3615 Requires<[FeatureDistinctOps]>; 3616 let NumOpsValue = "2" in 3617 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>; 3618 } 3619} 3620 3621multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2, 3622 SDPatternOperator operator, RegisterOperand cls1, 3623 RegisterOperand cls2> { 3624 let NumOpsKey = mnemonic in { 3625 let NumOpsValue = "3" in 3626 def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>, 3627 Requires<[FeatureDistinctOps]>; 3628 let NumOpsValue = "2" in 3629 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>; 3630 } 3631} 3632 3633class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3634 RegisterOperand cls1, RegisterOperand cls2, 3635 RegisterOperand cls3> 3636 : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3), 3637 mnemonic#"\t$R1, $R3, $R2", 3638 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> { 3639 let M4 = 0; 3640} 3641 3642class BinaryRRFc<string mnemonic, bits<16> opcode, 3643 RegisterOperand cls1, RegisterOperand cls2> 3644 : InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M3), 3645 mnemonic#"\t$R1, $R2, $M3", []>; 3646 3647class BinaryMemRRFc<string mnemonic, bits<16> opcode, 3648 RegisterOperand cls1, RegisterOperand cls2, ImmOpWithPattern imm> 3649 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3), 3650 mnemonic#"\t$R1, $R2, $M3", []> { 3651 let Constraints = "$R1 = $R1src"; 3652 let DisableEncoding = "$R1src"; 3653} 3654 3655multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode, 3656 RegisterOperand cls1, RegisterOperand cls2> { 3657 def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>; 3658 def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>; 3659} 3660 3661class BinaryRRFd<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3662 RegisterOperand cls2> 3663 : InstRRFd<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M4), 3664 mnemonic#"\t$R1, $R2, $M4", []>; 3665 3666class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3667 RegisterOperand cls2> 3668 : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2), 3669 mnemonic#"\t$R1, $M3, $R2", []> { 3670 let M4 = 0; 3671} 3672 3673class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3674 RegisterOperand cls2> 3675 : InstRRFc<opcode, (outs cls1:$R1), 3676 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), 3677 mnemonic#"$M3\t$R1, $R2", 3678 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src, 3679 cond4:$valid, cond4:$M3))]> { 3680 let Constraints = "$R1 = $R1src"; 3681 let DisableEncoding = "$R1src"; 3682 let CCMaskLast = 1; 3683 let NumOpsKey = !subst("loc", "sel", mnemonic); 3684 let NumOpsValue = "2"; 3685 let OpKey = mnemonic#cls1; 3686 let OpType = "reg"; 3687} 3688 3689// Like CondBinaryRRF, but used for the raw assembly form. The condition-code 3690// mask is the third operand rather than being part of the mnemonic. 3691class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3692 RegisterOperand cls2> 3693 : InstRRFc<opcode, (outs cls1:$R1), 3694 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3), 3695 mnemonic#"\t$R1, $R2, $M3", []> { 3696 let Constraints = "$R1 = $R1src"; 3697 let DisableEncoding = "$R1src"; 3698} 3699 3700// Like CondBinaryRRF, but with a fixed CC mask. 3701class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode, 3702 RegisterOperand cls1, RegisterOperand cls2> 3703 : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 3704 mnemonic#V.suffix#"\t$R1, $R2", []> { 3705 let Constraints = "$R1 = $R1src"; 3706 let DisableEncoding = "$R1src"; 3707 let isAsmParserOnly = V.alternate; 3708 let AsmVariantName = V.asmvariant; 3709 let M3 = V.ccmask; 3710} 3711 3712multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode, 3713 RegisterOperand cls1, RegisterOperand cls2> { 3714 let isCodeGenOnly = 1 in 3715 def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>; 3716 def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>; 3717} 3718 3719class CondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3720 RegisterOperand cls2, RegisterOperand cls3> 3721 : InstRRFa<opcode, (outs cls1:$R1), 3722 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4), 3723 mnemonic#"$M4\t$R1, $R2, $R3", 3724 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3, 3725 cond4:$valid, cond4:$M4))]> { 3726 let CCMaskLast = 1; 3727 let NumOpsKey = mnemonic; 3728 let NumOpsValue = "3"; 3729 let OpKey = mnemonic#cls1; 3730 let OpType = "reg"; 3731} 3732 3733// Like CondBinaryRRFa, but used for the raw assembly form. The condition-code 3734// mask is the third operand rather than being part of the mnemonic. 3735class AsmCondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3736 RegisterOperand cls2, RegisterOperand cls3> 3737 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2, imm32zx4:$M4), 3738 mnemonic#"\t$R1, $R2, $R3, $M4", []>; 3739 3740// Like CondBinaryRRFa, but with a fixed CC mask. 3741class FixedCondBinaryRRFa<CondVariant V, string mnemonic, bits<16> opcode, 3742 RegisterOperand cls1, RegisterOperand cls2, 3743 RegisterOperand cls3> 3744 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2), 3745 mnemonic#V.suffix#"\t$R1, $R2, $R3", []> { 3746 let isAsmParserOnly = V.alternate; 3747 let AsmVariantName = V.asmvariant; 3748 let M4 = V.ccmask; 3749} 3750 3751multiclass CondBinaryRRFaPair<string mnemonic, bits<16> opcode, 3752 RegisterOperand cls1, RegisterOperand cls2, 3753 RegisterOperand cls3> { 3754 let isCodeGenOnly = 1 in 3755 def "" : CondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 3756 def Asm : AsmCondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 3757} 3758 3759class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3760 RegisterOperand cls, ImmOpWithPattern imm> 3761 : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 3762 mnemonic#"\t$R1, $I2", 3763 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 3764 let Constraints = "$R1 = $R1src"; 3765 let DisableEncoding = "$R1src"; 3766} 3767 3768class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3769 RegisterOperand cls, ImmOpWithPattern imm> 3770 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2), 3771 mnemonic#"\t$R1, $R3, $I2", 3772 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; 3773 3774multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2, 3775 SDPatternOperator operator, RegisterOperand cls, 3776 ImmOpWithPattern imm> { 3777 let NumOpsKey = mnemonic in { 3778 let NumOpsValue = "3" in 3779 def K : BinaryRIE<mnemonic#"k", opcode2, operator, cls, imm>, 3780 Requires<[FeatureDistinctOps]>; 3781 let NumOpsValue = "2" in 3782 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>; 3783 } 3784} 3785 3786class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls, 3787 ImmOpWithPattern imm> 3788 : InstRIEg<opcode, (outs cls:$R1), 3789 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3), 3790 mnemonic#"$M3\t$R1, $I2", 3791 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src, 3792 cond4:$valid, cond4:$M3))]> { 3793 let Constraints = "$R1 = $R1src"; 3794 let DisableEncoding = "$R1src"; 3795 let CCMaskLast = 1; 3796} 3797 3798// Like CondBinaryRIE, but used for the raw assembly form. The condition-code 3799// mask is the third operand rather than being part of the mnemonic. 3800class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls, 3801 ImmOpWithPattern imm> 3802 : InstRIEg<opcode, (outs cls:$R1), 3803 (ins cls:$R1src, imm:$I2, imm32zx4:$M3), 3804 mnemonic#"\t$R1, $I2, $M3", []> { 3805 let Constraints = "$R1 = $R1src"; 3806 let DisableEncoding = "$R1src"; 3807} 3808 3809// Like CondBinaryRIE, but with a fixed CC mask. 3810class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode, 3811 RegisterOperand cls, ImmOpWithPattern imm> 3812 : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 3813 mnemonic#V.suffix#"\t$R1, $I2", []> { 3814 let Constraints = "$R1 = $R1src"; 3815 let DisableEncoding = "$R1src"; 3816 let isAsmParserOnly = V.alternate; 3817 let AsmVariantName = V.asmvariant; 3818 let M3 = V.ccmask; 3819} 3820 3821multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode, 3822 RegisterOperand cls, ImmOpWithPattern imm> { 3823 let isCodeGenOnly = 1 in 3824 def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>; 3825 def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>; 3826} 3827 3828class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3829 RegisterOperand cls, ImmOpWithPattern imm> 3830 : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 3831 mnemonic#"\t$R1, $I2", 3832 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 3833 let Constraints = "$R1 = $R1src"; 3834 let DisableEncoding = "$R1src"; 3835} 3836 3837class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3838 RegisterOperand cls> 3839 : InstRSa<opcode, (outs cls:$R1), 3840 (ins cls:$R1src, (shift12only $B2, $D2):$BD2), 3841 mnemonic#"\t$R1, $BD2", 3842 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> { 3843 let R3 = 0; 3844 let Constraints = "$R1 = $R1src"; 3845 let DisableEncoding = "$R1src"; 3846} 3847 3848class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3849 RegisterOperand cls> 3850 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (shift20only $B2, $D2):$BD2), 3851 mnemonic#"\t$R1, $R3, $BD2", 3852 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>; 3853 3854multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 3855 SDPatternOperator operator, RegisterOperand cls> { 3856 let NumOpsKey = mnemonic in { 3857 let NumOpsValue = "3" in 3858 def K : BinaryRSY<mnemonic#"k", opcode2, operator, cls>, 3859 Requires<[FeatureDistinctOps]>; 3860 let NumOpsValue = "2" in 3861 def "" : BinaryRS<mnemonic, opcode1, operator, cls>; 3862 } 3863} 3864 3865class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls> 3866 : InstRSLb<opcode, (outs cls:$R1), 3867 (ins (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3), 3868 mnemonic#"\t$R1, $BDL2, $M3", []> { 3869 let mayLoad = 1; 3870} 3871 3872class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3873 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 3874 AddressingMode mode = bdxaddr12only> 3875 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2), 3876 mnemonic#"\t$R1, $XBD2", 3877 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 3878 let OpKey = mnemonic#"r"#cls; 3879 let OpType = "mem"; 3880 let Constraints = "$R1 = $R1src"; 3881 let DisableEncoding = "$R1src"; 3882 let mayLoad = 1; 3883 let AccessBytes = bytes; 3884} 3885 3886class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3887 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 3888 : InstRXE<opcode, (outs cls:$R1), 3889 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2), 3890 mnemonic#"\t$R1, $XBD2", 3891 [(set cls:$R1, (operator cls:$R1src, 3892 (load bdxaddr12only:$XBD2)))]> { 3893 let OpKey = mnemonic#"r"#cls; 3894 let OpType = "mem"; 3895 let Constraints = "$R1 = $R1src"; 3896 let DisableEncoding = "$R1src"; 3897 let mayLoad = 1; 3898 let AccessBytes = bytes; 3899 let M3 = 0; 3900} 3901 3902class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3903 RegisterOperand cls1, RegisterOperand cls2, 3904 SDPatternOperator load, bits<5> bytes> 3905 : InstRXF<opcode, (outs cls1:$R1), 3906 (ins cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2), 3907 mnemonic#"\t$R1, $R3, $XBD2", 3908 [(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> { 3909 let OpKey = mnemonic#"r"#cls; 3910 let OpType = "mem"; 3911 let mayLoad = 1; 3912 let AccessBytes = bytes; 3913} 3914 3915class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3916 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 3917 AddressingMode mode = bdxaddr20only> 3918 : InstRXYa<opcode, (outs cls:$R1), 3919 (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2), 3920 mnemonic#"\t$R1, $XBD2", 3921 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 3922 let OpKey = mnemonic#"r"#cls; 3923 let OpType = "mem"; 3924 let Constraints = "$R1 = $R1src"; 3925 let DisableEncoding = "$R1src"; 3926 let mayLoad = 1; 3927 let AccessBytes = bytes; 3928} 3929 3930multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 3931 SDPatternOperator operator, RegisterOperand cls, 3932 SDPatternOperator load, bits<5> bytes> { 3933 let DispKey = mnemonic # cls in { 3934 let DispSize = "12" in 3935 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes, 3936 bdxaddr12pair>; 3937 let DispSize = "20" in 3938 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes, 3939 bdxaddr20pair>; 3940 } 3941} 3942 3943class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3944 Operand imm, AddressingMode mode = bdaddr12only> 3945 : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2), 3946 mnemonic#"\t$BD1, $I2", 3947 [(store (operator (z_load mode:$BD1), imm:$I2), mode:$BD1)]> { 3948 let mayLoad = 1; 3949 let mayStore = 1; 3950} 3951 3952class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3953 Operand imm, AddressingMode mode = bdaddr20only> 3954 : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2), 3955 mnemonic#"\t$BD1, $I2", 3956 [(store (operator (z_load mode:$BD1), imm:$I2), mode:$BD1)]> { 3957 let mayLoad = 1; 3958 let mayStore = 1; 3959} 3960 3961multiclass BinarySIPair<string mnemonic, bits<8> siOpcode, 3962 bits<16> siyOpcode, SDPatternOperator operator, 3963 Operand imm> { 3964 let DispKey = mnemonic # cls in { 3965 let DispSize = "12" in 3966 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>; 3967 let DispSize = "20" in 3968 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>; 3969 } 3970} 3971 3972class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls> 3973 : InstSSF<opcode, (outs cls:$R3), 3974 (ins (bdaddr12pair $B1, $D1):$BD1, (bdaddr12pair $B2, $D2):$BD2), 3975 mnemonic#"\t$R3, $BD1, $BD2", []> { 3976 let mayLoad = 1; 3977} 3978 3979class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3980 TypedReg tr, bits<4> type> 3981 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3), 3982 mnemonic#"\t$V1, $I2, $I3", 3983 [(set (tr.vt tr.op:$V1), (operator imm32zx8_timm:$I2, imm32zx8_timm:$I3))]> { 3984 let M4 = type; 3985} 3986 3987class BinaryVRIbGeneric<string mnemonic, bits<16> opcode> 3988 : InstVRIb<opcode, (outs VR128:$V1), 3989 (ins imm32zx8:$I2, imm32zx8:$I3, imm32zx4:$M4), 3990 mnemonic#"\t$V1, $I2, $I3, $M4", []>; 3991 3992class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3993 TypedReg tr1, TypedReg tr2, bits<4> type> 3994 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2), 3995 mnemonic#"\t$V1, $V3, $I2", 3996 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3), 3997 imm32zx16_timm:$I2))]> { 3998 let M4 = type; 3999} 4000 4001class BinaryVRIcGeneric<string mnemonic, bits<16> opcode> 4002 : InstVRIc<opcode, (outs VR128:$V1), 4003 (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4), 4004 mnemonic#"\t$V1, $V3, $I2, $M4", []>; 4005 4006class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4007 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5> 4008 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3), 4009 mnemonic#"\t$V1, $V2, $I3", 4010 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4011 imm32zx12_timm:$I3))]> { 4012 let M4 = type; 4013 let M5 = m5; 4014} 4015 4016class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode> 4017 : InstVRIe<opcode, (outs VR128:$V1), 4018 (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 4019 mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>; 4020 4021class BinaryVRIh<string mnemonic, bits<16> opcode> 4022 : InstVRIh<opcode, (outs VR128:$V1), 4023 (ins imm32zx16:$I2, imm32zx4:$I3), 4024 mnemonic#"\t$V1, $I2, $I3", []>; 4025 4026class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4027 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0> 4028 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5), 4029 mnemonic#"\t$V1, $V2, $M5", 4030 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4031 imm32zx12:$M5))]> { 4032 let M3 = type; 4033 let M4 = m4; 4034} 4035 4036class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode> 4037 : InstVRRa<opcode, (outs VR128:$V1), 4038 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5), 4039 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>; 4040 4041class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4042 TypedReg tr1, TypedReg tr2, bits<4> type = 0, 4043 bits<4> modifier = 0> 4044 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), 4045 mnemonic#"\t$V1, $V2, $V3", 4046 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4047 (tr2.vt tr2.op:$V3)))]> { 4048 let M4 = type; 4049 let M5 = modifier; 4050} 4051 4052class BinaryExtraVRRb<string mnemonic, bits<16> opcode, bits<4> type = 0> 4053 : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5), 4054 mnemonic#"\t$V1, $V2, $V3, $M5", []> { 4055 let M4 = type; 4056} 4057 4058class BinaryExtraVRRbGeneric<string mnemonic, bits<16> opcode> 4059 : InstVRRb<opcode, (outs VR128:$V1), 4060 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 4061 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>; 4062 4063// Declare a pair of instructions, one which sets CC and one which doesn't. 4064// The CC-setting form ends with "S" and sets the low bit of M5. 4065multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode, 4066 SDPatternOperator operator, 4067 SDPatternOperator operator_cc, TypedReg tr1, 4068 TypedReg tr2, bits<4> type, bits<4> modifier = 0> { 4069 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, 4070 !and (modifier, 14)>; 4071 let Defs = [CC] in 4072 def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 4073 !add (!and (modifier, 14), 1)>; 4074} 4075 4076class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode> 4077 : InstVRRb<opcode, (outs VR128:$V1), 4078 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 4079 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> { 4080 let Defs = [CC]; 4081} 4082 4083// Declare a pair of instructions, one which sets CC and one which doesn't. 4084// The CC-setting form ends with "S" and sets the low bit of M5. 4085// The form that does not set CC has an extra operand to optionally allow 4086// specifying arbitrary M5 values in assembler. 4087multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode, 4088 SDPatternOperator operator, 4089 SDPatternOperator operator_cc, 4090 TypedReg tr1, TypedReg tr2, bits<4> type> { 4091 let M4 = type in 4092 def "" : InstVRRb<opcode, (outs tr1.op:$V1), 4093 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5), 4094 mnemonic#"\t$V1, $V2, $V3, $M5", []>; 4095 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))), 4096 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>; 4097 def : InstAlias<mnemonic#"\t$V1, $V2, $V3", 4098 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 4099 tr2.op:$V3, 0)>; 4100 let Defs = [CC] in 4101 def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 1>; 4102} 4103 4104multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> { 4105 let Defs = [CC] in 4106 def "" : InstVRRb<opcode, (outs VR128:$V1), 4107 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 4108 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>; 4109 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4", 4110 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 4111 imm32zx4:$M4, 0)>; 4112} 4113 4114class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4115 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0, 4116 bits<4> m6 = 0, string fp_mnemonic = ""> 4117 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), 4118 mnemonic#"\t$V1, $V2, $V3", 4119 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4120 (tr2.vt tr2.op:$V3)))]> { 4121 let M4 = type; 4122 let M5 = m5; 4123 let M6 = m6; 4124 let OpKey = fp_mnemonic#"MemFold"#!subst("VR", "FP", !cast<string>(tr1.op)); 4125 let OpType = "reg"; 4126} 4127 4128class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0, 4129 bits<4> m6 = 0> 4130 : InstVRRc<opcode, (outs VR128:$V1), 4131 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4), 4132 mnemonic#"\t$V1, $V2, $V3, $M4", []> { 4133 let M5 = m5; 4134 let M6 = m6; 4135} 4136 4137class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0> 4138 : InstVRRc<opcode, (outs VR128:$V1), 4139 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 4140 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> { 4141 let M6 = m6; 4142} 4143 4144// Declare a pair of instructions, one which sets CC and one which doesn't. 4145// The CC-setting form ends with "S" and sets the low bit of M5. 4146multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode, 4147 SDPatternOperator operator, 4148 SDPatternOperator operator_cc, TypedReg tr1, 4149 TypedReg tr2, bits<4> type, bits<4> m5, 4150 bits<4> modifier = 0> { 4151 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, 4152 m5, !and (modifier, 14)>; 4153 let Defs = [CC] in 4154 def S : BinaryVRRc<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 4155 m5, !add (!and (modifier, 14), 1)>; 4156} 4157 4158class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode> 4159 : InstVRRc<opcode, (outs VR128:$V1), 4160 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 4161 imm32zx4:$M6), 4162 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>; 4163 4164class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4165 TypedReg tr> 4166 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3), 4167 mnemonic#"\t$V1, $R2, $R3", 4168 [(set (tr.vt tr.op:$V1), (operator GR64:$R2, GR64:$R3))]>; 4169 4170class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls> 4171 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3), 4172 mnemonic#"\t$R1, $V2, $M3", []> { 4173 let M4 = 0; 4174} 4175 4176class BinaryVRRk<string mnemonic, bits<16> opcode> 4177 : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3), 4178 mnemonic#"\t$V1, $V2, $M3", []>; 4179 4180class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4181 TypedReg tr1, TypedReg tr2, bits<4> type> 4182 : InstVRSa<opcode, (outs tr1.op:$V1), 4183 (ins tr2.op:$V3, (shift12only $B2, $D2):$BD2), 4184 mnemonic#"\t$V1, $V3, $BD2", 4185 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3), 4186 shift12only:$BD2))]> { 4187 let M4 = type; 4188} 4189 4190class BinaryVRSaGeneric<string mnemonic, bits<16> opcode> 4191 : InstVRSa<opcode, (outs VR128:$V1), 4192 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4:$M4), 4193 mnemonic#"\t$V1, $V3, $BD2, $M4", []>; 4194 4195class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4196 bits<5> bytes> 4197 : InstVRSb<opcode, (outs VR128:$V1), 4198 (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2), 4199 mnemonic#"\t$V1, $R3, $BD2", 4200 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> { 4201 let M4 = 0; 4202 let mayLoad = 1; 4203 let AccessBytes = bytes; 4204} 4205 4206class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4207 TypedReg tr, bits<4> type> 4208 : InstVRSc<opcode, (outs GR64:$R1), 4209 (ins tr.op:$V3, (shift12only $B2, $D2):$BD2), 4210 mnemonic#"\t$R1, $V3, $BD2", 4211 [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> { 4212 let M4 = type; 4213} 4214 4215class BinaryVRScGeneric<string mnemonic, bits<16> opcode> 4216 : InstVRSc<opcode, (outs GR64:$R1), 4217 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4: $M4), 4218 mnemonic#"\t$R1, $V3, $BD2, $M4", []>; 4219 4220class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4221 bits<5> bytes> 4222 : InstVRSd<opcode, (outs VR128:$V1), 4223 (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2), 4224 mnemonic#"\t$V1, $R3, $BD2", 4225 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> { 4226 let mayLoad = 1; 4227 let AccessBytes = bytes; 4228} 4229 4230class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4231 TypedReg tr, bits<5> bytes> 4232 : InstVRX<opcode, (outs VR128:$V1), 4233 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 4234 mnemonic#"\t$V1, $XBD2, $M3", 4235 [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2, 4236 imm32zx4_timm:$M3))]> { 4237 let mayLoad = 1; 4238 let AccessBytes = bytes; 4239} 4240 4241class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 4242 bits<5> bytes, AddressingMode mode = bdaddr12only> 4243 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4244 mnemonic#"\t$R1, $M3, $BD2", []> { 4245 let mayStore = 1; 4246 let AccessBytes = bytes; 4247} 4248 4249class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 4250 bits<5> bytes, AddressingMode mode = bdaddr20only> 4251 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4252 mnemonic#"\t$R1, $M3, $BD2", []> { 4253 let mayStore = 1; 4254 let AccessBytes = bytes; 4255} 4256 4257multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode, 4258 bits<16> rsyOpcode, RegisterOperand cls, 4259 bits<5> bytes> { 4260 let DispKey = mnemonic # cls in { 4261 let DispSize = "12" in 4262 def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>; 4263 let DispSize = "20" in 4264 def Y : StoreBinaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, 4265 bdaddr20pair>; 4266 } 4267} 4268 4269class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls> 4270 : InstRSLb<opcode, (outs), 4271 (ins cls:$R1, (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, 4272 imm32zx4:$M3), 4273 mnemonic#"\t$R1, $BDL2, $M3", []> { 4274 let mayStore = 1; 4275} 4276 4277class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4278 bits<5> bytes> 4279 : InstVSI<opcode, (outs VR128:$V1), 4280 (ins (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3), 4281 mnemonic#"\t$V1, $BD2, $I3", 4282 [(set VR128:$V1, (operator imm32zx8:$I3, bdaddr12only:$BD2))]> { 4283 let mayLoad = 1; 4284 let AccessBytes = bytes; 4285} 4286 4287class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, 4288 ImmOpWithPattern index> 4289 : InstVRV<opcode, (outs), 4290 (ins VR128:$V1, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3), 4291 mnemonic#"\t$V1, $VBD2, $M3", []> { 4292 let mayStore = 1; 4293 let AccessBytes = bytes; 4294} 4295 4296class StoreBinaryVRX<string mnemonic, bits<16> opcode, 4297 SDPatternOperator operator, TypedReg tr, bits<5> bytes, 4298 ImmOpWithPattern index> 4299 : InstVRX<opcode, (outs), 4300 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3), 4301 mnemonic#"\t$V1, $XBD2, $M3", 4302 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> { 4303 let mayStore = 1; 4304 let AccessBytes = bytes; 4305} 4306 4307class MemoryBinarySSd<string mnemonic, bits<8> opcode, 4308 RegisterOperand cls> 4309 : InstSSd<opcode, (outs), 4310 (ins (bdraddr12only $B1, $D1, $R1):$RBD1, 4311 (bdaddr12only $B2, $D2):$BD2, cls:$R3), 4312 mnemonic#"\t$RBD1, $BD2, $R3", []>; 4313 4314class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 4315 RegisterOperand cls1, RegisterOperand cls2> 4316 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2), 4317 mnemonic#"\t$R1, $R2", 4318 [(set CC, (operator cls1:$R1, cls2:$R2))]> { 4319 let OpKey = mnemonic#cls1; 4320 let OpType = "reg"; 4321 let isCompare = 1; 4322} 4323 4324class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4325 RegisterOperand cls1, RegisterOperand cls2> 4326 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2), 4327 mnemonic#"\t$R1, $R2", 4328 [(set CC, (operator cls1:$R1, cls2:$R2))]> { 4329 let OpKey = mnemonic#cls1; 4330 let OpType = "reg"; 4331 let isCompare = 1; 4332} 4333 4334class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 4335 RegisterOperand cls, ImmOpWithPattern imm> 4336 : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2), 4337 mnemonic#"\t$R1, $I2", 4338 [(set CC, (operator cls:$R1, imm:$I2))]> { 4339 let isCompare = 1; 4340} 4341 4342class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 4343 RegisterOperand cls, ImmOpWithPattern imm> 4344 : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2), 4345 mnemonic#"\t$R1, $I2", 4346 [(set CC, (operator cls:$R1, imm:$I2))]> { 4347 let isCompare = 1; 4348} 4349 4350class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 4351 RegisterOperand cls, SDPatternOperator load> 4352 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2), 4353 mnemonic#"\t$R1, $RI2", 4354 [(set CC, (operator cls:$R1, (load pcrel32:$RI2)))]> { 4355 let isCompare = 1; 4356 let mayLoad = 1; 4357 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 4358 // However, BDXs have two extra operands and are therefore 6 units more 4359 // complex. 4360 let AddedComplexity = 7; 4361} 4362 4363class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 4364 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 4365 AddressingMode mode = bdxaddr12only> 4366 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 4367 mnemonic#"\t$R1, $XBD2", 4368 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> { 4369 let OpKey = mnemonic#"r"#cls; 4370 let OpType = "mem"; 4371 let isCompare = 1; 4372 let mayLoad = 1; 4373 let AccessBytes = bytes; 4374} 4375 4376class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4377 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 4378 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 4379 mnemonic#"\t$R1, $XBD2", 4380 [(set CC, (operator cls:$R1, (load bdxaddr12only:$XBD2)))]> { 4381 let OpKey = mnemonic#"r"#cls; 4382 let OpType = "mem"; 4383 let isCompare = 1; 4384 let mayLoad = 1; 4385 let AccessBytes = bytes; 4386 let M3 = 0; 4387} 4388 4389class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4390 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 4391 AddressingMode mode = bdxaddr20only> 4392 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 4393 mnemonic#"\t$R1, $XBD2", 4394 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> { 4395 let OpKey = mnemonic#"r"#cls; 4396 let OpType = "mem"; 4397 let isCompare = 1; 4398 let mayLoad = 1; 4399 let AccessBytes = bytes; 4400} 4401 4402multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 4403 SDPatternOperator operator, RegisterOperand cls, 4404 SDPatternOperator load, bits<5> bytes> { 4405 let DispKey = mnemonic # cls in { 4406 let DispSize = "12" in 4407 def "" : CompareRX<mnemonic, rxOpcode, operator, cls, 4408 load, bytes, bdxaddr12pair>; 4409 let DispSize = "20" in 4410 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls, 4411 load, bytes, bdxaddr20pair>; 4412 } 4413} 4414 4415class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 4416 bits<5> bytes, AddressingMode mode = bdaddr12only> 4417 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4418 mnemonic#"\t$R1, $M3, $BD2", []> { 4419 let mayLoad = 1; 4420 let AccessBytes = bytes; 4421} 4422 4423class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 4424 bits<5> bytes, AddressingMode mode = bdaddr20only> 4425 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4426 mnemonic#"\t$R1, $M3, $BD2", []> { 4427 let mayLoad = 1; 4428 let AccessBytes = bytes; 4429} 4430 4431multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 4432 RegisterOperand cls, bits<5> bytes> { 4433 let DispKey = mnemonic # cls in { 4434 let DispSize = "12" in 4435 def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>; 4436 let DispSize = "20" in 4437 def Y : CompareRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>; 4438 } 4439} 4440 4441class CompareSSb<string mnemonic, bits<8> opcode> 4442 : InstSSb<opcode, 4443 (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1, 4444 (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2), 4445 mnemonic#"\t$BDL1, $BDL2", []> { 4446 let isCompare = 1; 4447 let mayLoad = 1; 4448} 4449 4450class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 4451 SDPatternOperator load, ImmOpWithPattern imm, 4452 AddressingMode mode = bdaddr12only> 4453 : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2), 4454 mnemonic#"\t$BD1, $I2", 4455 [(set CC, (operator (load mode:$BD1), imm:$I2))]> { 4456 let isCompare = 1; 4457 let mayLoad = 1; 4458} 4459 4460class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4461 SDPatternOperator load, ImmOpWithPattern imm> 4462 : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2), 4463 mnemonic#"\t$BD1, $I2", 4464 [(set CC, (operator (load bdaddr12only:$BD1), imm:$I2))]> { 4465 let isCompare = 1; 4466 let mayLoad = 1; 4467} 4468 4469class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4470 SDPatternOperator load, ImmOpWithPattern imm, 4471 AddressingMode mode = bdaddr20only> 4472 : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2), 4473 mnemonic#"\t$BD1, $I2", 4474 [(set CC, (operator (load mode:$BD1), imm:$I2))]> { 4475 let isCompare = 1; 4476 let mayLoad = 1; 4477} 4478 4479multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 4480 SDPatternOperator operator, SDPatternOperator load, 4481 ImmOpWithPattern imm> { 4482 let DispKey = mnemonic in { 4483 let DispSize = "12" in 4484 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>; 4485 let DispSize = "20" in 4486 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm, 4487 bdaddr20pair>; 4488 } 4489} 4490 4491class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4492 TypedReg tr, bits<4> type, string fp_mnemonic = ""> 4493 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2), 4494 mnemonic#"\t$V1, $V2", 4495 [(set CC, (operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2)))]> { 4496 let isCompare = 1; 4497 let M3 = type; 4498 let M4 = 0; 4499 let M5 = 0; 4500 let OpKey = fp_mnemonic#!subst("VR", "FP", !cast<string>(tr.op)); 4501 let OpType = "reg"; 4502} 4503 4504class CompareVRRaGeneric<string mnemonic, bits<16> opcode> 4505 : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3), 4506 mnemonic#"\t$V1, $V2, $M3", []> { 4507 let isCompare = 1; 4508 let M4 = 0; 4509 let M5 = 0; 4510} 4511 4512class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode> 4513 : InstVRRa<opcode, (outs), 4514 (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4), 4515 mnemonic#"\t$V1, $V2, $M3, $M4", []> { 4516 let isCompare = 1; 4517 let M5 = 0; 4518} 4519 4520class CompareVRRh<string mnemonic, bits<16> opcode> 4521 : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3), 4522 mnemonic#"\t$V1, $V2, $M3", []> { 4523 let isCompare = 1; 4524} 4525 4526class TestInherentS<string mnemonic, bits<16> opcode, 4527 SDPatternOperator operator> 4528 : InstS<opcode, (outs), (ins), mnemonic, [(set CC, (operator))]> { 4529 let B2 = 0; 4530 let D2 = 0; 4531} 4532 4533class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4534 RegisterOperand cls> 4535 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 4536 mnemonic#"\t$R1, $XBD2", 4537 [(set CC, (operator cls:$R1, bdxaddr12only:$XBD2))]> { 4538 let M3 = 0; 4539} 4540 4541class TestBinarySIL<string mnemonic, bits<16> opcode, 4542 SDPatternOperator operator, ImmOpWithPattern imm> 4543 : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2), 4544 mnemonic#"\t$BD1, $I2", 4545 [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>; 4546 4547class TestRSL<string mnemonic, bits<16> opcode> 4548 : InstRSLa<opcode, (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1), 4549 mnemonic#"\t$BDL1", []> { 4550 let mayLoad = 1; 4551} 4552 4553class TestVRRg<string mnemonic, bits<16> opcode> 4554 : InstVRRg<opcode, (outs), (ins VR128:$V1), 4555 mnemonic#"\t$V1", []> { 4556 let I2 = 0; 4557} 4558 4559class TestExtraVRRg<string mnemonic, bits<16> opcode> 4560 : InstVRRg<opcode, (outs), (ins VR128:$V1, imm32zx16:$I2), 4561 mnemonic#"\t$V1, $I2", []>; 4562 4563class TestExtraVRIl<string mnemonic, bits<16> opcode> 4564 : InstVRIl<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx16:$I3), 4565 mnemonic#"\t$V1, $V2, $I3", []>; 4566 4567class SideEffectTernarySSc<string mnemonic, bits<8> opcode> 4568 : InstSSc<opcode, (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1, 4569 (shift12only $B2, $D2):$BD2, imm32zx4:$I3), 4570 mnemonic#"\t$BDL1, $BD2, $I3", []>; 4571 4572class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode, 4573 RegisterOperand cls1, RegisterOperand cls2, 4574 RegisterOperand cls3> 4575 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3), 4576 mnemonic#"\t$R1, $R2, $R3", []> { 4577 let M4 = 0; 4578} 4579 4580class SideEffectTernaryMemMemRRFa<string mnemonic, bits<16> opcode, 4581 RegisterOperand cls1, RegisterOperand cls2, 4582 RegisterOperand cls3> 4583 : InstRRFa<opcode, (outs cls1:$R1, cls2:$R2), 4584 (ins cls1:$R1src, cls2:$R2src, cls3:$R3), 4585 mnemonic#"\t$R1, $R2, $R3", []> { 4586 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 4587 let DisableEncoding = "$R1src, $R2src"; 4588 let M4 = 0; 4589} 4590 4591class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode, 4592 RegisterOperand cls1, RegisterOperand cls2, 4593 RegisterOperand cls3> 4594 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3), 4595 mnemonic#"\t$R1, $R3, $R2", []> { 4596 let M4 = 0; 4597} 4598 4599class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode, 4600 RegisterOperand cls1, 4601 RegisterOperand cls2, 4602 RegisterOperand cls3> 4603 : InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3), 4604 (ins cls1:$R1src, cls2:$R2src, cls3:$R3src), 4605 mnemonic#"\t$R1, $R3, $R2", []> { 4606 let Constraints = "$R1 = $R1src, $R2 = $R2src, $R3 = $R3src"; 4607 let DisableEncoding = "$R1src, $R2src, $R3src"; 4608 let M4 = 0; 4609} 4610 4611class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode, 4612 RegisterOperand cls1, RegisterOperand cls2, 4613 ImmOpWithPattern imm> 4614 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3), 4615 mnemonic#"\t$R1, $R2, $M3", []>; 4616 4617multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode, 4618 RegisterOperand cls1, 4619 RegisterOperand cls2> { 4620 def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>; 4621 def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>; 4622} 4623 4624class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode, 4625 RegisterOperand cls1, RegisterOperand cls2, 4626 ImmOpWithPattern imm> 4627 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), 4628 (ins cls1:$R1src, cls2:$R2src, imm:$M3), 4629 mnemonic#"\t$R1, $R2, $M3", []> { 4630 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 4631 let DisableEncoding = "$R1src, $R2src"; 4632} 4633 4634multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode, 4635 RegisterOperand cls1, 4636 RegisterOperand cls2> { 4637 def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>; 4638 def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>; 4639} 4640 4641class SideEffectTernarySSF<string mnemonic, bits<12> opcode, 4642 RegisterOperand cls> 4643 : InstSSF<opcode, (outs), 4644 (ins (bdaddr12only $B1, $D1):$BD1, 4645 (bdaddr12only $B2, $D2):$BD2, cls:$R3), 4646 mnemonic#"\t$BD1, $BD2, $R3", []>; 4647 4648class TernaryRRFa<string mnemonic, bits<16> opcode, 4649 RegisterOperand cls1, RegisterOperand cls2, 4650 RegisterOperand cls3> 4651 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4), 4652 mnemonic#"\t$R1, $R2, $R3, $M4", []>; 4653 4654class TernaryRRFb<string mnemonic, bits<16> opcode, 4655 RegisterOperand cls1, RegisterOperand cls2, 4656 RegisterOperand cls3> 4657 : InstRRFb<opcode, (outs cls1:$R1, cls3:$R3), 4658 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M4), 4659 mnemonic#"\t$R1, $R3, $R2, $M4", []> { 4660 let Constraints = "$R1 = $R1src"; 4661 let DisableEncoding = "$R1src"; 4662} 4663 4664class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1, 4665 RegisterOperand cls2> 4666 : InstRRFe<opcode, (outs cls1:$R1), 4667 (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4), 4668 mnemonic#"\t$R1, $M3, $R2, $M4", []>; 4669 4670class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4671 RegisterOperand cls1, RegisterOperand cls2> 4672 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2), 4673 mnemonic#"\t$R1, $R3, $R2", 4674 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, cls2:$R2))]> { 4675 let OpKey = mnemonic#cls; 4676 let OpType = "reg"; 4677 let Constraints = "$R1 = $R1src"; 4678 let DisableEncoding = "$R1src"; 4679} 4680 4681class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 4682 bits<5> bytes, AddressingMode mode = bdaddr12only> 4683 : InstRSb<opcode, (outs cls:$R1), 4684 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4685 mnemonic#"\t$R1, $M3, $BD2", []> { 4686 4687 let Constraints = "$R1 = $R1src"; 4688 let DisableEncoding = "$R1src"; 4689 let mayLoad = 1; 4690 let AccessBytes = bytes; 4691} 4692 4693class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 4694 bits<5> bytes, AddressingMode mode = bdaddr20only> 4695 : InstRSYb<opcode, (outs cls:$R1), 4696 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4697 mnemonic#"\t$R1, $M3, $BD2", []> { 4698 4699 let Constraints = "$R1 = $R1src"; 4700 let DisableEncoding = "$R1src"; 4701 let mayLoad = 1; 4702 let AccessBytes = bytes; 4703} 4704 4705multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 4706 RegisterOperand cls, bits<5> bytes> { 4707 let DispKey = mnemonic # cls in { 4708 let DispSize = "12" in 4709 def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>; 4710 let DispSize = "20" in 4711 def Y : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>; 4712 } 4713} 4714 4715class SideEffectTernaryRS<string mnemonic, bits<8> opcode, 4716 RegisterOperand cls1, RegisterOperand cls2> 4717 : InstRSa<opcode, (outs), 4718 (ins cls1:$R1, cls2:$R3, (bdaddr12only $B2, $D2):$BD2), 4719 mnemonic#"\t$R1, $R3, $BD2", []>; 4720 4721class SideEffectTernaryRSY<string mnemonic, bits<16> opcode, 4722 RegisterOperand cls1, RegisterOperand cls2> 4723 : InstRSYa<opcode, (outs), 4724 (ins cls1:$R1, cls2:$R3, (bdaddr20only $B2, $D2):$BD2), 4725 mnemonic#"\t$R1, $R3, $BD2", []>; 4726 4727class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode, 4728 RegisterOperand cls1, RegisterOperand cls2> 4729 : InstRSa<opcode, (outs cls1:$R1, cls2:$R3), 4730 (ins cls1:$R1src, cls2:$R3src, (shift12only $B2, $D2):$BD2), 4731 mnemonic#"\t$R1, $R3, $BD2", []> { 4732 let Constraints = "$R1 = $R1src, $R3 = $R3src"; 4733 let DisableEncoding = "$R1src, $R3src"; 4734} 4735 4736class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode, 4737 RegisterOperand cls1, RegisterOperand cls2> 4738 : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3), 4739 (ins cls1:$R1src, cls2:$R3src, (shift20only $B2, $D2):$BD2), 4740 mnemonic#"\t$R1, $R3, $BD2", []> { 4741 let Constraints = "$R1 = $R1src, $R3 = $R3src"; 4742 let DisableEncoding = "$R1src, $R3src"; 4743} 4744 4745class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4746 RegisterOperand cls1, RegisterOperand cls2, 4747 SDPatternOperator load, bits<5> bytes> 4748 : InstRXF<opcode, (outs cls1:$R1), 4749 (ins cls2:$R1src, cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2), 4750 mnemonic#"\t$R1, $R3, $XBD2", 4751 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, 4752 (load bdxaddr12only:$XBD2)))]> { 4753 let OpKey = mnemonic#"r"#cls; 4754 let OpType = "mem"; 4755 let Constraints = "$R1 = $R1src"; 4756 let DisableEncoding = "$R1src"; 4757 let mayLoad = 1; 4758 let AccessBytes = bytes; 4759} 4760 4761class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4762 TypedReg tr1, TypedReg tr2, ImmOpWithPattern imm, ImmOpWithPattern index> 4763 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3), 4764 mnemonic#"\t$V1, $I2, $M3", 4765 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 4766 imm:$I2, index:$M3))]> { 4767 let Constraints = "$V1 = $V1src"; 4768 let DisableEncoding = "$V1src"; 4769} 4770 4771class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4772 TypedReg tr1, TypedReg tr2, bits<4> type> 4773 : InstVRId<opcode, (outs tr1.op:$V1), 4774 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), 4775 mnemonic#"\t$V1, $V2, $V3, $I4", 4776 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4777 (tr2.vt tr2.op:$V3), 4778 imm32zx8_timm:$I4))]> { 4779 let M5 = type; 4780} 4781 4782class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls> 4783 : InstVRIi<opcode, (outs VR128:$V1), 4784 (ins cls:$R2, imm32zx8:$I3, imm32zx4:$M4), 4785 mnemonic#"\t$V1, $R2, $I3, $M4", []>; 4786 4787class TernaryVRIj<string mnemonic, bits<16> opcode> 4788 : InstVRIj<opcode, (outs VR128:$V1), 4789 (ins VR128:$V2, imm32zx8:$I3, imm32zx4:$M4), 4790 mnemonic#"\t$V1, $V2, $I3, $M4", []>; 4791 4792class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4793 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or> 4794 : InstVRRa<opcode, (outs tr1.op:$V1), 4795 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5), 4796 mnemonic#"\t$V1, $V2, $M4, $M5", 4797 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4798 imm32zx4_timm:$M4, 4799 imm32zx4_timm:$M5))], 4800 m4or> { 4801 let M3 = type; 4802} 4803 4804class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode> 4805 : InstVRRa<opcode, (outs VR128:$V1), 4806 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5), 4807 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>; 4808 4809class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4810 TypedReg tr1, TypedReg tr2, bits<4> type, 4811 SDPatternOperator m5mask, bits<4> m5or> 4812 : InstVRRb<opcode, (outs tr1.op:$V1), 4813 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5), 4814 mnemonic#"\t$V1, $V2, $V3, $M5", 4815 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4816 (tr2.vt tr2.op:$V3), 4817 m5mask:$M5))], 4818 m5or> { 4819 let M4 = type; 4820} 4821 4822// Declare a pair of instructions, one which sets CC and one which doesn't. 4823// The CC-setting form ends with "S" and sets the low bit of M5. 4824// Also create aliases to make use of M5 operand optional in assembler. 4825multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode, 4826 SDPatternOperator operator, 4827 SDPatternOperator operator_cc, 4828 TypedReg tr1, TypedReg tr2, bits<4> type, 4829 bits<4> modifier = 0> { 4830 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, 4831 imm32zx4even_timm, !and (modifier, 14)>; 4832 def : InstAlias<mnemonic#"\t$V1, $V2, $V3", 4833 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 4834 tr2.op:$V3, 0)>; 4835 let Defs = [CC] in 4836 def S : TernaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 4837 imm32zx4even_timm, !add(!and (modifier, 14), 1)>; 4838 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3", 4839 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, 4840 tr2.op:$V3, 0)>; 4841} 4842 4843multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> { 4844 let Defs = [CC] in 4845 def "" : InstVRRb<opcode, (outs VR128:$V1), 4846 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 4847 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>; 4848 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4", 4849 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 4850 imm32zx4:$M4, 0)>; 4851} 4852 4853class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4854 TypedReg tr1, TypedReg tr2> 4855 : InstVRRc<opcode, (outs tr1.op:$V1), 4856 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4), 4857 mnemonic#"\t$V1, $V2, $V3, $M4", 4858 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4859 (tr2.vt tr2.op:$V3), 4860 imm32zx4_timm:$M4))]> { 4861 let M5 = 0; 4862 let M6 = 0; 4863} 4864 4865class TernaryVRRcInt<string mnemonic, bits<16> opcode, 4866 SDPatternOperator operator, TypedReg tr1, TypedReg tr2, 4867 bits<4> type = 0> 4868 : InstVRRc<opcode, (outs tr1.op:$V1), 4869 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5), 4870 mnemonic#"\t$V1, $V2, $V3, $M5", 4871 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4872 (tr2.vt tr2.op:$V3), 4873 imm32zx4_timm:$M5))]> { 4874 let M4 = type; 4875 let M6 = 0; 4876} 4877 4878class TernaryVRRcIntGeneric<string mnemonic, bits<16> opcode> 4879 : InstVRRc<opcode, (outs VR128:$V1), 4880 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 4881 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> { 4882 let M6 = 0; 4883} 4884 4885class TernaryVRRcFloat<string mnemonic, bits<16> opcode, 4886 SDPatternOperator operator, TypedReg tr1, TypedReg tr2, 4887 bits<4> type = 0, bits<4> m5 = 0> 4888 : InstVRRc<opcode, (outs tr1.op:$V1), 4889 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M6), 4890 mnemonic#"\t$V1, $V2, $V3, $M6", 4891 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4892 (tr2.vt tr2.op:$V3), 4893 imm32zx4_timm:$M6))]> { 4894 let M4 = type; 4895 let M5 = m5; 4896} 4897 4898class TernaryVRRcFloatGeneric<string mnemonic, bits<16> opcode> 4899 : InstVRRc<opcode, (outs VR128:$V1), 4900 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 4901 imm32zx4:$M6), 4902 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>; 4903 4904class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4905 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m6 = 0> 4906 : InstVRRd<opcode, (outs tr1.op:$V1), 4907 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), 4908 mnemonic#"\t$V1, $V2, $V3, $V4", 4909 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4910 (tr2.vt tr2.op:$V3), 4911 (tr1.vt tr1.op:$V4)))]> { 4912 let M5 = type; 4913 let M6 = m6; 4914} 4915 4916class TernaryVRRdGeneric<string mnemonic, bits<16> opcode> 4917 : InstVRRd<opcode, (outs VR128:$V1), 4918 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5), 4919 mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> { 4920 let M6 = 0; 4921} 4922 4923// Ternary operation where the assembler mnemonic has an extra operand to 4924// optionally allow specifying arbitrary M6 values. 4925multiclass TernaryExtraVRRd<string mnemonic, bits<16> opcode, 4926 SDPatternOperator operator, 4927 TypedReg tr1, TypedReg tr2, bits<4> type> { 4928 let M5 = type, Defs = [CC] in 4929 def "" : InstVRRd<opcode, (outs tr1.op:$V1), 4930 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, imm32zx4:$M6), 4931 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", []>; 4932 def : Pat<(operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3), 4933 (tr1.vt tr1.op:$V4)), 4934 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, 0)>; 4935 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4", 4936 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 4937 tr2.op:$V3, tr1.op:$V4, 0)>; 4938} 4939 4940multiclass TernaryExtraVRRdGeneric<string mnemonic, bits<16> opcode> { 4941 let Defs = [CC] in 4942 def "" : InstVRRd<opcode, (outs VR128:$V1), 4943 (ins VR128:$V2, VR128:$V3, VR128:$V4, 4944 imm32zx4:$M5, imm32zx4:$M6), 4945 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>; 4946 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5", 4947 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 4948 VR128:$V4, imm32zx4:$M5, 0)>; 4949} 4950 4951class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4952 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0, 4953 string fp_mnemonic = ""> 4954 : InstVRRe<opcode, (outs tr1.op:$V1), 4955 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), 4956 mnemonic#"\t$V1, $V2, $V3, $V4", 4957 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4958 (tr2.vt tr2.op:$V3), 4959 (tr1.vt tr1.op:$V4)))]> { 4960 let M5 = m5; 4961 let M6 = type; 4962 let OpKey = fp_mnemonic#"MemFold"#!subst("VR", "FP", !cast<string>(tr1.op)); 4963 let OpType = "reg"; 4964} 4965 4966class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode> 4967 : InstVRRe<opcode, (outs VR128:$V1), 4968 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6), 4969 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>; 4970 4971class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4972 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type> 4973 : InstVRSb<opcode, (outs tr1.op:$V1), 4974 (ins tr2.op:$V1src, cls:$R3, (shift12only $B2, $D2):$BD2), 4975 mnemonic#"\t$V1, $R3, $BD2", 4976 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 4977 cls:$R3, 4978 shift12only:$BD2))]> { 4979 let Constraints = "$V1 = $V1src"; 4980 let DisableEncoding = "$V1src"; 4981 let M4 = type; 4982} 4983 4984class TernaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls> 4985 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, 4986 imm32zx4:$M3, imm32zx4:$M4), 4987 mnemonic#"\t$R1, $V2, $M3, $M4", []>; 4988 4989class TernaryVRRj<string mnemonic, bits<16> opcode> 4990 : InstVRRj<opcode, (outs VR128:$V1), (ins VR128:$V2, 4991 VR128:$V3, imm32zx4:$M4), 4992 mnemonic#"\t$V1, $V2, $V3, $M4", []>; 4993 4994class TernaryVRSbGeneric<string mnemonic, bits<16> opcode> 4995 : InstVRSb<opcode, (outs VR128:$V1), 4996 (ins VR128:$V1src, GR64:$R3, (shift12only $B2, $D2):$BD2, 4997 imm32zx4:$M4), 4998 mnemonic#"\t$V1, $R3, $BD2, $M4", []> { 4999 let Constraints = "$V1 = $V1src"; 5000 let DisableEncoding = "$V1src"; 5001} 5002 5003class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, 5004 ImmOpWithPattern index> 5005 : InstVRV<opcode, (outs VR128:$V1), 5006 (ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3), 5007 mnemonic#"\t$V1, $VBD2, $M3", []> { 5008 let Constraints = "$V1 = $V1src"; 5009 let DisableEncoding = "$V1src"; 5010 let mayLoad = 1; 5011 let AccessBytes = bytes; 5012} 5013 5014class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 5015 TypedReg tr1, TypedReg tr2, bits<5> bytes, ImmOpWithPattern index> 5016 : InstVRX<opcode, (outs tr1.op:$V1), 5017 (ins tr2.op:$V1src, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3), 5018 mnemonic#"\t$V1, $XBD2, $M3", 5019 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 5020 bdxaddr12only:$XBD2, 5021 index:$M3))]> { 5022 let Constraints = "$V1 = $V1src"; 5023 let DisableEncoding = "$V1src"; 5024 let mayLoad = 1; 5025 let AccessBytes = bytes; 5026} 5027 5028class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, 5029 TypedReg tr1, TypedReg tr2, bits<4> type> 5030 : InstVRId<opcode, (outs tr1.op:$V1), 5031 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), 5032 mnemonic#"\t$V1, $V2, $V3, $I4", 5033 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 5034 (tr2.vt tr2.op:$V2), 5035 (tr2.vt tr2.op:$V3), 5036 imm32zx8_timm:$I4))]> { 5037 let Constraints = "$V1 = $V1src"; 5038 let DisableEncoding = "$V1src"; 5039 let M5 = type; 5040} 5041 5042class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode> 5043 : InstVRId<opcode, (outs VR128:$V1), 5044 (ins VR128:$V1src, VR128:$V2, VR128:$V3, 5045 imm32zx8:$I4, imm32zx4:$M5), 5046 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> { 5047 let Constraints = "$V1 = $V1src"; 5048 let DisableEncoding = "$V1src"; 5049} 5050 5051class QuaternaryVRIf<string mnemonic, bits<16> opcode> 5052 : InstVRIf<opcode, (outs VR128:$V1), 5053 (ins VR128:$V2, VR128:$V3, 5054 imm32zx8:$I4, imm32zx4:$M5), 5055 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []>; 5056 5057class QuaternaryVRIg<string mnemonic, bits<16> opcode> 5058 : InstVRIg<opcode, (outs VR128:$V1), 5059 (ins VR128:$V2, imm32zx8:$I3, 5060 imm32zx8:$I4, imm32zx4:$M5), 5061 mnemonic#"\t$V1, $V2, $I3, $I4, $M5", []>; 5062 5063class QuaternaryVRIk<string mnemonic, bits<16> opcode, 5064 SDPatternOperator operator, TypedReg tr> 5065 : InstVRIk<opcode, (outs VR128:$V1), 5066 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx8:$I5), 5067 mnemonic#"\t$V1, $V2, $V3, $V4, $I5", 5068 [(set (tr.vt tr.op:$V1), (operator (tr.vt tr.op:$V2), 5069 (tr.vt tr.op:$V3), 5070 (tr.vt tr.op:$V4), 5071 imm32zx8_timm:$I5))]>; 5072 5073class QuaternaryVRRd<string mnemonic, bits<16> opcode, 5074 SDPatternOperator operator, TypedReg tr1, TypedReg tr2, 5075 TypedReg tr3, TypedReg tr4, bits<4> type, 5076 SDPatternOperator m6mask = imm32zx4_timm, bits<4> m6or = 0> 5077 : InstVRRd<opcode, (outs tr1.op:$V1), 5078 (ins tr2.op:$V2, tr3.op:$V3, tr4.op:$V4, m6mask:$M6), 5079 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", 5080 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 5081 (tr3.vt tr3.op:$V3), 5082 (tr4.vt tr4.op:$V4), 5083 m6mask:$M6))], 5084 m6or> { 5085 let M5 = type; 5086} 5087 5088class QuaternaryVRRdGeneric<string mnemonic, bits<16> opcode> 5089 : InstVRRd<opcode, (outs VR128:$V1), 5090 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6), 5091 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>; 5092 5093// Declare a pair of instructions, one which sets CC and one which doesn't. 5094// The CC-setting form ends with "S" and sets the low bit of M6. 5095// Also create aliases to make use of M6 operand optional in assembler. 5096multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode, 5097 SDPatternOperator operator, 5098 SDPatternOperator operator_cc, 5099 TypedReg tr1, TypedReg tr2, bits<4> type, 5100 bits<4> modifier = 0> { 5101 def "" : QuaternaryVRRd<mnemonic, opcode, operator, 5102 tr1, tr2, tr2, tr2, type, 5103 imm32zx4even_timm, !and (modifier, 14)>; 5104 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4", 5105 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 5106 tr2.op:$V3, tr2.op:$V4, 0)>; 5107 let Defs = [CC] in 5108 def S : QuaternaryVRRd<mnemonic#"s", opcode, operator_cc, 5109 tr1, tr2, tr2, tr2, type, 5110 imm32zx4even_timm, !add (!and (modifier, 14), 1)>; 5111 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4", 5112 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, 5113 tr2.op:$V3, tr2.op:$V4, 0)>; 5114} 5115 5116multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> { 5117 let Defs = [CC] in 5118 def "" : QuaternaryVRRdGeneric<mnemonic, opcode>; 5119 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5", 5120 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 5121 VR128:$V4, imm32zx4_timm:$M5, 0)>; 5122} 5123 5124class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode, 5125 RegisterOperand cls1, RegisterOperand cls2, 5126 RegisterOperand cls3> 5127 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4), 5128 mnemonic#"\t$R1, $R2, $R3, $M4", []>; 5129 5130multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode, 5131 RegisterOperand cls1, 5132 RegisterOperand cls2, 5133 RegisterOperand cls3> { 5134 def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 5135 def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 5136 def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>; 5137} 5138 5139class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode, 5140 RegisterOperand cls1, RegisterOperand cls2, 5141 RegisterOperand cls3> 5142 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4), 5143 mnemonic#"\t$R1, $R3, $R2, $M4", []>; 5144 5145multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode, 5146 RegisterOperand cls1, 5147 RegisterOperand cls2, 5148 RegisterOperand cls3> { 5149 def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>; 5150 def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>; 5151} 5152 5153class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode, 5154 RegisterOperand cls> 5155 : InstSSe<opcode, (outs), 5156 (ins cls:$R1, (bdaddr12only $B2, $D2):$BD2, cls:$R3, 5157 (bdaddr12only $B4, $D4):$BD4), 5158 mnemonic#"\t$R1, $BD2, $R3, $BD4", []>; 5159 5160class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 5161 RegisterOperand cls, AddressingMode mode = bdaddr20only> 5162 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (mode $B2, $D2):$BD2), 5163 mnemonic#"\t$R1, $R3, $BD2", 5164 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> { 5165 let mayLoad = 1; 5166 let mayStore = 1; 5167} 5168 5169class CmpSwapRRE<string mnemonic, bits<16> opcode, 5170 RegisterOperand cls1, RegisterOperand cls2> 5171 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 5172 mnemonic#"\t$R1, $R2", []> { 5173 let Constraints = "$R1 = $R1src"; 5174 let DisableEncoding = "$R1src"; 5175 let mayLoad = 1; 5176 let mayStore = 1; 5177} 5178 5179class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 5180 RegisterOperand cls, AddressingMode mode = bdaddr12only> 5181 : InstRSa<opcode, (outs cls:$R1), 5182 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2), 5183 mnemonic#"\t$R1, $R3, $BD2", 5184 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 5185 let Constraints = "$R1 = $R1src"; 5186 let DisableEncoding = "$R1src"; 5187 let mayLoad = 1; 5188 let mayStore = 1; 5189} 5190 5191class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 5192 RegisterOperand cls, AddressingMode mode = bdaddr20only> 5193 : InstRSYa<opcode, (outs cls:$R1), 5194 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2), 5195 mnemonic#"\t$R1, $R3, $BD2", 5196 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 5197 let Constraints = "$R1 = $R1src"; 5198 let DisableEncoding = "$R1src"; 5199 let mayLoad = 1; 5200 let mayStore = 1; 5201} 5202 5203multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 5204 SDPatternOperator operator, RegisterOperand cls> { 5205 let DispKey = mnemonic # cls in { 5206 let DispSize = "12" in 5207 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>; 5208 let DispSize = "20" in 5209 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>; 5210 } 5211} 5212 5213class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1, 5214 RegisterOperand cls2, bits<8> I3Or = 0, bits<8> I4Or = 0> 5215 : InstRIEf<opcode, (outs cls1:$R1), 5216 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 5217 imm32zx8:$I5), 5218 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", [], I3Or, I4Or> { 5219 let Constraints = "$R1 = $R1src"; 5220 let DisableEncoding = "$R1src"; 5221} 5222 5223class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator> 5224 : InstRXYb<opcode, (outs), 5225 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2), 5226 mnemonic#"\t$M1, $XBD2", 5227 [(operator imm32zx4_timm:$M1, bdxaddr20only:$XBD2)]>; 5228 5229class PrefetchRILPC<string mnemonic, bits<12> opcode, 5230 SDPatternOperator operator> 5231 : InstRILc<opcode, (outs), (ins imm32zx4_timm:$M1, pcrel32:$RI2), 5232 mnemonic#"\t$M1, $RI2", 5233 [(operator imm32zx4_timm:$M1, pcrel32:$RI2)]> { 5234 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 5235 // However, BDXs have two extra operands and are therefore 6 units more 5236 // complex. 5237 let AddedComplexity = 7; 5238} 5239 5240class BranchPreloadSMI<string mnemonic, bits<8> opcode> 5241 : InstSMI<opcode, (outs), 5242 (ins imm32zx4:$M1, brtarget16bpp:$RI2, 5243 (bdaddr12only $B3, $D3):$BD3), 5244 mnemonic#"\t$M1, $RI2, $BD3", []>; 5245 5246class BranchPreloadMII<string mnemonic, bits<8> opcode> 5247 : InstMII<opcode, (outs), 5248 (ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3), 5249 mnemonic#"\t$M1, $RI2, $RI3", []>; 5250 5251//===----------------------------------------------------------------------===// 5252// Pseudo instructions 5253//===----------------------------------------------------------------------===// 5254// 5255// Convenience instructions that get lowered to real instructions 5256// by either SystemZTargetLowering::EmitInstrWithCustomInserter() 5257// or SystemZInstrInfo::expandPostRAPseudo(). 5258// 5259//===----------------------------------------------------------------------===// 5260 5261class Pseudo<dag outs, dag ins, list<dag> pattern> 5262 : InstSystemZ<0, outs, ins, "", pattern> { 5263 let isPseudo = 1; 5264 let isCodeGenOnly = 1; 5265} 5266 5267// Like UnaryRI, but expanded after RA depending on the choice of register. 5268class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls, 5269 ImmOpWithPattern imm> 5270 : Pseudo<(outs cls:$R1), (ins imm:$I2), 5271 [(set cls:$R1, (operator imm:$I2))]>; 5272 5273// Like UnaryRXY, but expanded after RA depending on the choice of register. 5274class UnaryRXYPseudo<string key, SDPatternOperator operator, 5275 RegisterOperand cls, bits<5> bytes, 5276 AddressingMode mode = bdxaddr20only> 5277 : Pseudo<(outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2), 5278 [(set cls:$R1, (operator mode:$XBD2))]> { 5279 let OpKey = key#"r"#cls; 5280 let OpType = "mem"; 5281 let mayLoad = 1; 5282 let Has20BitOffset = 1; 5283 let HasIndex = 1; 5284 let AccessBytes = bytes; 5285} 5286 5287// Like UnaryRR, but expanded after RA depending on the choice of registers. 5288class UnaryRRPseudo<string key, SDPatternOperator operator, 5289 RegisterOperand cls1, RegisterOperand cls2> 5290 : Pseudo<(outs cls1:$R1), (ins cls2:$R2), 5291 [(set cls1:$R1, (operator cls2:$R2))]> { 5292 let OpKey = key#cls1; 5293 let OpType = "reg"; 5294} 5295 5296// Like BinaryRI, but expanded after RA depending on the choice of register. 5297class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls, 5298 ImmOpWithPattern imm> 5299 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2), 5300 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 5301 let Constraints = "$R1 = $R1src"; 5302} 5303 5304// Like BinaryRIE, but expanded after RA depending on the choice of register. 5305class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls, 5306 ImmOpWithPattern imm> 5307 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2), 5308 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; 5309 5310// Like BinaryRIAndK, but expanded after RA depending on the choice of register. 5311multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator, 5312 RegisterOperand cls, ImmOpWithPattern imm> { 5313 let NumOpsKey = key in { 5314 let NumOpsValue = "3" in 5315 def K : BinaryRIEPseudo<operator, cls, imm>, 5316 Requires<[FeatureHighWord, FeatureDistinctOps]>; 5317 let NumOpsValue = "2" in 5318 def "" : BinaryRIPseudo<operator, cls, imm>, 5319 Requires<[FeatureHighWord]>; 5320 } 5321} 5322 5323// A pseudo that is used during register allocation when folding a memory 5324// operand. The 3-address register instruction with a spilled source cannot 5325// be converted directly to a target 2-address reg/mem instruction. 5326// Mapping: <INSN>R -> MemFoldPseudo -> <INSN> 5327class MemFoldPseudo<string mnemonic, RegisterOperand cls, bits<5> bytes, 5328 AddressingMode mode> 5329 : Pseudo<(outs cls:$R1), (ins cls:$R2, (mode $B2, $D2, $X2):$XBD2), []> { 5330 let OpKey = !subst("mscrk", "msrkc", 5331 !subst("msgcrk", "msgrkc", 5332 mnemonic#"rk"#cls)); 5333 let OpType = "mem"; 5334 let MemKey = mnemonic#cls; 5335 let MemType = "pseudo"; 5336 let mayLoad = 1; 5337 let AccessBytes = bytes; 5338 let HasIndex = 1; 5339 let hasNoSchedulingInfo = 1; 5340} 5341 5342// Same as MemFoldPseudo but for mapping a W... vector instruction 5343class MemFoldPseudo_FP<string mnemonic, RegisterOperand cls, bits<5> bytes, 5344 AddressingMode mode> 5345 : MemFoldPseudo<mnemonic, cls, bytes, mode> { 5346 let OpKey = mnemonic#"r"#"MemFold"#cls; 5347} 5348 5349class MemFoldPseudo_FPTern<string mnemonic, RegisterOperand cls, bits<5> bytes, 5350 AddressingMode mode> 5351 : Pseudo<(outs cls:$R1), 5352 (ins cls:$R2, cls:$R3, (mode $B2, $D2, $X2):$XBD2), []> { 5353 let OpKey = mnemonic#"r"#"MemFold"#cls; 5354 let OpType = "mem"; 5355 let MemKey = mnemonic#cls; 5356 let MemType = "pseudo"; 5357 let mayLoad = 1; 5358 let AccessBytes = bytes; 5359 let HasIndex = 1; 5360 let hasNoSchedulingInfo = 1; 5361} 5362 5363// Same as MemFoldPseudo but for Load On Condition with CC operands. 5364class MemFoldPseudo_CondMove<string mnemonic, RegisterOperand cls, bits<5> bytes, 5365 AddressingMode mode> 5366 : Pseudo<(outs cls:$R1), 5367 (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> { 5368 let OpKey = !subst("loc", "sel", mnemonic)#"r"#cls; 5369 let OpType = "mem"; 5370 let MemKey = mnemonic#cls; 5371 let MemType = "pseudo"; 5372 let mayLoad = 1; 5373 let AccessBytes = bytes; 5374 let hasNoSchedulingInfo = 1; 5375} 5376 5377// Like CompareRI, but expanded after RA depending on the choice of register. 5378class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls, 5379 ImmOpWithPattern imm> 5380 : Pseudo<(outs), (ins cls:$R1, imm:$I2), 5381 [(set CC, (operator cls:$R1, imm:$I2))]> { 5382 let isCompare = 1; 5383} 5384 5385// Like CompareRXY, but expanded after RA depending on the choice of register. 5386class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls, 5387 SDPatternOperator load, bits<5> bytes, 5388 AddressingMode mode = bdxaddr20only> 5389 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 5390 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> { 5391 let mayLoad = 1; 5392 let Has20BitOffset = 1; 5393 let HasIndex = 1; 5394 let AccessBytes = bytes; 5395} 5396 5397// Like TestBinarySIL, but expanded later. 5398class TestBinarySILPseudo<SDPatternOperator operator, ImmOpWithPattern imm> 5399 : Pseudo<(outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2), 5400 [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>; 5401 5402// Like CondBinaryRRF, but expanded after RA depending on the choice of 5403// register. 5404class CondBinaryRRFPseudo<string mnemonic, RegisterOperand cls1, 5405 RegisterOperand cls2> 5406 : Pseudo<(outs cls1:$R1), 5407 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), 5408 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src, 5409 cond4:$valid, cond4:$M3))]> { 5410 let Constraints = "$R1 = $R1src"; 5411 let DisableEncoding = "$R1src"; 5412 let CCMaskLast = 1; 5413 let NumOpsKey = !subst("loc", "sel", mnemonic); 5414 let NumOpsValue = "2"; 5415 let OpKey = mnemonic#cls1; 5416 let OpType = "reg"; 5417} 5418 5419// Like CondBinaryRRFa, but expanded after RA depending on the choice of 5420// register. 5421class CondBinaryRRFaPseudo<string mnemonic, RegisterOperand cls1, 5422 RegisterOperand cls2, RegisterOperand cls3> 5423 : Pseudo<(outs cls1:$R1), 5424 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4), 5425 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3, 5426 cond4:$valid, cond4:$M4))]> { 5427 let CCMaskLast = 1; 5428 let NumOpsKey = mnemonic; 5429 let NumOpsValue = "3"; 5430 let OpKey = mnemonic#cls1; 5431 let OpType = "reg"; 5432} 5433 5434// Like CondBinaryRIE, but expanded after RA depending on the choice of 5435// register. 5436class CondBinaryRIEPseudo<RegisterOperand cls, ImmOpWithPattern imm> 5437 : Pseudo<(outs cls:$R1), 5438 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3), 5439 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src, 5440 cond4:$valid, cond4:$M3))]> { 5441 let Constraints = "$R1 = $R1src"; 5442 let DisableEncoding = "$R1src"; 5443 let CCMaskLast = 1; 5444} 5445 5446// Like CondUnaryRSY, but expanded after RA depending on the choice of 5447// register. 5448class CondUnaryRSYPseudo<string mnemonic, SDPatternOperator operator, 5449 RegisterOperand cls, bits<5> bytes, 5450 AddressingMode mode = bdaddr20only> 5451 : Pseudo<(outs cls:$R1), 5452 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), 5453 [(set cls:$R1, 5454 (z_select_ccmask (operator mode:$BD2), cls:$R1src, 5455 cond4:$valid, cond4:$R3))]> { 5456 let Constraints = "$R1 = $R1src"; 5457 let DisableEncoding = "$R1src"; 5458 let mayLoad = 1; 5459 let AccessBytes = bytes; 5460 let CCMaskLast = 1; 5461 let OpKey = mnemonic#"r"#cls; 5462 let OpType = "mem"; 5463 let MemKey = mnemonic#cls; 5464 let MemType = "target"; 5465} 5466 5467// Like CondStoreRSY, but expanded after RA depending on the choice of 5468// register. 5469class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes, 5470 AddressingMode mode = bdaddr20only> 5471 : Pseudo<(outs), 5472 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), []> { 5473 let mayStore = 1; 5474 let AccessBytes = bytes; 5475 let CCMaskLast = 1; 5476} 5477 5478// Like StoreRXY, but expanded after RA depending on the choice of register. 5479class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls, 5480 bits<5> bytes, AddressingMode mode = bdxaddr20only> 5481 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 5482 [(operator cls:$R1, mode:$XBD2)]> { 5483 let mayStore = 1; 5484 let Has20BitOffset = 1; 5485 let HasIndex = 1; 5486 let AccessBytes = bytes; 5487} 5488 5489// Like RotateSelectRIEf, but expanded after RA depending on the choice 5490// of registers. 5491class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2> 5492 : Pseudo<(outs cls1:$R1), 5493 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 5494 imm32zx8:$I5), 5495 []> { 5496 let Constraints = "$R1 = $R1src"; 5497 let DisableEncoding = "$R1src"; 5498} 5499 5500// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is 5501// the value of the PSW's 2-bit condition code field. 5502class SelectWrapper<ValueType vt, RegisterOperand cls> 5503 : Pseudo<(outs cls:$dst), 5504 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc), 5505 [(set (vt cls:$dst), (z_select_ccmask cls:$src1, cls:$src2, 5506 imm32zx4_timm:$valid, imm32zx4_timm:$cc))]> { 5507 let usesCustomInserter = 1; 5508 let hasNoSchedulingInfo = 1; 5509 let Uses = [CC]; 5510} 5511 5512// Stores $new to $addr if $cc is true ("" case) or false (Inv case). 5513multiclass CondStores<RegisterOperand cls, SDPatternOperator store, 5514 SDPatternOperator load, AddressingMode mode> { 5515 let Uses = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1, 5516 mayLoad = 1, mayStore = 1 in { 5517 def "" : Pseudo<(outs), 5518 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), 5519 [(store (z_select_ccmask cls:$new, (load mode:$addr), 5520 imm32zx4_timm:$valid, imm32zx4_timm:$cc), 5521 mode:$addr)]>; 5522 def Inv : Pseudo<(outs), 5523 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), 5524 [(store (z_select_ccmask (load mode:$addr), cls:$new, 5525 imm32zx4_timm:$valid, imm32zx4_timm:$cc), 5526 mode:$addr)]>; 5527 } 5528} 5529 5530// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND 5531// describe the second (non-memory) operand. 5532class AtomicLoadWBinary<SDPatternOperator operator, dag pat, 5533 DAGOperand operand> 5534 : Pseudo<(outs GR32:$dst), 5535 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift, 5536 ADDR32:$negbitshift, uimm32:$bitsize), 5537 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift, 5538 ADDR32:$negbitshift, uimm32:$bitsize))]> { 5539 let Defs = [CC]; 5540 let Has20BitOffset = 1; 5541 let mayLoad = 1; 5542 let mayStore = 1; 5543 let usesCustomInserter = 1; 5544 let hasNoSchedulingInfo = 1; 5545} 5546 5547// Specializations of AtomicLoadWBinary. 5548class AtomicLoadWBinaryReg<SDPatternOperator operator> 5549 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>; 5550class AtomicLoadWBinaryImm<SDPatternOperator operator, ImmOpWithPattern imm> 5551 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>; 5552 5553// A pseudo instruction that is a direct alias of a real instruction. 5554// These aliases are used in cases where a particular register operand is 5555// fixed or where the same instruction is used with different register sizes. 5556// The size parameter is the size in bytes of the associated real instruction. 5557class Alias<int size, dag outs, dag ins, list<dag> pattern> 5558 : InstSystemZ<size, outs, ins, "", pattern> { 5559 let isPseudo = 1; 5560 let isCodeGenOnly = 1; 5561} 5562 5563class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2> 5564 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>; 5565 5566// An alias of a UnaryVRR*, but with different register sizes. 5567class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2> 5568 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2), 5569 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]>; 5570 5571// An alias of a UnaryVRX, but with different register sizes. 5572class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr, 5573 AddressingMode mode = bdxaddr12only> 5574 : Alias<6, (outs tr.op:$V1), (ins (mode $B2, $D2, $X2):$XBD2), 5575 [(set (tr.vt tr.op:$V1), (operator mode:$XBD2))]>; 5576 5577// An alias of a StoreVRX, but with different register sizes. 5578class StoreAliasVRX<SDPatternOperator operator, TypedReg tr, 5579 AddressingMode mode = bdxaddr12only> 5580 : Alias<6, (outs), (ins tr.op:$V1, (mode $B2, $D2, $X2):$XBD2), 5581 [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>; 5582 5583// An alias of a BinaryRI, but with different register sizes. 5584class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls, 5585 ImmOpWithPattern imm> 5586 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 5587 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 5588 let Constraints = "$R1 = $R1src"; 5589} 5590 5591// An alias of a BinaryRIL, but with different register sizes. 5592class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls, 5593 ImmOpWithPattern imm> 5594 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 5595 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 5596 let Constraints = "$R1 = $R1src"; 5597} 5598 5599// An alias of a BinaryVRRf, but with different register sizes. 5600class BinaryAliasVRRf<RegisterOperand cls> 5601 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>; 5602 5603// An alias of a CompareRI, but with different register sizes. 5604class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls, 5605 ImmOpWithPattern imm> 5606 : Alias<4, (outs), (ins cls:$R1, imm:$I2), 5607 [(set CC, (operator cls:$R1, imm:$I2))]> { 5608 let isCompare = 1; 5609} 5610 5611// An alias of a RotateSelectRIEf, but with different register sizes. 5612class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2> 5613 : Alias<6, (outs cls1:$R1), 5614 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 5615 imm32zx8:$I5), []> { 5616 let Constraints = "$R1 = $R1src"; 5617} 5618 5619class MemsetPseudo<DAGOperand lenop, DAGOperand byteop> 5620 : Pseudo<(outs), (ins bdaddr12only:$dest, lenop:$length, byteop:$B), 5621 [(z_memset_mvc bdaddr12only:$dest, lenop:$length, byteop:$B)]> { 5622 let Defs = [CC]; 5623 let mayLoad = 1; 5624 let mayStore = 1; 5625 let usesCustomInserter = 1; 5626 let hasNoSchedulingInfo = 1; 5627} 5628 5629//===----------------------------------------------------------------------===// 5630// Multiclasses that emit both real and pseudo instructions 5631//===----------------------------------------------------------------------===// 5632 5633multiclass BinaryRXYAndPseudo<string mnemonic, bits<16> opcode, 5634 SDPatternOperator operator, RegisterOperand cls, 5635 SDPatternOperator load, bits<5> bytes, 5636 AddressingMode mode = bdxaddr20only> { 5637 def "" : BinaryRXY<mnemonic, opcode, operator, cls, load, bytes, mode> { 5638 let MemKey = mnemonic#cls; 5639 let MemType = "target"; 5640 } 5641 let Has20BitOffset = 1 in 5642 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, mode>; 5643} 5644 5645multiclass BinaryRXPairAndPseudo<string mnemonic, bits<8> rxOpcode, 5646 bits<16> rxyOpcode, SDPatternOperator operator, 5647 RegisterOperand cls, 5648 SDPatternOperator load, bits<5> bytes> { 5649 let DispKey = mnemonic # cls in { 5650 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes, 5651 bdxaddr12pair> { 5652 let DispSize = "12"; 5653 let MemKey = mnemonic#cls; 5654 let MemType = "target"; 5655 } 5656 let DispSize = "20" in 5657 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, 5658 bytes, bdxaddr20pair>; 5659 } 5660 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, bdxaddr12pair>; 5661} 5662 5663multiclass BinaryRXEAndPseudo<string mnemonic, bits<16> opcode, 5664 SDPatternOperator operator, RegisterOperand cls, 5665 SDPatternOperator load, bits<5> bytes> { 5666 def "" : BinaryRXE<mnemonic, opcode, operator, cls, load, bytes> { 5667 let MemKey = mnemonic#cls; 5668 let MemType = "target"; 5669 } 5670 def _MemFoldPseudo : MemFoldPseudo_FP<mnemonic, cls, bytes, bdxaddr12pair>; 5671} 5672 5673multiclass TernaryRXFAndPseudo<string mnemonic, bits<16> opcode, 5674 SDPatternOperator operator, RegisterOperand cls1, 5675 RegisterOperand cls2, SDPatternOperator load, 5676 bits<5> bytes> { 5677 def "" : TernaryRXF<mnemonic, opcode, operator, cls1, cls2, load, bytes> { 5678 let MemKey = mnemonic#cls1; 5679 let MemType = "target"; 5680 } 5681 def _MemFoldPseudo : MemFoldPseudo_FPTern<mnemonic, cls1, bytes, bdxaddr12pair>; 5682} 5683 5684multiclass CondUnaryRSYPairAndMemFold<string mnemonic, bits<16> opcode, 5685 SDPatternOperator operator, 5686 RegisterOperand cls, bits<5> bytes, 5687 AddressingMode mode = bdaddr20only> { 5688 defm "" : CondUnaryRSYPair<mnemonic, opcode, operator, cls, bytes, mode>; 5689 def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>; 5690} 5691 5692multiclass CondUnaryRSYPseudoAndMemFold<string mnemonic, 5693 SDPatternOperator operator, 5694 RegisterOperand cls, bits<5> bytes, 5695 AddressingMode mode = bdaddr20only> { 5696 def "" : CondUnaryRSYPseudo<mnemonic, operator, cls, bytes, mode>; 5697 def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>; 5698} 5699 5700// Define an instruction that operates on two fixed-length blocks of memory, 5701// and associated pseudo instructions for operating on blocks of any size. 5702// There are two pseudos for the different cases of when the length is 5703// constant or variable. The length operand of a pseudo is actually one less 5704// than the intended number of bytes, since the register case needs to use an 5705// EXRL with a target instruction that adds one to the length always. 5706multiclass MemorySS<string mnemonic, bits<8> opcode, SDPatternOperator memop> { 5707 def "" : SideEffectBinarySSa<mnemonic, opcode>; 5708 let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [CC] in { 5709 def Imm : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5710 imm64:$length), 5711 [(memop bdaddr12only:$dest, bdaddr12only:$src, 5712 imm64:$length)]>; 5713 def Reg : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5714 ADDR64:$length), 5715 [(memop bdaddr12only:$dest, bdaddr12only:$src, 5716 ADDR64:$length)]>; 5717 } 5718} 5719 5720// The same, but setting a CC result as comparison operator. 5721multiclass CompareMemorySS<string mnemonic, bits<8> opcode, 5722 SDPatternOperator memop> { 5723 def "" : SideEffectBinarySSa<mnemonic, opcode>; 5724 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 5725 def Imm : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5726 imm64:$length), 5727 [(set CC, (memop bdaddr12only:$dest, bdaddr12only:$src, 5728 imm64:$length))]>; 5729 def Reg : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5730 ADDR64:$length), 5731 [(set CC, (memop bdaddr12only:$dest, bdaddr12only:$src, 5732 ADDR64:$length))]>; 5733 } 5734} 5735 5736// Define an instruction that operates on two strings, both terminated 5737// by the character in R0. The instruction processes a CPU-determinated 5738// number of bytes at a time and sets CC to 3 if the instruction needs 5739// to be repeated. Also define a pseudo instruction that represents 5740// the full loop (the main instruction plus the branch on CC==3). 5741multiclass StringRRE<string mnemonic, bits<16> opcode, 5742 SDPatternOperator operator> { 5743 let Uses = [R0L] in 5744 def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>; 5745 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 5746 def Loop : Pseudo<(outs GR64:$end), 5747 (ins GR64:$start1, GR64:$start2, GR32:$char), 5748 [(set GR64:$end, (operator GR64:$start1, GR64:$start2, 5749 GR32:$char))]>; 5750} 5751