1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SparcMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/SparcFixupKinds.h"
14 #include "SparcMCExpr.h"
15 #include "SparcMCTargetDesc.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCFixup.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectFileInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCSymbol.h"
29 #include "llvm/MC/SubtargetFeature.h"
30 #include "llvm/Support/Casting.h"
31 #include "llvm/Support/Endian.h"
32 #include "llvm/Support/EndianStream.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include <cassert>
36 #include <cstdint>
37
38 using namespace llvm;
39
40 #define DEBUG_TYPE "mccodeemitter"
41
42 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
43
44 namespace {
45
46 class SparcMCCodeEmitter : public MCCodeEmitter {
47 MCContext &Ctx;
48
49 public:
SparcMCCodeEmitter(const MCInstrInfo &,MCContext & ctx)50 SparcMCCodeEmitter(const MCInstrInfo &, MCContext &ctx)
51 : Ctx(ctx) {}
52 SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
53 SparcMCCodeEmitter &operator=(const SparcMCCodeEmitter &) = delete;
54 ~SparcMCCodeEmitter() override = default;
55
56 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
57 SmallVectorImpl<MCFixup> &Fixups,
58 const MCSubtargetInfo &STI) const override;
59
60 // getBinaryCodeForInstr - TableGen'erated function for getting the
61 // binary encoding for an instruction.
62 uint64_t getBinaryCodeForInstr(const MCInst &MI,
63 SmallVectorImpl<MCFixup> &Fixups,
64 const MCSubtargetInfo &STI) const;
65
66 /// getMachineOpValue - Return binary encoding of operand. If the machine
67 /// operand requires relocation, record the relocation and return zero.
68 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
69 SmallVectorImpl<MCFixup> &Fixups,
70 const MCSubtargetInfo &STI) const;
71 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
72 SmallVectorImpl<MCFixup> &Fixups,
73 const MCSubtargetInfo &STI) const;
74 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
75 SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &STI) const;
77 unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo,
78 SmallVectorImpl<MCFixup> &Fixups,
79 const MCSubtargetInfo &STI) const;
80 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
81 SmallVectorImpl<MCFixup> &Fixups,
82 const MCSubtargetInfo &STI) const;
83 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
84 SmallVectorImpl<MCFixup> &Fixups,
85 const MCSubtargetInfo &STI) const;
86 };
87
88 } // end anonymous namespace
89
encodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const90 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
91 SmallVectorImpl<MCFixup> &Fixups,
92 const MCSubtargetInfo &STI) const {
93 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
94 support::endian::write(OS, Bits,
95 Ctx.getAsmInfo()->isLittleEndian() ? support::little
96 : support::big);
97
98 // Some instructions have phantom operands that only contribute a fixup entry.
99 unsigned SymOpNo = 0;
100 switch (MI.getOpcode()) {
101 default: break;
102 case SP::TLS_CALL: SymOpNo = 1; break;
103 case SP::GDOP_LDrr:
104 case SP::GDOP_LDXrr:
105 case SP::TLS_ADDrr:
106 case SP::TLS_ADDXrr:
107 case SP::TLS_LDrr:
108 case SP::TLS_LDXrr: SymOpNo = 3; break;
109 }
110 if (SymOpNo != 0) {
111 const MCOperand &MO = MI.getOperand(SymOpNo);
112 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
113 assert(op == 0 && "Unexpected operand value!");
114 (void)op; // suppress warning.
115 }
116
117 ++MCNumEmitted; // Keep track of the # of mi's emitted.
118 }
119
120 unsigned SparcMCCodeEmitter::
getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const121 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
122 SmallVectorImpl<MCFixup> &Fixups,
123 const MCSubtargetInfo &STI) const {
124 if (MO.isReg())
125 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
126
127 if (MO.isImm())
128 return MO.getImm();
129
130 assert(MO.isExpr());
131 const MCExpr *Expr = MO.getExpr();
132 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
133 MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
134 Fixups.push_back(MCFixup::create(0, Expr, Kind));
135 return 0;
136 }
137
138 int64_t Res;
139 if (Expr->evaluateAsAbsolute(Res))
140 return Res;
141
142 llvm_unreachable("Unhandled expression!");
143 return 0;
144 }
145
146 unsigned
getSImm13OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const147 SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo,
148 SmallVectorImpl<MCFixup> &Fixups,
149 const MCSubtargetInfo &STI) const {
150 const MCOperand &MO = MI.getOperand(OpNo);
151
152 if (MO.isImm())
153 return MO.getImm();
154
155 assert(MO.isExpr() &&
156 "getSImm13OpValue expects only expressions or an immediate");
157
158 const MCExpr *Expr = MO.getExpr();
159
160 // Constant value, no fixup is needed
161 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
162 return CE->getValue();
163
164 MCFixupKind Kind;
165 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
166 Kind = MCFixupKind(SExpr->getFixupKind());
167 } else {
168 bool IsPic = Ctx.getObjectFileInfo()->isPositionIndependent();
169 Kind = IsPic ? MCFixupKind(Sparc::fixup_sparc_got13)
170 : MCFixupKind(Sparc::fixup_sparc_13);
171 }
172
173 Fixups.push_back(MCFixup::create(0, Expr, Kind));
174 return 0;
175 }
176
177 unsigned SparcMCCodeEmitter::
getCallTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const178 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
179 SmallVectorImpl<MCFixup> &Fixups,
180 const MCSubtargetInfo &STI) const {
181 const MCOperand &MO = MI.getOperand(OpNo);
182 const MCExpr *Expr = MO.getExpr();
183 const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr);
184
185 if (MI.getOpcode() == SP::TLS_CALL) {
186 // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
187 // encodeInstruction.
188 #ifndef NDEBUG
189 // Verify that the callee is actually __tls_get_addr.
190 assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
191 "Unexpected expression in TLS_CALL");
192 const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
193 assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
194 "Unexpected function for TLS_CALL");
195 #endif
196 return 0;
197 }
198
199 MCFixupKind Kind = MCFixupKind(SExpr->getFixupKind());
200 Fixups.push_back(MCFixup::create(0, Expr, Kind));
201 return 0;
202 }
203
204 unsigned SparcMCCodeEmitter::
getBranchTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const205 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
206 SmallVectorImpl<MCFixup> &Fixups,
207 const MCSubtargetInfo &STI) const {
208 const MCOperand &MO = MI.getOperand(OpNo);
209 if (MO.isReg() || MO.isImm())
210 return getMachineOpValue(MI, MO, Fixups, STI);
211
212 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
213 (MCFixupKind)Sparc::fixup_sparc_br22));
214 return 0;
215 }
216
217 unsigned SparcMCCodeEmitter::
getBranchPredTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const218 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
219 SmallVectorImpl<MCFixup> &Fixups,
220 const MCSubtargetInfo &STI) const {
221 const MCOperand &MO = MI.getOperand(OpNo);
222 if (MO.isReg() || MO.isImm())
223 return getMachineOpValue(MI, MO, Fixups, STI);
224
225 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
226 (MCFixupKind)Sparc::fixup_sparc_br19));
227 return 0;
228 }
229
230 unsigned SparcMCCodeEmitter::
getBranchOnRegTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const231 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
232 SmallVectorImpl<MCFixup> &Fixups,
233 const MCSubtargetInfo &STI) const {
234 const MCOperand &MO = MI.getOperand(OpNo);
235 if (MO.isReg() || MO.isImm())
236 return getMachineOpValue(MI, MO, Fixups, STI);
237
238 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
239 (MCFixupKind)Sparc::fixup_sparc_br16_2));
240 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
241 (MCFixupKind)Sparc::fixup_sparc_br16_14));
242
243 return 0;
244 }
245
246 #include "SparcGenMCCodeEmitter.inc"
247
createSparcMCCodeEmitter(const MCInstrInfo & MCII,MCContext & Ctx)248 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
249 MCContext &Ctx) {
250 return new SparcMCCodeEmitter(MCII, Ctx);
251 }
252