1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines an instruction selector for the SPARC target.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "SparcTargetMachine.h"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/IR/Intrinsics.h"
17 #include "llvm/Support/Compiler.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
21 using namespace llvm;
22
23 //===----------------------------------------------------------------------===//
24 // Instruction Selector Implementation
25 //===----------------------------------------------------------------------===//
26
27 //===--------------------------------------------------------------------===//
28 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
29 /// instructions for SelectionDAG operations.
30 ///
31 namespace {
32 class SparcDAGToDAGISel : public SelectionDAGISel {
33 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
34 /// make the right decision when generating code for different targets.
35 const SparcSubtarget &Subtarget;
36 SparcTargetMachine &TM;
37 public:
SparcDAGToDAGISel(SparcTargetMachine & tm)38 explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
39 : SelectionDAGISel(tm),
40 Subtarget(tm.getSubtarget<SparcSubtarget>()),
41 TM(tm) {
42 }
43
44 SDNode *Select(SDNode *N) override;
45
46 // Complex Pattern Selectors.
47 bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
48 bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
49
50 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
51 /// inline asm expressions.
52 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
53 char ConstraintCode,
54 std::vector<SDValue> &OutOps) override;
55
getPassName() const56 const char *getPassName() const override {
57 return "SPARC DAG->DAG Pattern Instruction Selection";
58 }
59
60 // Include the pieces autogenerated from the target description.
61 #include "SparcGenDAGISel.inc"
62
63 private:
64 SDNode* getGlobalBaseReg();
65 };
66 } // end anonymous namespace
67
getGlobalBaseReg()68 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
69 unsigned GlobalBaseReg =
70 TM.getSubtargetImpl()->getInstrInfo()->getGlobalBaseReg(MF);
71 return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode();
72 }
73
SelectADDRri(SDValue Addr,SDValue & Base,SDValue & Offset)74 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
75 SDValue &Base, SDValue &Offset) {
76 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
77 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), TLI->getPointerTy());
78 Offset = CurDAG->getTargetConstant(0, MVT::i32);
79 return true;
80 }
81 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
82 Addr.getOpcode() == ISD::TargetGlobalAddress ||
83 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
84 return false; // direct calls.
85
86 if (Addr.getOpcode() == ISD::ADD) {
87 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
88 if (isInt<13>(CN->getSExtValue())) {
89 if (FrameIndexSDNode *FIN =
90 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
91 // Constant offset from frame ref.
92 Base =
93 CurDAG->getTargetFrameIndex(FIN->getIndex(), TLI->getPointerTy());
94 } else {
95 Base = Addr.getOperand(0);
96 }
97 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
98 return true;
99 }
100 }
101 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
102 Base = Addr.getOperand(1);
103 Offset = Addr.getOperand(0).getOperand(0);
104 return true;
105 }
106 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
107 Base = Addr.getOperand(0);
108 Offset = Addr.getOperand(1).getOperand(0);
109 return true;
110 }
111 }
112 Base = Addr;
113 Offset = CurDAG->getTargetConstant(0, MVT::i32);
114 return true;
115 }
116
SelectADDRrr(SDValue Addr,SDValue & R1,SDValue & R2)117 bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
118 if (Addr.getOpcode() == ISD::FrameIndex) return false;
119 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
120 Addr.getOpcode() == ISD::TargetGlobalAddress ||
121 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
122 return false; // direct calls.
123
124 if (Addr.getOpcode() == ISD::ADD) {
125 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
126 if (isInt<13>(CN->getSExtValue()))
127 return false; // Let the reg+imm pattern catch this!
128 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
129 Addr.getOperand(1).getOpcode() == SPISD::Lo)
130 return false; // Let the reg+imm pattern catch this!
131 R1 = Addr.getOperand(0);
132 R2 = Addr.getOperand(1);
133 return true;
134 }
135
136 R1 = Addr;
137 R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy());
138 return true;
139 }
140
Select(SDNode * N)141 SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
142 SDLoc dl(N);
143 if (N->isMachineOpcode()) {
144 N->setNodeId(-1);
145 return nullptr; // Already selected.
146 }
147
148 switch (N->getOpcode()) {
149 default: break;
150 case SPISD::GLOBAL_BASE_REG:
151 return getGlobalBaseReg();
152
153 case ISD::SDIV:
154 case ISD::UDIV: {
155 // sdivx / udivx handle 64-bit divides.
156 if (N->getValueType(0) == MVT::i64)
157 break;
158 // FIXME: should use a custom expander to expose the SRA to the dag.
159 SDValue DivLHS = N->getOperand(0);
160 SDValue DivRHS = N->getOperand(1);
161
162 // Set the Y register to the high-part.
163 SDValue TopPart;
164 if (N->getOpcode() == ISD::SDIV) {
165 TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
166 CurDAG->getTargetConstant(31, MVT::i32)), 0);
167 } else {
168 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
169 }
170 TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
171 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
172
173 // FIXME: Handle div by immediate.
174 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
175 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
176 TopPart);
177 }
178 case ISD::MULHU:
179 case ISD::MULHS: {
180 // FIXME: Handle mul by immediate.
181 SDValue MulLHS = N->getOperand(0);
182 SDValue MulRHS = N->getOperand(1);
183 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
184 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
185 MulLHS, MulRHS);
186 // The high part is in the Y register.
187 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
188 }
189 }
190
191 return SelectCode(N);
192 }
193
194
195 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
196 /// inline asm expressions.
197 bool
SelectInlineAsmMemoryOperand(const SDValue & Op,char ConstraintCode,std::vector<SDValue> & OutOps)198 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
199 char ConstraintCode,
200 std::vector<SDValue> &OutOps) {
201 SDValue Op0, Op1;
202 switch (ConstraintCode) {
203 default: return true;
204 case 'm': // memory
205 if (!SelectADDRrr(Op, Op0, Op1))
206 SelectADDRri(Op, Op0, Op1);
207 break;
208 }
209
210 OutOps.push_back(Op0);
211 OutOps.push_back(Op1);
212 return false;
213 }
214
215 /// createSparcISelDag - This pass converts a legalized DAG into a
216 /// SPARC-specific DAG, ready for instruction scheduling.
217 ///
createSparcISelDag(SparcTargetMachine & TM)218 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
219 return new SparcDAGToDAGISel(TM);
220 }
221