1 //===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format SPARC assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MCTargetDesc/SparcInstPrinter.h"
15 #include "MCTargetDesc/SparcMCExpr.h"
16 #include "MCTargetDesc/SparcTargetStreamer.h"
17 #include "Sparc.h"
18 #include "SparcInstrInfo.h"
19 #include "SparcTargetMachine.h"
20 #include "TargetInfo/SparcTargetInfo.h"
21 #include "llvm/CodeGen/AsmPrinter.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/IR/Mangler.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/MC/TargetRegistry.h"
33 #include "llvm/Support/raw_ostream.h"
34 using namespace llvm;
35
36 #define DEBUG_TYPE "asm-printer"
37
38 namespace {
39 class SparcAsmPrinter : public AsmPrinter {
getTargetStreamer()40 SparcTargetStreamer &getTargetStreamer() {
41 return static_cast<SparcTargetStreamer &>(
42 *OutStreamer->getTargetStreamer());
43 }
44 public:
SparcAsmPrinter(TargetMachine & TM,std::unique_ptr<MCStreamer> Streamer)45 explicit SparcAsmPrinter(TargetMachine &TM,
46 std::unique_ptr<MCStreamer> Streamer)
47 : AsmPrinter(TM, std::move(Streamer)) {}
48
getPassName() const49 StringRef getPassName() const override { return "Sparc Assembly Printer"; }
50
51 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
52 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
53 const char *Modifier = nullptr);
54
55 void emitFunctionBodyStart() override;
56 void emitInstruction(const MachineInstr *MI) override;
57
getRegisterName(MCRegister Reg)58 static const char *getRegisterName(MCRegister Reg) {
59 return SparcInstPrinter::getRegisterName(Reg);
60 }
61
62 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
63 const char *ExtraCode, raw_ostream &O) override;
64 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
65 const char *ExtraCode, raw_ostream &O) override;
66
67 void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
68 const MCSubtargetInfo &STI);
69
70 };
71 } // end of anonymous namespace
72
createSparcMCOperand(SparcMCExpr::VariantKind Kind,MCSymbol * Sym,MCContext & OutContext)73 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind,
74 MCSymbol *Sym, MCContext &OutContext) {
75 const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Sym,
76 OutContext);
77 const SparcMCExpr *expr = SparcMCExpr::create(Kind, MCSym, OutContext);
78 return MCOperand::createExpr(expr);
79
80 }
createPCXCallOP(MCSymbol * Label,MCContext & OutContext)81 static MCOperand createPCXCallOP(MCSymbol *Label,
82 MCContext &OutContext) {
83 return createSparcMCOperand(SparcMCExpr::VK_Sparc_WDISP30, Label, OutContext);
84 }
85
createPCXRelExprOp(SparcMCExpr::VariantKind Kind,MCSymbol * GOTLabel,MCSymbol * StartLabel,MCSymbol * CurLabel,MCContext & OutContext)86 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind,
87 MCSymbol *GOTLabel, MCSymbol *StartLabel,
88 MCSymbol *CurLabel,
89 MCContext &OutContext)
90 {
91 const MCSymbolRefExpr *GOT = MCSymbolRefExpr::create(GOTLabel, OutContext);
92 const MCSymbolRefExpr *Start = MCSymbolRefExpr::create(StartLabel,
93 OutContext);
94 const MCSymbolRefExpr *Cur = MCSymbolRefExpr::create(CurLabel,
95 OutContext);
96
97 const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Cur, Start, OutContext);
98 const MCBinaryExpr *Add = MCBinaryExpr::createAdd(GOT, Sub, OutContext);
99 const SparcMCExpr *expr = SparcMCExpr::create(Kind,
100 Add, OutContext);
101 return MCOperand::createExpr(expr);
102 }
103
EmitCall(MCStreamer & OutStreamer,MCOperand & Callee,const MCSubtargetInfo & STI)104 static void EmitCall(MCStreamer &OutStreamer,
105 MCOperand &Callee,
106 const MCSubtargetInfo &STI)
107 {
108 MCInst CallInst;
109 CallInst.setOpcode(SP::CALL);
110 CallInst.addOperand(Callee);
111 OutStreamer.emitInstruction(CallInst, STI);
112 }
113
EmitSETHI(MCStreamer & OutStreamer,MCOperand & Imm,MCOperand & RD,const MCSubtargetInfo & STI)114 static void EmitSETHI(MCStreamer &OutStreamer,
115 MCOperand &Imm, MCOperand &RD,
116 const MCSubtargetInfo &STI)
117 {
118 MCInst SETHIInst;
119 SETHIInst.setOpcode(SP::SETHIi);
120 SETHIInst.addOperand(RD);
121 SETHIInst.addOperand(Imm);
122 OutStreamer.emitInstruction(SETHIInst, STI);
123 }
124
EmitBinary(MCStreamer & OutStreamer,unsigned Opcode,MCOperand & RS1,MCOperand & Src2,MCOperand & RD,const MCSubtargetInfo & STI)125 static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode,
126 MCOperand &RS1, MCOperand &Src2, MCOperand &RD,
127 const MCSubtargetInfo &STI)
128 {
129 MCInst Inst;
130 Inst.setOpcode(Opcode);
131 Inst.addOperand(RD);
132 Inst.addOperand(RS1);
133 Inst.addOperand(Src2);
134 OutStreamer.emitInstruction(Inst, STI);
135 }
136
EmitOR(MCStreamer & OutStreamer,MCOperand & RS1,MCOperand & Imm,MCOperand & RD,const MCSubtargetInfo & STI)137 static void EmitOR(MCStreamer &OutStreamer,
138 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
139 const MCSubtargetInfo &STI) {
140 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
141 }
142
EmitADD(MCStreamer & OutStreamer,MCOperand & RS1,MCOperand & RS2,MCOperand & RD,const MCSubtargetInfo & STI)143 static void EmitADD(MCStreamer &OutStreamer,
144 MCOperand &RS1, MCOperand &RS2, MCOperand &RD,
145 const MCSubtargetInfo &STI) {
146 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI);
147 }
148
EmitSHL(MCStreamer & OutStreamer,MCOperand & RS1,MCOperand & Imm,MCOperand & RD,const MCSubtargetInfo & STI)149 static void EmitSHL(MCStreamer &OutStreamer,
150 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
151 const MCSubtargetInfo &STI) {
152 EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI);
153 }
154
155
EmitHiLo(MCStreamer & OutStreamer,MCSymbol * GOTSym,SparcMCExpr::VariantKind HiKind,SparcMCExpr::VariantKind LoKind,MCOperand & RD,MCContext & OutContext,const MCSubtargetInfo & STI)156 static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym,
157 SparcMCExpr::VariantKind HiKind,
158 SparcMCExpr::VariantKind LoKind,
159 MCOperand &RD,
160 MCContext &OutContext,
161 const MCSubtargetInfo &STI) {
162
163 MCOperand hi = createSparcMCOperand(HiKind, GOTSym, OutContext);
164 MCOperand lo = createSparcMCOperand(LoKind, GOTSym, OutContext);
165 EmitSETHI(OutStreamer, hi, RD, STI);
166 EmitOR(OutStreamer, RD, lo, RD, STI);
167 }
168
LowerGETPCXAndEmitMCInsts(const MachineInstr * MI,const MCSubtargetInfo & STI)169 void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
170 const MCSubtargetInfo &STI)
171 {
172 MCSymbol *GOTLabel =
173 OutContext.getOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
174
175 const MachineOperand &MO = MI->getOperand(0);
176 assert(MO.getReg() != SP::O7 &&
177 "%o7 is assigned as destination for getpcx!");
178
179 MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
180
181
182 if (!isPositionIndependent()) {
183 // Just load the address of GOT to MCRegOP.
184 switch(TM.getCodeModel()) {
185 default:
186 llvm_unreachable("Unsupported absolute code model");
187 case CodeModel::Small:
188 EmitHiLo(*OutStreamer, GOTLabel,
189 SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
190 MCRegOP, OutContext, STI);
191 break;
192 case CodeModel::Medium: {
193 EmitHiLo(*OutStreamer, GOTLabel,
194 SparcMCExpr::VK_Sparc_H44, SparcMCExpr::VK_Sparc_M44,
195 MCRegOP, OutContext, STI);
196 MCOperand imm = MCOperand::createExpr(MCConstantExpr::create(12,
197 OutContext));
198 EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
199 MCOperand lo = createSparcMCOperand(SparcMCExpr::VK_Sparc_L44,
200 GOTLabel, OutContext);
201 EmitOR(*OutStreamer, MCRegOP, lo, MCRegOP, STI);
202 break;
203 }
204 case CodeModel::Large: {
205 EmitHiLo(*OutStreamer, GOTLabel,
206 SparcMCExpr::VK_Sparc_HH, SparcMCExpr::VK_Sparc_HM,
207 MCRegOP, OutContext, STI);
208 MCOperand imm = MCOperand::createExpr(MCConstantExpr::create(32,
209 OutContext));
210 EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
211 // Use register %o7 to load the lower 32 bits.
212 MCOperand RegO7 = MCOperand::createReg(SP::O7);
213 EmitHiLo(*OutStreamer, GOTLabel,
214 SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
215 RegO7, OutContext, STI);
216 EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
217 }
218 }
219 return;
220 }
221
222 MCSymbol *StartLabel = OutContext.createTempSymbol();
223 MCSymbol *EndLabel = OutContext.createTempSymbol();
224 MCSymbol *SethiLabel = OutContext.createTempSymbol();
225
226 MCOperand RegO7 = MCOperand::createReg(SP::O7);
227
228 // <StartLabel>:
229 // call <EndLabel>
230 // <SethiLabel>:
231 // sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
232 // <EndLabel>:
233 // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
234 // add <MO>, %o7, <MO>
235
236 OutStreamer->emitLabel(StartLabel);
237 MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
238 EmitCall(*OutStreamer, Callee, STI);
239 OutStreamer->emitLabel(SethiLabel);
240 MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC22,
241 GOTLabel, StartLabel, SethiLabel,
242 OutContext);
243 EmitSETHI(*OutStreamer, hiImm, MCRegOP, STI);
244 OutStreamer->emitLabel(EndLabel);
245 MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC10,
246 GOTLabel, StartLabel, EndLabel,
247 OutContext);
248 EmitOR(*OutStreamer, MCRegOP, loImm, MCRegOP, STI);
249 EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
250 }
251
emitInstruction(const MachineInstr * MI)252 void SparcAsmPrinter::emitInstruction(const MachineInstr *MI) {
253 Sparc_MC::verifyInstructionPredicates(MI->getOpcode(),
254 getSubtargetInfo().getFeatureBits());
255
256 switch (MI->getOpcode()) {
257 default: break;
258 case TargetOpcode::DBG_VALUE:
259 // FIXME: Debug Value.
260 return;
261 case SP::GETPCX:
262 LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo());
263 return;
264 }
265 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
266 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
267 do {
268 MCInst TmpInst;
269 LowerSparcMachineInstrToMCInst(&*I, TmpInst, *this);
270 EmitToStreamer(*OutStreamer, TmpInst);
271 } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
272 }
273
emitFunctionBodyStart()274 void SparcAsmPrinter::emitFunctionBodyStart() {
275 if (!MF->getSubtarget<SparcSubtarget>().is64Bit())
276 return;
277
278 const MachineRegisterInfo &MRI = MF->getRegInfo();
279 const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
280 for (unsigned i = 0; globalRegs[i] != 0; ++i) {
281 unsigned reg = globalRegs[i];
282 if (MRI.use_empty(reg))
283 continue;
284
285 if (reg == SP::G6 || reg == SP::G7)
286 getTargetStreamer().emitSparcRegisterIgnore(reg);
287 else
288 getTargetStreamer().emitSparcRegisterScratch(reg);
289 }
290 }
291
printOperand(const MachineInstr * MI,int opNum,raw_ostream & O)292 void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
293 raw_ostream &O) {
294 const DataLayout &DL = getDataLayout();
295 const MachineOperand &MO = MI->getOperand (opNum);
296 SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags();
297
298 #ifndef NDEBUG
299 // Verify the target flags.
300 if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
301 if (MI->getOpcode() == SP::CALL)
302 assert(TF == SparcMCExpr::VK_Sparc_None &&
303 "Cannot handle target flags on call address");
304 else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
305 assert((TF == SparcMCExpr::VK_Sparc_HI
306 || TF == SparcMCExpr::VK_Sparc_H44
307 || TF == SparcMCExpr::VK_Sparc_HH
308 || TF == SparcMCExpr::VK_Sparc_LM
309 || TF == SparcMCExpr::VK_Sparc_TLS_GD_HI22
310 || TF == SparcMCExpr::VK_Sparc_TLS_LDM_HI22
311 || TF == SparcMCExpr::VK_Sparc_TLS_LDO_HIX22
312 || TF == SparcMCExpr::VK_Sparc_TLS_IE_HI22
313 || TF == SparcMCExpr::VK_Sparc_TLS_LE_HIX22) &&
314 "Invalid target flags for address operand on sethi");
315 else if (MI->getOpcode() == SP::TLS_CALL)
316 assert((TF == SparcMCExpr::VK_Sparc_None
317 || TF == SparcMCExpr::VK_Sparc_TLS_GD_CALL
318 || TF == SparcMCExpr::VK_Sparc_TLS_LDM_CALL) &&
319 "Cannot handle target flags on tls call address");
320 else if (MI->getOpcode() == SP::TLS_ADDrr)
321 assert((TF == SparcMCExpr::VK_Sparc_TLS_GD_ADD
322 || TF == SparcMCExpr::VK_Sparc_TLS_LDM_ADD
323 || TF == SparcMCExpr::VK_Sparc_TLS_LDO_ADD
324 || TF == SparcMCExpr::VK_Sparc_TLS_IE_ADD) &&
325 "Cannot handle target flags on add for TLS");
326 else if (MI->getOpcode() == SP::TLS_LDrr)
327 assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LD &&
328 "Cannot handle target flags on ld for TLS");
329 else if (MI->getOpcode() == SP::TLS_LDXrr)
330 assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LDX &&
331 "Cannot handle target flags on ldx for TLS");
332 else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri)
333 assert((TF == SparcMCExpr::VK_Sparc_TLS_LDO_LOX10
334 || TF == SparcMCExpr::VK_Sparc_TLS_LE_LOX10) &&
335 "Cannot handle target flags on xor for TLS");
336 else
337 assert((TF == SparcMCExpr::VK_Sparc_LO
338 || TF == SparcMCExpr::VK_Sparc_M44
339 || TF == SparcMCExpr::VK_Sparc_L44
340 || TF == SparcMCExpr::VK_Sparc_HM
341 || TF == SparcMCExpr::VK_Sparc_TLS_GD_LO10
342 || TF == SparcMCExpr::VK_Sparc_TLS_LDM_LO10
343 || TF == SparcMCExpr::VK_Sparc_TLS_IE_LO10 ) &&
344 "Invalid target flags for small address operand");
345 }
346 #endif
347
348
349 bool CloseParen = SparcMCExpr::printVariantKind(O, TF);
350
351 switch (MO.getType()) {
352 case MachineOperand::MO_Register:
353 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
354 break;
355
356 case MachineOperand::MO_Immediate:
357 O << MO.getImm();
358 break;
359 case MachineOperand::MO_MachineBasicBlock:
360 MO.getMBB()->getSymbol()->print(O, MAI);
361 return;
362 case MachineOperand::MO_GlobalAddress:
363 PrintSymbolOperand(MO, O);
364 break;
365 case MachineOperand::MO_BlockAddress:
366 O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
367 break;
368 case MachineOperand::MO_ExternalSymbol:
369 O << MO.getSymbolName();
370 break;
371 case MachineOperand::MO_ConstantPoolIndex:
372 O << DL.getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
373 << MO.getIndex();
374 break;
375 case MachineOperand::MO_Metadata:
376 MO.getMetadata()->printAsOperand(O, MMI->getModule());
377 break;
378 default:
379 llvm_unreachable("<unknown operand type>");
380 }
381 if (CloseParen) O << ")";
382 }
383
printMemOperand(const MachineInstr * MI,int opNum,raw_ostream & O,const char * Modifier)384 void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
385 raw_ostream &O, const char *Modifier) {
386 printOperand(MI, opNum, O);
387
388 // If this is an ADD operand, emit it like normal operands.
389 if (Modifier && !strcmp(Modifier, "arith")) {
390 O << ", ";
391 printOperand(MI, opNum+1, O);
392 return;
393 }
394
395 if (MI->getOperand(opNum+1).isReg() &&
396 MI->getOperand(opNum+1).getReg() == SP::G0)
397 return; // don't print "+%g0"
398 if (MI->getOperand(opNum+1).isImm() &&
399 MI->getOperand(opNum+1).getImm() == 0)
400 return; // don't print "+0"
401
402 O << "+";
403 printOperand(MI, opNum+1, O);
404 }
405
406 /// PrintAsmOperand - Print out an operand for an inline asm expression.
407 ///
PrintAsmOperand(const MachineInstr * MI,unsigned OpNo,const char * ExtraCode,raw_ostream & O)408 bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
409 const char *ExtraCode,
410 raw_ostream &O) {
411 if (ExtraCode && ExtraCode[0]) {
412 if (ExtraCode[1] != 0) return true; // Unknown modifier.
413
414 switch (ExtraCode[0]) {
415 default:
416 // See if this is a generic print operand
417 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
418 case 'f':
419 case 'r':
420 break;
421 }
422 }
423
424 printOperand(MI, OpNo, O);
425
426 return false;
427 }
428
PrintAsmMemoryOperand(const MachineInstr * MI,unsigned OpNo,const char * ExtraCode,raw_ostream & O)429 bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
430 unsigned OpNo,
431 const char *ExtraCode,
432 raw_ostream &O) {
433 if (ExtraCode && ExtraCode[0])
434 return true; // Unknown modifier
435
436 O << '[';
437 printMemOperand(MI, OpNo, O);
438 O << ']';
439
440 return false;
441 }
442
443 // Force static initialization.
LLVMInitializeSparcAsmPrinter()444 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcAsmPrinter() {
445 RegisterAsmPrinter<SparcAsmPrinter> X(getTheSparcTarget());
446 RegisterAsmPrinter<SparcAsmPrinter> Y(getTheSparcV9Target());
447 RegisterAsmPrinter<SparcAsmPrinter> Z(getTheSparcelTarget());
448 }
449