1 //===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "MCTargetDesc/SparcFixupKinds.h"
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "llvm/ADT/StringSwitch.h"
12 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCELFObjectWriter.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCFixupKindInfo.h"
16 #include "llvm/MC/MCObjectWriter.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCValue.h"
19 #include "llvm/MC/TargetRegistry.h"
20 #include "llvm/Support/EndianStream.h"
21
22 using namespace llvm;
23
adjustFixupValue(unsigned Kind,uint64_t Value)24 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
25 switch (Kind) {
26 default:
27 llvm_unreachable("Unknown fixup kind!");
28 case FK_Data_1:
29 case FK_Data_2:
30 case FK_Data_4:
31 case FK_Data_8:
32 return Value;
33
34 case Sparc::fixup_sparc_wplt30:
35 case Sparc::fixup_sparc_call30:
36 return (Value >> 2) & 0x3fffffff;
37
38 case Sparc::fixup_sparc_br22:
39 return (Value >> 2) & 0x3fffff;
40
41 case Sparc::fixup_sparc_br19:
42 return (Value >> 2) & 0x7ffff;
43
44 case Sparc::fixup_sparc_br16_2:
45 return (Value >> 2) & 0xc000;
46
47 case Sparc::fixup_sparc_br16_14:
48 return (Value >> 2) & 0x3fff;
49
50 case Sparc::fixup_sparc_hix22:
51 return (~Value >> 10) & 0x3fffff;
52
53 case Sparc::fixup_sparc_pc22:
54 case Sparc::fixup_sparc_got22:
55 case Sparc::fixup_sparc_tls_gd_hi22:
56 case Sparc::fixup_sparc_tls_ldm_hi22:
57 case Sparc::fixup_sparc_tls_ie_hi22:
58 case Sparc::fixup_sparc_hi22:
59 case Sparc::fixup_sparc_lm:
60 return (Value >> 10) & 0x3fffff;
61
62 case Sparc::fixup_sparc_got13:
63 case Sparc::fixup_sparc_13:
64 return Value & 0x1fff;
65
66 case Sparc::fixup_sparc_lox10:
67 return (Value & 0x3ff) | 0x1c00;
68
69 case Sparc::fixup_sparc_pc10:
70 case Sparc::fixup_sparc_got10:
71 case Sparc::fixup_sparc_tls_gd_lo10:
72 case Sparc::fixup_sparc_tls_ldm_lo10:
73 case Sparc::fixup_sparc_tls_ie_lo10:
74 case Sparc::fixup_sparc_lo10:
75 return Value & 0x3ff;
76
77 case Sparc::fixup_sparc_h44:
78 return (Value >> 22) & 0x3fffff;
79
80 case Sparc::fixup_sparc_m44:
81 return (Value >> 12) & 0x3ff;
82
83 case Sparc::fixup_sparc_l44:
84 return Value & 0xfff;
85
86 case Sparc::fixup_sparc_hh:
87 return (Value >> 42) & 0x3fffff;
88
89 case Sparc::fixup_sparc_hm:
90 return (Value >> 32) & 0x3ff;
91
92 case Sparc::fixup_sparc_tls_ldo_hix22:
93 case Sparc::fixup_sparc_tls_le_hix22:
94 case Sparc::fixup_sparc_tls_ldo_lox10:
95 case Sparc::fixup_sparc_tls_le_lox10:
96 assert(Value == 0 && "Sparc TLS relocs expect zero Value");
97 return 0;
98
99 case Sparc::fixup_sparc_tls_gd_add:
100 case Sparc::fixup_sparc_tls_gd_call:
101 case Sparc::fixup_sparc_tls_ldm_add:
102 case Sparc::fixup_sparc_tls_ldm_call:
103 case Sparc::fixup_sparc_tls_ldo_add:
104 case Sparc::fixup_sparc_tls_ie_ld:
105 case Sparc::fixup_sparc_tls_ie_ldx:
106 case Sparc::fixup_sparc_tls_ie_add:
107 case Sparc::fixup_sparc_gotdata_lox10:
108 case Sparc::fixup_sparc_gotdata_hix22:
109 case Sparc::fixup_sparc_gotdata_op:
110 return 0;
111 }
112 }
113
114 /// getFixupKindNumBytes - The number of bytes the fixup may change.
getFixupKindNumBytes(unsigned Kind)115 static unsigned getFixupKindNumBytes(unsigned Kind) {
116 switch (Kind) {
117 default:
118 return 4;
119 case FK_Data_1:
120 return 1;
121 case FK_Data_2:
122 return 2;
123 case FK_Data_8:
124 return 8;
125 }
126 }
127
128 namespace {
129 class SparcAsmBackend : public MCAsmBackend {
130 protected:
131 const Target &TheTarget;
132 bool Is64Bit;
133
134 public:
SparcAsmBackend(const Target & T)135 SparcAsmBackend(const Target &T)
136 : MCAsmBackend(StringRef(T.getName()) == "sparcel" ? support::little
137 : support::big),
138 TheTarget(T), Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {}
139
getNumFixupKinds() const140 unsigned getNumFixupKinds() const override {
141 return Sparc::NumTargetFixupKinds;
142 }
143
getFixupKind(StringRef Name) const144 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override {
145 unsigned Type;
146 Type = llvm::StringSwitch<unsigned>(Name)
147 #define ELF_RELOC(X, Y) .Case(#X, Y)
148 #include "llvm/BinaryFormat/ELFRelocs/Sparc.def"
149 #undef ELF_RELOC
150 .Case("BFD_RELOC_NONE", ELF::R_SPARC_NONE)
151 .Case("BFD_RELOC_8", ELF::R_SPARC_8)
152 .Case("BFD_RELOC_16", ELF::R_SPARC_16)
153 .Case("BFD_RELOC_32", ELF::R_SPARC_32)
154 .Case("BFD_RELOC_64", ELF::R_SPARC_64)
155 .Default(-1u);
156 if (Type == -1u)
157 return std::nullopt;
158 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
159 }
160
getFixupKindInfo(MCFixupKind Kind) const161 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
162 const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
163 // name offset bits flags
164 { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
165 { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
166 { "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
167 { "fixup_sparc_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel },
168 { "fixup_sparc_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel },
169 { "fixup_sparc_13", 19, 13, 0 },
170 { "fixup_sparc_hi22", 10, 22, 0 },
171 { "fixup_sparc_lo10", 22, 10, 0 },
172 { "fixup_sparc_h44", 10, 22, 0 },
173 { "fixup_sparc_m44", 22, 10, 0 },
174 { "fixup_sparc_l44", 20, 12, 0 },
175 { "fixup_sparc_hh", 10, 22, 0 },
176 { "fixup_sparc_hm", 22, 10, 0 },
177 { "fixup_sparc_lm", 10, 22, 0 },
178 { "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
179 { "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel },
180 { "fixup_sparc_got22", 10, 22, 0 },
181 { "fixup_sparc_got10", 22, 10, 0 },
182 { "fixup_sparc_got13", 19, 13, 0 },
183 { "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
184 { "fixup_sparc_tls_gd_hi22", 10, 22, 0 },
185 { "fixup_sparc_tls_gd_lo10", 22, 10, 0 },
186 { "fixup_sparc_tls_gd_add", 0, 0, 0 },
187 { "fixup_sparc_tls_gd_call", 0, 0, 0 },
188 { "fixup_sparc_tls_ldm_hi22", 10, 22, 0 },
189 { "fixup_sparc_tls_ldm_lo10", 22, 10, 0 },
190 { "fixup_sparc_tls_ldm_add", 0, 0, 0 },
191 { "fixup_sparc_tls_ldm_call", 0, 0, 0 },
192 { "fixup_sparc_tls_ldo_hix22", 10, 22, 0 },
193 { "fixup_sparc_tls_ldo_lox10", 22, 10, 0 },
194 { "fixup_sparc_tls_ldo_add", 0, 0, 0 },
195 { "fixup_sparc_tls_ie_hi22", 10, 22, 0 },
196 { "fixup_sparc_tls_ie_lo10", 22, 10, 0 },
197 { "fixup_sparc_tls_ie_ld", 0, 0, 0 },
198 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
199 { "fixup_sparc_tls_ie_add", 0, 0, 0 },
200 { "fixup_sparc_tls_le_hix22", 0, 0, 0 },
201 { "fixup_sparc_tls_le_lox10", 0, 0, 0 },
202 { "fixup_sparc_hix22", 10, 22, 0 },
203 { "fixup_sparc_lox10", 19, 13, 0 },
204 { "fixup_sparc_gotdata_hix22", 0, 0, 0 },
205 { "fixup_sparc_gotdata_lox10", 0, 0, 0 },
206 { "fixup_sparc_gotdata_op", 0, 0, 0 },
207 };
208
209 const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
210 // name offset bits flags
211 { "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
212 { "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
213 { "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
214 { "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel },
215 { "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel },
216 { "fixup_sparc_13", 0, 13, 0 },
217 { "fixup_sparc_hi22", 0, 22, 0 },
218 { "fixup_sparc_lo10", 0, 10, 0 },
219 { "fixup_sparc_h44", 0, 22, 0 },
220 { "fixup_sparc_m44", 0, 10, 0 },
221 { "fixup_sparc_l44", 0, 12, 0 },
222 { "fixup_sparc_hh", 0, 22, 0 },
223 { "fixup_sparc_hm", 0, 10, 0 },
224 { "fixup_sparc_lm", 0, 22, 0 },
225 { "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
226 { "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
227 { "fixup_sparc_got22", 0, 22, 0 },
228 { "fixup_sparc_got10", 0, 10, 0 },
229 { "fixup_sparc_got13", 0, 13, 0 },
230 { "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
231 { "fixup_sparc_tls_gd_hi22", 0, 22, 0 },
232 { "fixup_sparc_tls_gd_lo10", 0, 10, 0 },
233 { "fixup_sparc_tls_gd_add", 0, 0, 0 },
234 { "fixup_sparc_tls_gd_call", 0, 0, 0 },
235 { "fixup_sparc_tls_ldm_hi22", 0, 22, 0 },
236 { "fixup_sparc_tls_ldm_lo10", 0, 10, 0 },
237 { "fixup_sparc_tls_ldm_add", 0, 0, 0 },
238 { "fixup_sparc_tls_ldm_call", 0, 0, 0 },
239 { "fixup_sparc_tls_ldo_hix22", 0, 22, 0 },
240 { "fixup_sparc_tls_ldo_lox10", 0, 10, 0 },
241 { "fixup_sparc_tls_ldo_add", 0, 0, 0 },
242 { "fixup_sparc_tls_ie_hi22", 0, 22, 0 },
243 { "fixup_sparc_tls_ie_lo10", 0, 10, 0 },
244 { "fixup_sparc_tls_ie_ld", 0, 0, 0 },
245 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
246 { "fixup_sparc_tls_ie_add", 0, 0, 0 },
247 { "fixup_sparc_tls_le_hix22", 0, 0, 0 },
248 { "fixup_sparc_tls_le_lox10", 0, 0, 0 },
249 { "fixup_sparc_hix22", 0, 22, 0 },
250 { "fixup_sparc_lox10", 0, 13, 0 },
251 { "fixup_sparc_gotdata_hix22", 0, 0, 0 },
252 { "fixup_sparc_gotdata_lox10", 0, 0, 0 },
253 { "fixup_sparc_gotdata_op", 0, 0, 0 },
254 };
255
256 // Fixup kinds from .reloc directive are like R_SPARC_NONE. They do
257 // not require any extra processing.
258 if (Kind >= FirstLiteralRelocationKind)
259 return MCAsmBackend::getFixupKindInfo(FK_NONE);
260
261 if (Kind < FirstTargetFixupKind)
262 return MCAsmBackend::getFixupKindInfo(Kind);
263
264 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
265 "Invalid kind!");
266 if (Endian == support::little)
267 return InfosLE[Kind - FirstTargetFixupKind];
268
269 return InfosBE[Kind - FirstTargetFixupKind];
270 }
271
shouldForceRelocation(const MCAssembler & Asm,const MCFixup & Fixup,const MCValue & Target)272 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
273 const MCValue &Target) override {
274 if (Fixup.getKind() >= FirstLiteralRelocationKind)
275 return true;
276 switch ((Sparc::Fixups)Fixup.getKind()) {
277 default:
278 return false;
279 case Sparc::fixup_sparc_wplt30:
280 if (Target.getSymA()->getSymbol().isTemporary())
281 return false;
282 [[fallthrough]];
283 case Sparc::fixup_sparc_tls_gd_hi22:
284 case Sparc::fixup_sparc_tls_gd_lo10:
285 case Sparc::fixup_sparc_tls_gd_add:
286 case Sparc::fixup_sparc_tls_gd_call:
287 case Sparc::fixup_sparc_tls_ldm_hi22:
288 case Sparc::fixup_sparc_tls_ldm_lo10:
289 case Sparc::fixup_sparc_tls_ldm_add:
290 case Sparc::fixup_sparc_tls_ldm_call:
291 case Sparc::fixup_sparc_tls_ldo_hix22:
292 case Sparc::fixup_sparc_tls_ldo_lox10:
293 case Sparc::fixup_sparc_tls_ldo_add:
294 case Sparc::fixup_sparc_tls_ie_hi22:
295 case Sparc::fixup_sparc_tls_ie_lo10:
296 case Sparc::fixup_sparc_tls_ie_ld:
297 case Sparc::fixup_sparc_tls_ie_ldx:
298 case Sparc::fixup_sparc_tls_ie_add:
299 case Sparc::fixup_sparc_tls_le_hix22:
300 case Sparc::fixup_sparc_tls_le_lox10:
301 return true;
302 }
303 }
304
305 /// fixupNeedsRelaxation - Target specific predicate for whether a given
306 /// fixup requires the associated instruction to be relaxed.
fixupNeedsRelaxation(const MCFixup & Fixup,uint64_t Value,const MCRelaxableFragment * DF,const MCAsmLayout & Layout) const307 bool fixupNeedsRelaxation(const MCFixup &Fixup,
308 uint64_t Value,
309 const MCRelaxableFragment *DF,
310 const MCAsmLayout &Layout) const override {
311 // FIXME.
312 llvm_unreachable("fixupNeedsRelaxation() unimplemented");
313 return false;
314 }
relaxInstruction(MCInst & Inst,const MCSubtargetInfo & STI) const315 void relaxInstruction(MCInst &Inst,
316 const MCSubtargetInfo &STI) const override {
317 // FIXME.
318 llvm_unreachable("relaxInstruction() unimplemented");
319 }
320
writeNopData(raw_ostream & OS,uint64_t Count,const MCSubtargetInfo * STI) const321 bool writeNopData(raw_ostream &OS, uint64_t Count,
322 const MCSubtargetInfo *STI) const override {
323 // Cannot emit NOP with size not multiple of 32 bits.
324 if (Count % 4 != 0)
325 return false;
326
327 uint64_t NumNops = Count / 4;
328 for (uint64_t i = 0; i != NumNops; ++i)
329 support::endian::write<uint32_t>(OS, 0x01000000, Endian);
330
331 return true;
332 }
333 };
334
335 class ELFSparcAsmBackend : public SparcAsmBackend {
336 Triple::OSType OSType;
337 public:
ELFSparcAsmBackend(const Target & T,Triple::OSType OSType)338 ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
339 SparcAsmBackend(T), OSType(OSType) { }
340
applyFixup(const MCAssembler & Asm,const MCFixup & Fixup,const MCValue & Target,MutableArrayRef<char> Data,uint64_t Value,bool IsResolved,const MCSubtargetInfo * STI) const341 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
342 const MCValue &Target, MutableArrayRef<char> Data,
343 uint64_t Value, bool IsResolved,
344 const MCSubtargetInfo *STI) const override {
345
346 if (Fixup.getKind() >= FirstLiteralRelocationKind)
347 return;
348 Value = adjustFixupValue(Fixup.getKind(), Value);
349 if (!Value) return; // Doesn't change encoding.
350
351 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
352 unsigned Offset = Fixup.getOffset();
353 // For each byte of the fragment that the fixup touches, mask in the bits
354 // from the fixup value. The Value has been "split up" into the
355 // appropriate bitfields above.
356 for (unsigned i = 0; i != NumBytes; ++i) {
357 unsigned Idx = Endian == support::little ? i : (NumBytes - 1) - i;
358 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
359 }
360 }
361
362 std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const363 createObjectTargetWriter() const override {
364 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
365 return createSparcELFObjectWriter(Is64Bit, OSABI);
366 }
367 };
368
369 } // end anonymous namespace
370
createSparcAsmBackend(const Target & T,const MCSubtargetInfo & STI,const MCRegisterInfo & MRI,const MCTargetOptions & Options)371 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
372 const MCSubtargetInfo &STI,
373 const MCRegisterInfo &MRI,
374 const MCTargetOptions &Options) {
375 return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS());
376 }
377