xref: /llvm-project/llvm/test/Transforms/TypePromotion/ARM/signed.ll (revision 28f21cafdeac553039c9ae47a23df114c52bc27c) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -mtriple=arm -passes=typepromotion,verify  -S %s -o - | FileCheck %s
3
4; Test to check that ARMCodeGenPrepare doesn't optimised away sign extends.
5define i16 @test_signed_load(ptr %ptr) {
6; CHECK-LABEL: @test_signed_load(
7; CHECK-NEXT:    [[LOAD:%.*]] = load i16, ptr [[PTR:%.*]], align 2
8; CHECK-NEXT:    [[CONV0:%.*]] = zext i16 [[LOAD]] to i32
9; CHECK-NEXT:    [[CONV1:%.*]] = sext i16 [[LOAD]] to i32
10; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[CONV0]], [[CONV1]]
11; CHECK-NEXT:    [[CONV2:%.*]] = zext i1 [[CMP]] to i16
12; CHECK-NEXT:    ret i16 [[CONV2]]
13;
14  %load = load i16, ptr %ptr
15  %conv0 = zext i16 %load to i32
16  %conv1 = sext i16 %load to i32
17  %cmp = icmp eq i32 %conv0, %conv1
18  %conv2 = zext i1 %cmp to i16
19  ret i16 %conv2
20}
21
22; Don't allow sign bit generating opcodes.
23define i16 @test_ashr(i16 zeroext %arg) {
24; CHECK-LABEL: @test_ashr(
25; CHECK-NEXT:    [[ASHR:%.*]] = ashr i16 [[ARG:%.*]], 1
26; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i16 [[ASHR]], 0
27; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i16
28; CHECK-NEXT:    ret i16 [[CONV]]
29;
30  %ashr = ashr i16 %arg, 1
31  %cmp = icmp eq i16 %ashr, 0
32  %conv = zext i1 %cmp to i16
33  ret i16 %conv
34}
35
36define i16 @test_sdiv(i16 zeroext %arg) {
37; CHECK-LABEL: @test_sdiv(
38; CHECK-NEXT:    [[SDIV:%.*]] = sdiv i16 [[ARG:%.*]], 2
39; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i16 [[SDIV]], 0
40; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i16
41; CHECK-NEXT:    ret i16 [[CONV]]
42;
43  %sdiv = sdiv i16 %arg, 2
44  %cmp = icmp ne i16 %sdiv, 0
45  %conv = zext i1 %cmp to i16
46  ret i16 %conv
47}
48
49define i16 @test_srem(i16 zeroext %arg) {
50; CHECK-LABEL: @test_srem(
51; CHECK-NEXT:    [[SREM:%.*]] = srem i16 [[ARG:%.*]], 4
52; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i16 [[SREM]], 0
53; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i16
54; CHECK-NEXT:    ret i16 [[CONV]]
55;
56  %srem = srem i16 %arg, 4
57  %cmp = icmp ne i16 %srem, 0
58  %conv = zext i1 %cmp to i16
59  ret i16 %conv
60}
61
62define i32 @test_signext_b(ptr %ptr, i8 signext %arg) {
63; CHECK-LABEL: @test_signext_b(
64; CHECK-NEXT:  entry:
65; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[ARG:%.*]] to i32
66; CHECK-NEXT:    [[TMP1:%.*]] = load i8, ptr [[PTR:%.*]], align 1
67; CHECK-NEXT:    [[TMP2:%.*]] = zext i8 [[TMP1]] to i32
68; CHECK-NEXT:    [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], [[TMP0]]
69; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP3]], 128
70; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 42, i32 20894
71; CHECK-NEXT:    ret i32 [[RES]]
72;
73entry:
74  %0 = load i8, ptr %ptr, align 1
75  %1 = add nuw nsw i8 %0, %arg
76  %cmp = icmp ult i8 %1, 128
77  %res = select i1 %cmp, i32 42, i32 20894
78  ret i32 %res
79}
80
81define i32 @test_signext_b_ult_slt(ptr %ptr, i8 signext %arg) {
82; CHECK-LABEL: @test_signext_b_ult_slt(
83; CHECK-NEXT:  entry:
84; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[ARG:%.*]] to i32
85; CHECK-NEXT:    [[TMP1:%.*]] = load i8, ptr [[PTR:%.*]], align 1
86; CHECK-NEXT:    [[TMP2:%.*]] = zext i8 [[TMP1]] to i32
87; CHECK-NEXT:    [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], [[TMP0]]
88; CHECK-NEXT:    [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8
89; CHECK-NEXT:    [[CMP:%.*]] = icmp sle i8 [[TMP4]], 126
90; CHECK-NEXT:    [[CMP_1:%.*]] = icmp ule i32 [[TMP3]], [[TMP0]]
91; CHECK-NEXT:    [[OR:%.*]] = and i1 [[CMP]], [[CMP_1]]
92; CHECK-NEXT:    [[RES:%.*]] = select i1 [[OR]], i32 42, i32 57
93; CHECK-NEXT:    ret i32 [[RES]]
94;
95entry:
96  %0 = load i8, ptr %ptr, align 1
97  %1 = add nuw nsw i8 %0, %arg
98  %cmp = icmp sle i8 %1, 126
99  %cmp.1 = icmp ule i8 %1, %arg
100  %or = and i1 %cmp, %cmp.1
101  %res = select i1 %or, i32 42, i32 57
102  ret i32 %res
103}
104
105define i32 @test_signext_h(ptr %ptr, i16 signext %arg) {
106; CHECK-LABEL: @test_signext_h(
107; CHECK-NEXT:  entry:
108; CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[ARG:%.*]] to i32
109; CHECK-NEXT:    [[TMP1:%.*]] = load i16, ptr [[PTR:%.*]], align 1
110; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[TMP1]] to i32
111; CHECK-NEXT:    [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], [[TMP0]]
112; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP3]], 32768
113; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 42, i32 20894
114; CHECK-NEXT:    ret i32 [[RES]]
115;
116entry:
117  %0 = load i16, ptr %ptr, align 1
118  %1 = add nuw nsw i16 %0, %arg
119  %cmp = icmp ult i16 %1, 32768
120  %res = select i1 %cmp, i32 42, i32 20894
121  ret i32 %res
122}
123
124