1//===- SPIRVBase.td - MLIR SPIR-V Op Definitions Base file -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the base file for SPIR-V operation definition specification. 10// This file defines the SPIR-V dialect, common SPIR-V types, and utilities 11// for facilitating defining SPIR-V ops. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef MLIR_DIALECT_SPIRV_IR_BASE 16#define MLIR_DIALECT_SPIRV_IR_BASE 17 18include "mlir/IR/EnumAttr.td" 19include "mlir/IR/OpBase.td" 20include "mlir/Dialect/SPIRV/IR/SPIRVAvailability.td" 21 22//===----------------------------------------------------------------------===// 23// SPIR-V dialect definitions 24//===----------------------------------------------------------------------===// 25 26def SPIRV_Dialect : Dialect { 27 let name = "spirv"; 28 29 let summary = "The SPIR-V dialect in MLIR."; 30 31 let description = [{ 32 SPIR-V is a binary intermediate language for representing graphical-shader 33 stages and compute kernels for multiple Khronos APIs, including OpenCL, 34 OpenGL, and Vulkan. 35 See https://www.khronos.org/registry/spir-v for more details regarding 36 SPIR-V itself. 37 38 The SPIR-V dialect aims to be a proper compiler intermediate representation 39 to facilitate transformations. Ops in this dialect stay at the same semantic 40 level as the SPIR-V specification and try to have one-to-one mapping to the 41 corresponding SPIR-V instructions; but they may deviate representationally 42 to utilize MLIR mechanisms if it results in better representation and thus 43 benefits transformations. The dialect also aims to maintain straightforward 44 serialization into and deserialization from the SPIR-V binary format. 45 See https://mlir.llvm.org/docs/Dialects/SPIR-V/ for more details regarding 46 high-level designs and implementation structures of the SPIR-V dialect. 47 }]; 48 49 let cppNamespace = "::mlir::spirv"; 50 let useDefaultTypePrinterParser = 1; 51 let hasConstantMaterializer = 1; 52 let hasOperationAttrVerify = 1; 53 let hasRegionArgAttrVerify = 1; 54 let hasRegionResultAttrVerify = 1; 55 56 let extraClassDeclaration = [{ 57 void registerAttributes(); 58 void registerTypes(); 59 60 //===------------------------------------------------------------------===// 61 // Attribute 62 //===------------------------------------------------------------------===// 63 64 /// Returns the attribute name to use when specifying decorations on results 65 /// of operations. 66 static std::string getAttributeName(Decoration decoration); 67 68 /// Dialect attribute parsing hook. 69 Attribute parseAttribute( 70 DialectAsmParser &parser, Type type) const override; 71 /// Dialect attribute printing hook. 72 void printAttribute( 73 Attribute attr, DialectAsmPrinter &printer) const override; 74 }]; 75} 76 77//===----------------------------------------------------------------------===// 78// Utility definitions 79//===----------------------------------------------------------------------===// 80 81// Wrapper over base BitEnumAttr to set common fields. 82class SPIRV_BitEnum<string name, string description, 83 list<BitEnumAttrCaseBase> cases> 84 : I32BitEnumAttr<name, description, cases> { 85 let genSpecializedAttr = 0; 86 let cppNamespace = "::mlir::spirv"; 87} 88class SPIRV_BitEnumAttr<string name, string description, string mnemonic, 89 list<BitEnumAttrCaseBase> cases> : 90 EnumAttr<SPIRV_Dialect, SPIRV_BitEnum<name, description, cases>, mnemonic> { 91 let assemblyFormat = "`<` $value `>`"; 92} 93 94// Wrapper over base I32EnumAttr to set common fields. 95class SPIRV_I32Enum<string name, string description, 96 list<I32EnumAttrCase> cases> 97 : I32EnumAttr<name, description, cases> { 98 let genSpecializedAttr = 0; 99 let cppNamespace = "::mlir::spirv"; 100} 101class SPIRV_I32EnumAttr<string name, string description, string mnemonic, 102 list<I32EnumAttrCase> cases> : 103 EnumAttr<SPIRV_Dialect, SPIRV_I32Enum<name, description, cases>, mnemonic> { 104 let assemblyFormat = "`<` $value `>`"; 105} 106 107//===----------------------------------------------------------------------===// 108// SPIR-V availability definitions 109//===----------------------------------------------------------------------===// 110 111def SPIRV_V_1_0 : I32EnumAttrCase<"V_1_0", 0, "v1.0">; 112def SPIRV_V_1_1 : I32EnumAttrCase<"V_1_1", 1, "v1.1">; 113def SPIRV_V_1_2 : I32EnumAttrCase<"V_1_2", 2, "v1.2">; 114def SPIRV_V_1_3 : I32EnumAttrCase<"V_1_3", 3, "v1.3">; 115def SPIRV_V_1_4 : I32EnumAttrCase<"V_1_4", 4, "v1.4">; 116def SPIRV_V_1_5 : I32EnumAttrCase<"V_1_5", 5, "v1.5">; 117def SPIRV_V_1_6 : I32EnumAttrCase<"V_1_6", 6, "v1.6">; 118 119def SPIRV_VersionAttr : SPIRV_I32EnumAttr< 120 "Version", "valid SPIR-V version", "version", [ 121 SPIRV_V_1_0, SPIRV_V_1_1, SPIRV_V_1_2, SPIRV_V_1_3, SPIRV_V_1_4, SPIRV_V_1_5, 122 SPIRV_V_1_6]>; 123 124class MinVersion<I32EnumAttrCase min> : MinVersionBase< 125 "QueryMinVersionInterface", SPIRV_VersionAttr, min> { 126 let cppNamespace = "::mlir::spirv"; 127 let interfaceDescription = [{ 128 Querying interface for minimal required SPIR-V version. 129 130 This interface provides a `getMinVersion()` method to query the minimal 131 required version for the implementing SPIR-V operation. The returned value 132 is a `mlir::spirv::Version` enumerant. 133 }]; 134} 135 136class MaxVersion<I32EnumAttrCase max> : MaxVersionBase< 137 "QueryMaxVersionInterface", SPIRV_VersionAttr, max> { 138 let cppNamespace = "::mlir::spirv"; 139 let interfaceDescription = [{ 140 Querying interface for maximal supported SPIR-V version. 141 142 This interface provides a `getMaxVersion()` method to query the maximal 143 supported version for the implementing SPIR-V operation. The returned value 144 is a `mlir::spirv::Version` enumerant. 145 }]; 146} 147 148class Extension<list<I32EnumAttrCase> extensions> : Availability { 149 let cppNamespace = "::mlir::spirv"; 150 let interfaceName = "QueryExtensionInterface"; 151 let interfaceDescription = [{ 152 Querying interface for required SPIR-V extensions. 153 154 This interface provides a `getExtensions()` method to query the required 155 extensions for the implementing SPIR-V operation. The returned value 156 is a nested vector whose element is `mlir::spirv::Extension`s. The outer 157 vector's elements (which are vectors) should be interpreted as conjunction 158 while the inner vector's elements (which are `mlir::spirv::Extension`s) 159 should be interpreted as disjunction. For example, given 160 161 ``` 162 {{Extension::A, Extension::B}, {Extension::C}, {{Extension::D, Extension::E}} 163 ``` 164 165 The operation instance is available when (`Extension::A` OR `Extension::B`) 166 AND (`Extension::C`) AND (`Extension::D` OR `Extension::E`) is enabled. 167 }]; 168 169 // TODO: Returning SmallVector<ArrayRef<...>> is not recommended. 170 // Find a better way for this. 171 let queryFnRetType = "::llvm::SmallVector<::llvm::ArrayRef<" 172 "::mlir::spirv::Extension>, 1>"; 173 let queryFnName = "getExtensions"; 174 175 let mergeAction = !if( 176 !empty(extensions), "", "$overall.emplace_back($instance)"); 177 let initializer = "{}"; 178 let instanceType = "::llvm::ArrayRef<::mlir::spirv::Extension>"; 179 180 // Pack all extensions as a static array and get its reference. 181 let instancePreparation = !if(!empty(extensions), "", 182 "static const ::mlir::spirv::Extension exts[] = {" # 183 !interleave(!foreach(ext, extensions, 184 "::mlir::spirv::Extension::" # ext.symbol), ", ") # 185 "}; " # 186 // The following manual ArrayRef constructor call is to satisfy GCC 5. 187 "ArrayRef<::mlir::spirv::Extension> " # 188 "ref(exts, std::size(exts));"); 189 let instance = "ref"; 190} 191 192class Capability<list<I32EnumAttrCase> capabilities> : Availability { 193 let cppNamespace = "::mlir::spirv"; 194 let interfaceName = "QueryCapabilityInterface"; 195 let interfaceDescription = [{ 196 Querying interface for required SPIR-V capabilities. 197 198 This interface provides a `getCapabilities()` method to query the required 199 capabilities for the implementing SPIR-V operation. The returned value 200 is a nested vector whose element is `mlir::spirv::Capability`s. The outer 201 vector's elements (which are vectors) should be interpreted as conjunction 202 while the inner vector's elements (which are `mlir::spirv::Capability`s) 203 should be interpreted as disjunction. For example, given 204 205 ``` 206 {{Capability::A, Capability::B}, {Capability::C}, {{Capability::D, Capability::E}} 207 ``` 208 209 The operation instance is available when (`Capability::A` OR `Capability::B`) 210 AND (`Capability::C`) AND (`Capability::D` OR `Capability::E`) is enabled. 211 }]; 212 213 let queryFnRetType = "::llvm::SmallVector<::llvm::ArrayRef<" 214 "::mlir::spirv::Capability>, 1>"; 215 let queryFnName = "getCapabilities"; 216 217 let mergeAction = !if( 218 !empty(capabilities), "", "$overall.emplace_back($instance)"); 219 let initializer = "{}"; 220 let instanceType = "::llvm::ArrayRef<::mlir::spirv::Capability>"; 221 222 // Pack all capabilities as a static array and get its reference. 223 let instancePreparation = !if(!empty(capabilities), "", 224 "static const ::mlir::spirv::Capability caps[] = {" # 225 !interleave(!foreach(cap, capabilities, 226 "::mlir::spirv::Capability::" # cap.symbol), ", ") # 227 "}; " # 228 // The following manual ArrayRef constructor call is to satisfy GCC 5. 229 "ArrayRef<::mlir::spirv::Capability> " # 230 "ref(caps, std::size(caps));"); 231 let instance = "ref"; 232} 233 234class SPIRVOpInterface<string name> : OpInterface<name> { 235 let cppNamespace = "::mlir::spirv"; 236} 237// TODO: the following interfaces definitions are duplicating with the above. 238// Remove them once we are able to support dialect-specific contents in ODS. 239def QueryMinVersionInterface : SPIRVOpInterface<"QueryMinVersionInterface"> { 240 let methods = [InterfaceMethod< 241 "", "::std::optional<::mlir::spirv::Version>", "getMinVersion">]; 242} 243def QueryMaxVersionInterface : SPIRVOpInterface<"QueryMaxVersionInterface"> { 244 let methods = [InterfaceMethod< 245 "", "::std::optional<::mlir::spirv::Version>", "getMaxVersion">]; 246} 247def QueryExtensionInterface : SPIRVOpInterface<"QueryExtensionInterface"> { 248 let methods = [InterfaceMethod< 249 "", 250 "::llvm::SmallVector<::llvm::ArrayRef<::mlir::spirv::Extension>, 1>", 251 "getExtensions">]; 252} 253def QueryCapabilityInterface : SPIRVOpInterface<"QueryCapabilityInterface"> { 254 let methods = [InterfaceMethod< 255 "", 256 "::llvm::SmallVector<::llvm::ArrayRef<::mlir::spirv::Capability>, 1>", 257 "getCapabilities">]; 258} 259 260//===----------------------------------------------------------------------===// 261// SPIR-V target GPU vendor and device definitions 262//===----------------------------------------------------------------------===// 263 264def SPIRV_DT_CPU : I32EnumAttrCase<"CPU", 0>; 265def SPIRV_DT_DiscreteGPU : I32EnumAttrCase<"DiscreteGPU", 1>; 266def SPIRV_DT_IntegratedGPU : I32EnumAttrCase<"IntegratedGPU", 2>; 267// An accelerator other than GPU or CPU 268def SPIRV_DT_Other : I32EnumAttrCase<"Other", 3>; 269// Information missing. 270def SPIRV_DT_Unknown : I32EnumAttrCase<"Unknown", 0xffffffff>; 271 272def SPIRV_DeviceTypeAttr : SPIRV_I32EnumAttr< 273 "DeviceType", "valid SPIR-V device types", "device_type", [ 274 SPIRV_DT_Other, SPIRV_DT_IntegratedGPU, SPIRV_DT_DiscreteGPU, 275 SPIRV_DT_CPU, SPIRV_DT_Unknown 276 ]>; 277 278def SPIRV_V_AMD : I32EnumAttrCase<"AMD", 0>; 279def SPIRV_V_Apple : I32EnumAttrCase<"Apple", 1>; 280def SPIRV_V_ARM : I32EnumAttrCase<"ARM", 2>; 281def SPIRV_V_Broadcom : I32EnumAttrCase<"Broadcom", 3>; 282def SPIRV_V_Imagination : I32EnumAttrCase<"Imagination", 4>; 283def SPIRV_V_Intel : I32EnumAttrCase<"Intel", 5>; 284def SPIRV_V_NVIDIA : I32EnumAttrCase<"NVIDIA", 6>; 285def SPIRV_V_Qualcomm : I32EnumAttrCase<"Qualcomm", 7>; 286def SPIRV_V_SwiftShader : I32EnumAttrCase<"SwiftShader", 8>; 287def SPIRV_V_Unknown : I32EnumAttrCase<"Unknown", 0xffffffff>; 288 289def SPIRV_VendorAttr : SPIRV_I32EnumAttr< 290 "Vendor", "recognized SPIR-V vendor strings", "vendor", [ 291 SPIRV_V_AMD, SPIRV_V_Apple, SPIRV_V_ARM, SPIRV_V_Broadcom, SPIRV_V_Imagination, 292 SPIRV_V_Intel, SPIRV_V_NVIDIA, SPIRV_V_Qualcomm, SPIRV_V_SwiftShader, 293 SPIRV_V_Unknown 294 ]>; 295 296def SPIRV_CA_Metal : I32EnumAttrCase<"Metal", 0>; 297def SPIRV_CA_OpenCL : I32EnumAttrCase<"OpenCL", 1>; 298def SPIRV_CA_Vulkan : I32EnumAttrCase<"Vulkan", 2>; 299def SPIRV_CA_WebGPU : I32EnumAttrCase<"WebGPU", 3>; 300def SPIRV_CA_Unknown : I32EnumAttrCase<"Unknown", 0xffffffff>; 301 302def SPIRV_ClientAPIAttr : SPIRV_I32EnumAttr< 303 "ClientAPI", "recognized SPIR-V client APIs", "client_api", [ 304 SPIRV_CA_Metal, SPIRV_CA_OpenCL, SPIRV_CA_Vulkan, SPIRV_CA_WebGPU, 305 SPIRV_CA_Unknown 306 ]>; 307 308//===----------------------------------------------------------------------===// 309// SPIR-V extension definitions 310//===----------------------------------------------------------------------===// 311 312// Extensions known to the SPIR-V dialect. 313// https://github.com/KhronosGroup/SPIRV-Registry has the full list. 314// These start with the 'SPV' prefix to match the Khronos' naming scheme. 315def SPV_KHR_16bit_storage : I32EnumAttrCase<"SPV_KHR_16bit_storage", 0>; 316def SPV_KHR_8bit_storage : I32EnumAttrCase<"SPV_KHR_8bit_storage", 1>; 317def SPV_KHR_device_group : I32EnumAttrCase<"SPV_KHR_device_group", 2>; 318def SPV_KHR_float_controls : I32EnumAttrCase<"SPV_KHR_float_controls", 3>; 319def SPV_KHR_physical_storage_buffer : I32EnumAttrCase<"SPV_KHR_physical_storage_buffer", 4>; 320def SPV_KHR_multiview : I32EnumAttrCase<"SPV_KHR_multiview", 5>; 321def SPV_KHR_no_integer_wrap_decoration : I32EnumAttrCase<"SPV_KHR_no_integer_wrap_decoration", 6>; 322def SPV_KHR_post_depth_coverage : I32EnumAttrCase<"SPV_KHR_post_depth_coverage", 7>; 323def SPV_KHR_shader_atomic_counter_ops : I32EnumAttrCase<"SPV_KHR_shader_atomic_counter_ops", 8>; 324def SPV_KHR_shader_ballot : I32EnumAttrCase<"SPV_KHR_shader_ballot", 9>; 325def SPV_KHR_shader_clock : I32EnumAttrCase<"SPV_KHR_shader_clock", 10>; 326def SPV_KHR_shader_draw_parameters : I32EnumAttrCase<"SPV_KHR_shader_draw_parameters", 11>; 327def SPV_KHR_storage_buffer_storage_class : I32EnumAttrCase<"SPV_KHR_storage_buffer_storage_class", 12>; 328def SPV_KHR_subgroup_vote : I32EnumAttrCase<"SPV_KHR_subgroup_vote", 13>; 329def SPV_KHR_variable_pointers : I32EnumAttrCase<"SPV_KHR_variable_pointers", 14>; 330def SPV_KHR_vulkan_memory_model : I32EnumAttrCase<"SPV_KHR_vulkan_memory_model", 15>; 331def SPV_KHR_expect_assume : I32EnumAttrCase<"SPV_KHR_expect_assume", 16>; 332def SPV_KHR_integer_dot_product : I32EnumAttrCase<"SPV_KHR_integer_dot_product", 17>; 333def SPV_KHR_bit_instructions : I32EnumAttrCase<"SPV_KHR_bit_instructions", 18>; 334def SPV_KHR_fragment_shading_rate : I32EnumAttrCase<"SPV_KHR_fragment_shading_rate", 19>; 335def SPV_KHR_workgroup_memory_explicit_layout : I32EnumAttrCase<"SPV_KHR_workgroup_memory_explicit_layout", 20>; 336def SPV_KHR_ray_query : I32EnumAttrCase<"SPV_KHR_ray_query", 21>; 337def SPV_KHR_ray_tracing : I32EnumAttrCase<"SPV_KHR_ray_tracing", 22>; 338def SPV_KHR_subgroup_uniform_control_flow : I32EnumAttrCase<"SPV_KHR_subgroup_uniform_control_flow", 23>; 339def SPV_KHR_linkonce_odr : I32EnumAttrCase<"SPV_KHR_linkonce_odr", 24>; 340def SPV_KHR_fragment_shader_barycentric : I32EnumAttrCase<"SPV_KHR_fragment_shader_barycentric", 25>; 341def SPV_KHR_ray_cull_mask : I32EnumAttrCase<"SPV_KHR_ray_cull_mask", 26>; 342def SPV_KHR_uniform_group_instructions : I32EnumAttrCase<"SPV_KHR_uniform_group_instructions", 27>; 343def SPV_KHR_subgroup_rotate : I32EnumAttrCase<"SPV_KHR_subgroup_rotate", 28>; 344def SPV_KHR_non_semantic_info : I32EnumAttrCase<"SPV_KHR_non_semantic_info", 29>; 345def SPV_KHR_terminate_invocation : I32EnumAttrCase<"SPV_KHR_terminate_invocation", 30>; 346def SPV_KHR_cooperative_matrix : I32EnumAttrCase<"SPV_KHR_cooperative_matrix", 31>; 347 348def SPV_EXT_demote_to_helper_invocation : I32EnumAttrCase<"SPV_EXT_demote_to_helper_invocation", 1000>; 349def SPV_EXT_descriptor_indexing : I32EnumAttrCase<"SPV_EXT_descriptor_indexing", 1001>; 350def SPV_EXT_fragment_fully_covered : I32EnumAttrCase<"SPV_EXT_fragment_fully_covered", 1002>; 351def SPV_EXT_fragment_invocation_density : I32EnumAttrCase<"SPV_EXT_fragment_invocation_density", 1003>; 352def SPV_EXT_fragment_shader_interlock : I32EnumAttrCase<"SPV_EXT_fragment_shader_interlock", 1004>; 353def SPV_EXT_physical_storage_buffer : I32EnumAttrCase<"SPV_EXT_physical_storage_buffer", 1005>; 354def SPV_EXT_shader_stencil_export : I32EnumAttrCase<"SPV_EXT_shader_stencil_export", 1006>; 355def SPV_EXT_shader_viewport_index_layer : I32EnumAttrCase<"SPV_EXT_shader_viewport_index_layer", 1007>; 356def SPV_EXT_shader_atomic_float_add : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_add", 1008>; 357def SPV_EXT_shader_atomic_float_min_max : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_min_max", 1009>; 358def SPV_EXT_shader_image_int64 : I32EnumAttrCase<"SPV_EXT_shader_image_int64", 1010>; 359def SPV_EXT_shader_atomic_float16_add : I32EnumAttrCase<"SPV_EXT_shader_atomic_float16_add", 1011>; 360 361def SPV_AMD_gpu_shader_half_float_fetch : I32EnumAttrCase<"SPV_AMD_gpu_shader_half_float_fetch", 2000>; 362def SPV_AMD_shader_ballot : I32EnumAttrCase<"SPV_AMD_shader_ballot", 2001>; 363def SPV_AMD_shader_explicit_vertex_parameter : I32EnumAttrCase<"SPV_AMD_shader_explicit_vertex_parameter", 2002>; 364def SPV_AMD_shader_fragment_mask : I32EnumAttrCase<"SPV_AMD_shader_fragment_mask", 2003>; 365def SPV_AMD_shader_image_load_store_lod : I32EnumAttrCase<"SPV_AMD_shader_image_load_store_lod", 2004>; 366def SPV_AMD_texture_gather_bias_lod : I32EnumAttrCase<"SPV_AMD_texture_gather_bias_lod", 2005>; 367def SPV_AMD_shader_early_and_late_fragment_tests : I32EnumAttrCase<"SPV_AMD_shader_early_and_late_fragment_tests", 2006>; 368 369def SPV_GOOGLE_decorate_string : I32EnumAttrCase<"SPV_GOOGLE_decorate_string", 3000>; 370def SPV_GOOGLE_hlsl_functionality1 : I32EnumAttrCase<"SPV_GOOGLE_hlsl_functionality1", 3001>; 371def SPV_GOOGLE_user_type : I32EnumAttrCase<"SPV_GOOGLE_user_type", 3002>; 372 373def SPV_INTEL_device_side_avc_motion_estimation : I32EnumAttrCase<"SPV_INTEL_device_side_avc_motion_estimation", 4000>; 374def SPV_INTEL_media_block_io : I32EnumAttrCase<"SPV_INTEL_media_block_io", 4001>; 375def SPV_INTEL_shader_integer_functions2 : I32EnumAttrCase<"SPV_INTEL_shader_integer_functions2", 4002>; 376def SPV_INTEL_subgroups : I32EnumAttrCase<"SPV_INTEL_subgroups", 4003>; 377def SPV_INTEL_float_controls2 : I32EnumAttrCase<"SPV_INTEL_float_controls2", 4004>; 378def SPV_INTEL_function_pointers : I32EnumAttrCase<"SPV_INTEL_function_pointers", 4005>; 379def SPV_INTEL_inline_assembly : I32EnumAttrCase<"SPV_INTEL_inline_assembly", 4006>; 380def SPV_INTEL_vector_compute : I32EnumAttrCase<"SPV_INTEL_vector_compute", 4007>; 381def SPV_INTEL_variable_length_array : I32EnumAttrCase<"SPV_INTEL_variable_length_array", 4008>; 382def SPV_INTEL_fpga_memory_attributes : I32EnumAttrCase<"SPV_INTEL_fpga_memory_attributes", 4009>; 383def SPV_INTEL_arbitrary_precision_integers : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_integers", 4010>; 384def SPV_INTEL_arbitrary_precision_floating_point : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_floating_point", 4011>; 385def SPV_INTEL_unstructured_loop_controls : I32EnumAttrCase<"SPV_INTEL_unstructured_loop_controls", 4012>; 386def SPV_INTEL_fpga_loop_controls : I32EnumAttrCase<"SPV_INTEL_fpga_loop_controls", 4013>; 387def SPV_INTEL_kernel_attributes : I32EnumAttrCase<"SPV_INTEL_kernel_attributes", 4014>; 388def SPV_INTEL_fpga_memory_accesses : I32EnumAttrCase<"SPV_INTEL_fpga_memory_accesses", 4015>; 389def SPV_INTEL_fpga_cluster_attributes : I32EnumAttrCase<"SPV_INTEL_fpga_cluster_attributes", 4016>; 390def SPV_INTEL_loop_fuse : I32EnumAttrCase<"SPV_INTEL_loop_fuse", 4017>; 391def SPV_INTEL_fpga_buffer_location : I32EnumAttrCase<"SPV_INTEL_fpga_buffer_location", 4018>; 392def SPV_INTEL_arbitrary_precision_fixed_point : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_fixed_point", 4019>; 393def SPV_INTEL_usm_storage_classes : I32EnumAttrCase<"SPV_INTEL_usm_storage_classes", 4020>; 394def SPV_INTEL_io_pipes : I32EnumAttrCase<"SPV_INTEL_io_pipes", 4021>; 395def SPV_INTEL_blocking_pipes : I32EnumAttrCase<"SPV_INTEL_blocking_pipes", 4022>; 396def SPV_INTEL_fpga_reg : I32EnumAttrCase<"SPV_INTEL_fpga_reg", 4023>; 397def SPV_INTEL_long_constant_composite : I32EnumAttrCase<"SPV_INTEL_long_constant_composite", 4024>; 398def SPV_INTEL_optnone : I32EnumAttrCase<"SPV_INTEL_optnone", 4025>; 399def SPV_INTEL_debug_module : I32EnumAttrCase<"SPV_INTEL_debug_module", 4026>; 400def SPV_INTEL_fp_fast_math_mode : I32EnumAttrCase<"SPV_INTEL_fp_fast_math_mode", 4027>; 401def SPV_INTEL_memory_access_aliasing : I32EnumAttrCase<"SPV_INTEL_memory_access_aliasing", 4028>; 402def SPV_INTEL_split_barrier : I32EnumAttrCase<"SPV_INTEL_split_barrier", 4029>; 403def SPV_INTEL_bfloat16_conversion : I32EnumAttrCase<"SPV_INTEL_bfloat16_conversion", 4031>; 404def SPV_INTEL_cache_controls : I32EnumAttrCase<"SPV_INTEL_cache_controls", 4032>; 405 406def SPV_NV_compute_shader_derivatives : I32EnumAttrCase<"SPV_NV_compute_shader_derivatives", 5000>; 407def SPV_NV_cooperative_matrix : I32EnumAttrCase<"SPV_NV_cooperative_matrix", 5001>; 408def SPV_NV_fragment_shader_barycentric : I32EnumAttrCase<"SPV_NV_fragment_shader_barycentric", 5002>; 409def SPV_NV_geometry_shader_passthrough : I32EnumAttrCase<"SPV_NV_geometry_shader_passthrough", 5003>; 410def SPV_NV_mesh_shader : I32EnumAttrCase<"SPV_NV_mesh_shader", 5004>; 411def SPV_NV_ray_tracing : I32EnumAttrCase<"SPV_NV_ray_tracing", 5005>; 412def SPV_NV_sample_mask_override_coverage : I32EnumAttrCase<"SPV_NV_sample_mask_override_coverage", 5006>; 413def SPV_NV_shader_image_footprint : I32EnumAttrCase<"SPV_NV_shader_image_footprint", 5007>; 414def SPV_NV_shader_sm_builtins : I32EnumAttrCase<"SPV_NV_shader_sm_builtins", 5008>; 415def SPV_NV_shader_subgroup_partitioned : I32EnumAttrCase<"SPV_NV_shader_subgroup_partitioned", 5009>; 416def SPV_NV_shading_rate : I32EnumAttrCase<"SPV_NV_shading_rate", 5010>; 417def SPV_NV_stereo_view_rendering : I32EnumAttrCase<"SPV_NV_stereo_view_rendering", 5011>; 418def SPV_NV_viewport_array2 : I32EnumAttrCase<"SPV_NV_viewport_array2", 5012>; 419def SPV_NV_bindless_texture : I32EnumAttrCase<"SPV_NV_bindless_texture", 5013>; 420def SPV_NV_ray_tracing_motion_blur : I32EnumAttrCase<"SPV_NV_ray_tracing_motion_blur", 5014>; 421 422def SPV_NVX_multiview_per_view_attributes : I32EnumAttrCase<"SPV_NVX_multiview_per_view_attributes", 5015>; 423 424def SPIRV_ExtensionAttr : 425 SPIRV_I32EnumAttr<"Extension", "supported SPIR-V extensions", "ext", [ 426 SPV_KHR_16bit_storage, SPV_KHR_8bit_storage, SPV_KHR_device_group, 427 SPV_KHR_float_controls, SPV_KHR_physical_storage_buffer, SPV_KHR_multiview, 428 SPV_KHR_no_integer_wrap_decoration, SPV_KHR_post_depth_coverage, 429 SPV_KHR_shader_atomic_counter_ops, SPV_KHR_shader_ballot, 430 SPV_KHR_shader_clock, SPV_KHR_shader_draw_parameters, 431 SPV_KHR_storage_buffer_storage_class, SPV_KHR_subgroup_vote, 432 SPV_KHR_variable_pointers, SPV_KHR_vulkan_memory_model, SPV_KHR_expect_assume, 433 SPV_KHR_integer_dot_product, SPV_KHR_bit_instructions, SPV_KHR_fragment_shading_rate, 434 SPV_KHR_workgroup_memory_explicit_layout, SPV_KHR_ray_query, 435 SPV_KHR_ray_tracing, SPV_KHR_subgroup_uniform_control_flow, SPV_KHR_linkonce_odr, 436 SPV_KHR_fragment_shader_barycentric, SPV_KHR_ray_cull_mask, 437 SPV_KHR_uniform_group_instructions, SPV_KHR_subgroup_rotate, 438 SPV_KHR_non_semantic_info, SPV_KHR_terminate_invocation, 439 SPV_KHR_cooperative_matrix, 440 SPV_EXT_demote_to_helper_invocation, SPV_EXT_descriptor_indexing, 441 SPV_EXT_fragment_fully_covered, SPV_EXT_fragment_invocation_density, 442 SPV_EXT_fragment_shader_interlock, SPV_EXT_physical_storage_buffer, 443 SPV_EXT_shader_stencil_export, SPV_EXT_shader_viewport_index_layer, 444 SPV_EXT_shader_atomic_float_add, SPV_EXT_shader_atomic_float_min_max, 445 SPV_EXT_shader_image_int64, SPV_EXT_shader_atomic_float16_add, 446 SPV_AMD_gpu_shader_half_float_fetch, SPV_AMD_shader_ballot, 447 SPV_AMD_shader_explicit_vertex_parameter, SPV_AMD_shader_fragment_mask, 448 SPV_AMD_shader_image_load_store_lod, SPV_AMD_texture_gather_bias_lod, 449 SPV_AMD_shader_early_and_late_fragment_tests, 450 SPV_GOOGLE_decorate_string, SPV_GOOGLE_hlsl_functionality1, SPV_GOOGLE_user_type, 451 SPV_INTEL_device_side_avc_motion_estimation, SPV_INTEL_media_block_io, 452 SPV_INTEL_shader_integer_functions2, SPV_INTEL_subgroups, SPV_INTEL_vector_compute, 453 SPV_INTEL_float_controls2, SPV_INTEL_function_pointers, SPV_INTEL_inline_assembly, 454 SPV_INTEL_variable_length_array, SPV_INTEL_fpga_memory_attributes, 455 SPV_INTEL_unstructured_loop_controls, SPV_INTEL_fpga_loop_controls, 456 SPV_INTEL_arbitrary_precision_integers, SPV_INTEL_arbitrary_precision_floating_point, 457 SPV_INTEL_kernel_attributes, SPV_INTEL_fpga_memory_accesses, 458 SPV_INTEL_fpga_cluster_attributes, SPV_INTEL_loop_fuse, 459 SPV_INTEL_fpga_buffer_location, SPV_INTEL_arbitrary_precision_fixed_point, 460 SPV_INTEL_usm_storage_classes, SPV_INTEL_io_pipes, SPV_INTEL_blocking_pipes, 461 SPV_INTEL_fpga_reg, SPV_INTEL_long_constant_composite, SPV_INTEL_optnone, 462 SPV_INTEL_debug_module, SPV_INTEL_fp_fast_math_mode, 463 SPV_INTEL_memory_access_aliasing, SPV_INTEL_split_barrier, 464 SPV_INTEL_bfloat16_conversion, SPV_INTEL_cache_controls, 465 SPV_NV_compute_shader_derivatives, SPV_NV_cooperative_matrix, 466 SPV_NV_fragment_shader_barycentric, SPV_NV_geometry_shader_passthrough, 467 SPV_NV_mesh_shader, SPV_NV_ray_tracing, SPV_NV_sample_mask_override_coverage, 468 SPV_NV_shader_image_footprint, SPV_NV_shader_sm_builtins, 469 SPV_NV_shader_subgroup_partitioned, SPV_NV_shading_rate, 470 SPV_NV_stereo_view_rendering, SPV_NV_viewport_array2, SPV_NV_bindless_texture, 471 SPV_NV_ray_tracing_motion_blur, SPV_NVX_multiview_per_view_attributes 472 ]>; 473 474//===----------------------------------------------------------------------===// 475// SPIR-V enum definitions 476//===----------------------------------------------------------------------===// 477 478// Begin enum section. Generated from SPIR-V spec; DO NOT MODIFY! 479 480def SPIRV_C_Matrix : I32EnumAttrCase<"Matrix", 0>; 481def SPIRV_C_Addresses : I32EnumAttrCase<"Addresses", 4>; 482def SPIRV_C_Linkage : I32EnumAttrCase<"Linkage", 5>; 483def SPIRV_C_Kernel : I32EnumAttrCase<"Kernel", 6>; 484def SPIRV_C_Float16 : I32EnumAttrCase<"Float16", 9>; 485def SPIRV_C_Float64 : I32EnumAttrCase<"Float64", 10>; 486def SPIRV_C_Int64 : I32EnumAttrCase<"Int64", 11>; 487def SPIRV_C_Groups : I32EnumAttrCase<"Groups", 18> { 488 list<Availability> availability = [ 489 Extension<[SPV_AMD_shader_ballot]> 490 ]; 491} 492def SPIRV_C_Int16 : I32EnumAttrCase<"Int16", 22>; 493def SPIRV_C_Int8 : I32EnumAttrCase<"Int8", 39>; 494def SPIRV_C_Sampled1D : I32EnumAttrCase<"Sampled1D", 43>; 495def SPIRV_C_SampledBuffer : I32EnumAttrCase<"SampledBuffer", 46>; 496def SPIRV_C_GroupNonUniform : I32EnumAttrCase<"GroupNonUniform", 61> { 497 list<Availability> availability = [ 498 MinVersion<SPIRV_V_1_3> 499 ]; 500} 501def SPIRV_C_ShaderLayer : I32EnumAttrCase<"ShaderLayer", 69> { 502 list<Availability> availability = [ 503 MinVersion<SPIRV_V_1_5> 504 ]; 505} 506def SPIRV_C_ShaderViewportIndex : I32EnumAttrCase<"ShaderViewportIndex", 70> { 507 list<Availability> availability = [ 508 MinVersion<SPIRV_V_1_5> 509 ]; 510} 511def SPIRV_C_UniformDecoration : I32EnumAttrCase<"UniformDecoration", 71> { 512 list<Availability> availability = [ 513 MinVersion<SPIRV_V_1_6> 514 ]; 515} 516def SPIRV_C_SubgroupBallotKHR : I32EnumAttrCase<"SubgroupBallotKHR", 4423> { 517 list<Availability> availability = [ 518 Extension<[SPV_KHR_shader_ballot]> 519 ]; 520} 521def SPIRV_C_SubgroupVoteKHR : I32EnumAttrCase<"SubgroupVoteKHR", 4431> { 522 list<Availability> availability = [ 523 Extension<[SPV_KHR_subgroup_vote]> 524 ]; 525} 526def SPIRV_C_StorageBuffer16BitAccess : I32EnumAttrCase<"StorageBuffer16BitAccess", 4433> { 527 list<Availability> availability = [ 528 Extension<[SPV_KHR_16bit_storage]> 529 ]; 530} 531def SPIRV_C_StoragePushConstant16 : I32EnumAttrCase<"StoragePushConstant16", 4435> { 532 list<Availability> availability = [ 533 Extension<[SPV_KHR_16bit_storage]> 534 ]; 535} 536def SPIRV_C_StorageInputOutput16 : I32EnumAttrCase<"StorageInputOutput16", 4436> { 537 list<Availability> availability = [ 538 Extension<[SPV_KHR_16bit_storage]> 539 ]; 540} 541def SPIRV_C_DeviceGroup : I32EnumAttrCase<"DeviceGroup", 4437> { 542 list<Availability> availability = [ 543 Extension<[SPV_KHR_device_group]> 544 ]; 545} 546def SPIRV_C_AtomicStorageOps : I32EnumAttrCase<"AtomicStorageOps", 4445> { 547 list<Availability> availability = [ 548 Extension<[SPV_KHR_shader_atomic_counter_ops]> 549 ]; 550} 551def SPIRV_C_SampleMaskPostDepthCoverage : I32EnumAttrCase<"SampleMaskPostDepthCoverage", 4447> { 552 list<Availability> availability = [ 553 Extension<[SPV_KHR_post_depth_coverage]> 554 ]; 555} 556def SPIRV_C_StorageBuffer8BitAccess : I32EnumAttrCase<"StorageBuffer8BitAccess", 4448> { 557 list<Availability> availability = [ 558 Extension<[SPV_KHR_8bit_storage]> 559 ]; 560} 561def SPIRV_C_StoragePushConstant8 : I32EnumAttrCase<"StoragePushConstant8", 4450> { 562 list<Availability> availability = [ 563 Extension<[SPV_KHR_8bit_storage]> 564 ]; 565} 566def SPIRV_C_DenormPreserve : I32EnumAttrCase<"DenormPreserve", 4464> { 567 list<Availability> availability = [ 568 Extension<[SPV_KHR_float_controls]> 569 ]; 570} 571def SPIRV_C_DenormFlushToZero : I32EnumAttrCase<"DenormFlushToZero", 4465> { 572 list<Availability> availability = [ 573 Extension<[SPV_KHR_float_controls]> 574 ]; 575} 576def SPIRV_C_SignedZeroInfNanPreserve : I32EnumAttrCase<"SignedZeroInfNanPreserve", 4466> { 577 list<Availability> availability = [ 578 Extension<[SPV_KHR_float_controls]> 579 ]; 580} 581def SPIRV_C_RoundingModeRTE : I32EnumAttrCase<"RoundingModeRTE", 4467> { 582 list<Availability> availability = [ 583 Extension<[SPV_KHR_float_controls]> 584 ]; 585} 586def SPIRV_C_RoundingModeRTZ : I32EnumAttrCase<"RoundingModeRTZ", 4468> { 587 list<Availability> availability = [ 588 Extension<[SPV_KHR_float_controls]> 589 ]; 590} 591def SPIRV_C_ImageFootprintNV : I32EnumAttrCase<"ImageFootprintNV", 5282> { 592 list<Availability> availability = [ 593 Extension<[SPV_NV_shader_image_footprint]> 594 ]; 595} 596def SPIRV_C_FragmentBarycentricKHR : I32EnumAttrCase<"FragmentBarycentricKHR", 5284> { 597 list<Availability> availability = [ 598 Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]> 599 ]; 600} 601def SPIRV_C_ComputeDerivativeGroupQuadsNV : I32EnumAttrCase<"ComputeDerivativeGroupQuadsNV", 5288> { 602 list<Availability> availability = [ 603 Extension<[SPV_NV_compute_shader_derivatives]> 604 ]; 605} 606def SPIRV_C_GroupNonUniformPartitionedNV : I32EnumAttrCase<"GroupNonUniformPartitionedNV", 5297> { 607 list<Availability> availability = [ 608 Extension<[SPV_NV_shader_subgroup_partitioned]> 609 ]; 610} 611def SPIRV_C_VulkanMemoryModel : I32EnumAttrCase<"VulkanMemoryModel", 5345> { 612 list<Availability> availability = [ 613 MinVersion<SPIRV_V_1_5> 614 ]; 615} 616def SPIRV_C_VulkanMemoryModelDeviceScope : I32EnumAttrCase<"VulkanMemoryModelDeviceScope", 5346> { 617 list<Availability> availability = [ 618 MinVersion<SPIRV_V_1_5> 619 ]; 620} 621def SPIRV_C_ComputeDerivativeGroupLinearNV : I32EnumAttrCase<"ComputeDerivativeGroupLinearNV", 5350> { 622 list<Availability> availability = [ 623 Extension<[SPV_NV_compute_shader_derivatives]> 624 ]; 625} 626def SPIRV_C_BindlessTextureNV : I32EnumAttrCase<"BindlessTextureNV", 5390> { 627 list<Availability> availability = [ 628 Extension<[SPV_NV_bindless_texture]> 629 ]; 630} 631def SPIRV_C_SubgroupShuffleINTEL : I32EnumAttrCase<"SubgroupShuffleINTEL", 5568> { 632 list<Availability> availability = [ 633 Extension<[SPV_INTEL_subgroups]> 634 ]; 635} 636def SPIRV_C_SubgroupBufferBlockIOINTEL : I32EnumAttrCase<"SubgroupBufferBlockIOINTEL", 5569> { 637 list<Availability> availability = [ 638 Extension<[SPV_INTEL_subgroups]> 639 ]; 640} 641def SPIRV_C_SubgroupImageBlockIOINTEL : I32EnumAttrCase<"SubgroupImageBlockIOINTEL", 5570> { 642 list<Availability> availability = [ 643 Extension<[SPV_INTEL_subgroups]> 644 ]; 645} 646def SPIRV_C_SubgroupImageMediaBlockIOINTEL : I32EnumAttrCase<"SubgroupImageMediaBlockIOINTEL", 5579> { 647 list<Availability> availability = [ 648 Extension<[SPV_INTEL_media_block_io]> 649 ]; 650} 651def SPIRV_C_RoundToInfinityINTEL : I32EnumAttrCase<"RoundToInfinityINTEL", 5582> { 652 list<Availability> availability = [ 653 Extension<[SPV_INTEL_float_controls2]> 654 ]; 655} 656def SPIRV_C_FloatingPointModeINTEL : I32EnumAttrCase<"FloatingPointModeINTEL", 5583> { 657 list<Availability> availability = [ 658 Extension<[SPV_INTEL_float_controls2]> 659 ]; 660} 661def SPIRV_C_FunctionPointersINTEL : I32EnumAttrCase<"FunctionPointersINTEL", 5603> { 662 list<Availability> availability = [ 663 Extension<[SPV_INTEL_function_pointers]> 664 ]; 665} 666def SPIRV_C_IndirectReferencesINTEL : I32EnumAttrCase<"IndirectReferencesINTEL", 5604> { 667 list<Availability> availability = [ 668 Extension<[SPV_INTEL_function_pointers]> 669 ]; 670} 671def SPIRV_C_AsmINTEL : I32EnumAttrCase<"AsmINTEL", 5606> { 672 list<Availability> availability = [ 673 Extension<[SPV_INTEL_inline_assembly]> 674 ]; 675} 676def SPIRV_C_AtomicFloat32MinMaxEXT : I32EnumAttrCase<"AtomicFloat32MinMaxEXT", 5612> { 677 list<Availability> availability = [ 678 Extension<[SPV_EXT_shader_atomic_float_min_max]> 679 ]; 680} 681def SPIRV_C_AtomicFloat64MinMaxEXT : I32EnumAttrCase<"AtomicFloat64MinMaxEXT", 5613> { 682 list<Availability> availability = [ 683 Extension<[SPV_EXT_shader_atomic_float_min_max]> 684 ]; 685} 686def SPIRV_C_AtomicFloat16MinMaxEXT : I32EnumAttrCase<"AtomicFloat16MinMaxEXT", 5616> { 687 list<Availability> availability = [ 688 Extension<[SPV_EXT_shader_atomic_float_min_max]> 689 ]; 690} 691def SPIRV_C_VectorAnyINTEL : I32EnumAttrCase<"VectorAnyINTEL", 5619> { 692 list<Availability> availability = [ 693 Extension<[SPV_INTEL_vector_compute]> 694 ]; 695} 696def SPIRV_C_ExpectAssumeKHR : I32EnumAttrCase<"ExpectAssumeKHR", 5629> { 697 list<Availability> availability = [ 698 Extension<[SPV_KHR_expect_assume]> 699 ]; 700} 701def SPIRV_C_SubgroupAvcMotionEstimationINTEL : I32EnumAttrCase<"SubgroupAvcMotionEstimationINTEL", 5696> { 702 list<Availability> availability = [ 703 Extension<[SPV_INTEL_device_side_avc_motion_estimation]> 704 ]; 705} 706def SPIRV_C_SubgroupAvcMotionEstimationIntraINTEL : I32EnumAttrCase<"SubgroupAvcMotionEstimationIntraINTEL", 5697> { 707 list<Availability> availability = [ 708 Extension<[SPV_INTEL_device_side_avc_motion_estimation]> 709 ]; 710} 711def SPIRV_C_SubgroupAvcMotionEstimationChromaINTEL : I32EnumAttrCase<"SubgroupAvcMotionEstimationChromaINTEL", 5698> { 712 list<Availability> availability = [ 713 Extension<[SPV_INTEL_device_side_avc_motion_estimation]> 714 ]; 715} 716def SPIRV_C_VariableLengthArrayINTEL : I32EnumAttrCase<"VariableLengthArrayINTEL", 5817> { 717 list<Availability> availability = [ 718 Extension<[SPV_INTEL_variable_length_array]> 719 ]; 720} 721def SPIRV_C_FunctionFloatControlINTEL : I32EnumAttrCase<"FunctionFloatControlINTEL", 5821> { 722 list<Availability> availability = [ 723 Extension<[SPV_INTEL_float_controls2]> 724 ]; 725} 726def SPIRV_C_FPGAMemoryAttributesINTEL : I32EnumAttrCase<"FPGAMemoryAttributesINTEL", 5824> { 727 list<Availability> availability = [ 728 Extension<[SPV_INTEL_fpga_memory_attributes]> 729 ]; 730} 731def SPIRV_C_ArbitraryPrecisionIntegersINTEL : I32EnumAttrCase<"ArbitraryPrecisionIntegersINTEL", 5844> { 732 list<Availability> availability = [ 733 Extension<[SPV_INTEL_arbitrary_precision_integers]> 734 ]; 735} 736def SPIRV_C_ArbitraryPrecisionFloatingPointINTEL : I32EnumAttrCase<"ArbitraryPrecisionFloatingPointINTEL", 5845> { 737 list<Availability> availability = [ 738 Extension<[SPV_INTEL_arbitrary_precision_floating_point]> 739 ]; 740} 741def SPIRV_C_UnstructuredLoopControlsINTEL : I32EnumAttrCase<"UnstructuredLoopControlsINTEL", 5886> { 742 list<Availability> availability = [ 743 Extension<[SPV_INTEL_unstructured_loop_controls]> 744 ]; 745} 746def SPIRV_C_FPGALoopControlsINTEL : I32EnumAttrCase<"FPGALoopControlsINTEL", 5888> { 747 list<Availability> availability = [ 748 Extension<[SPV_INTEL_fpga_loop_controls]> 749 ]; 750} 751def SPIRV_C_KernelAttributesINTEL : I32EnumAttrCase<"KernelAttributesINTEL", 5892> { 752 list<Availability> availability = [ 753 Extension<[SPV_INTEL_kernel_attributes]> 754 ]; 755} 756def SPIRV_C_FPGAKernelAttributesINTEL : I32EnumAttrCase<"FPGAKernelAttributesINTEL", 5897> { 757 list<Availability> availability = [ 758 Extension<[SPV_INTEL_kernel_attributes]> 759 ]; 760} 761def SPIRV_C_FPGAMemoryAccessesINTEL : I32EnumAttrCase<"FPGAMemoryAccessesINTEL", 5898> { 762 list<Availability> availability = [ 763 Extension<[SPV_INTEL_fpga_memory_accesses]> 764 ]; 765} 766def SPIRV_C_FPGAClusterAttributesINTEL : I32EnumAttrCase<"FPGAClusterAttributesINTEL", 5904> { 767 list<Availability> availability = [ 768 Extension<[SPV_INTEL_fpga_cluster_attributes]> 769 ]; 770} 771def SPIRV_C_LoopFuseINTEL : I32EnumAttrCase<"LoopFuseINTEL", 5906> { 772 list<Availability> availability = [ 773 Extension<[SPV_INTEL_loop_fuse]> 774 ]; 775} 776def SPIRV_C_MemoryAccessAliasingINTEL : I32EnumAttrCase<"MemoryAccessAliasingINTEL", 5910> { 777 list<Availability> availability = [ 778 Extension<[SPV_INTEL_memory_access_aliasing]> 779 ]; 780} 781def SPIRV_C_FPGABufferLocationINTEL : I32EnumAttrCase<"FPGABufferLocationINTEL", 5920> { 782 list<Availability> availability = [ 783 Extension<[SPV_INTEL_fpga_buffer_location]> 784 ]; 785} 786def SPIRV_C_ArbitraryPrecisionFixedPointINTEL : I32EnumAttrCase<"ArbitraryPrecisionFixedPointINTEL", 5922> { 787 list<Availability> availability = [ 788 Extension<[SPV_INTEL_arbitrary_precision_fixed_point]> 789 ]; 790} 791def SPIRV_C_USMStorageClassesINTEL : I32EnumAttrCase<"USMStorageClassesINTEL", 5935> { 792 list<Availability> availability = [ 793 Extension<[SPV_INTEL_usm_storage_classes]> 794 ]; 795} 796def SPIRV_C_IOPipesINTEL : I32EnumAttrCase<"IOPipesINTEL", 5943> { 797 list<Availability> availability = [ 798 Extension<[SPV_INTEL_io_pipes]> 799 ]; 800} 801def SPIRV_C_BlockingPipesINTEL : I32EnumAttrCase<"BlockingPipesINTEL", 5945> { 802 list<Availability> availability = [ 803 Extension<[SPV_INTEL_blocking_pipes]> 804 ]; 805} 806def SPIRV_C_FPGARegINTEL : I32EnumAttrCase<"FPGARegINTEL", 5948> { 807 list<Availability> availability = [ 808 Extension<[SPV_INTEL_fpga_reg]> 809 ]; 810} 811def SPIRV_C_DotProductInputAll : I32EnumAttrCase<"DotProductInputAll", 6016> { 812 list<Availability> availability = [ 813 Extension<[SPV_KHR_integer_dot_product]>, 814 MinVersion<SPIRV_V_1_6> 815 ]; 816} 817def SPIRV_C_DotProductInput4x8Bit : I32EnumAttrCase<"DotProductInput4x8Bit", 6017> { 818 list<I32EnumAttrCase> implies = [SPIRV_C_Int8]; 819 list<Availability> availability = [ 820 Extension<[SPV_KHR_integer_dot_product]>, 821 MinVersion<SPIRV_V_1_6> 822 ]; 823} 824def SPIRV_C_DotProductInput4x8BitPacked : I32EnumAttrCase<"DotProductInput4x8BitPacked", 6018> { 825 list<Availability> availability = [ 826 Extension<[SPV_KHR_integer_dot_product]>, 827 MinVersion<SPIRV_V_1_6> 828 ]; 829} 830def SPIRV_C_DotProduct : I32EnumAttrCase<"DotProduct", 6019> { 831 list<Availability> availability = [ 832 Extension<[SPV_KHR_integer_dot_product]>, 833 MinVersion<SPIRV_V_1_6> 834 ]; 835} 836def SPIRV_C_RayCullMaskKHR : I32EnumAttrCase<"RayCullMaskKHR", 6020> { 837 list<Availability> availability = [ 838 Extension<[SPV_KHR_ray_cull_mask]> 839 ]; 840} 841def SPIRV_C_CooperativeMatrixKHR : I32EnumAttrCase<"CooperativeMatrixKHR", 6022> { 842 list<Availability> availability = [ 843 Extension<[SPV_KHR_cooperative_matrix]>, 844 MinVersion<SPIRV_V_1_6> 845 ]; 846} 847def SPIRV_C_BitInstructions : I32EnumAttrCase<"BitInstructions", 6025> { 848 list<Availability> availability = [ 849 Extension<[SPV_KHR_bit_instructions]> 850 ]; 851} 852def SPIRV_C_AtomicFloat32AddEXT : I32EnumAttrCase<"AtomicFloat32AddEXT", 6033> { 853 list<Availability> availability = [ 854 Extension<[SPV_EXT_shader_atomic_float_add]> 855 ]; 856} 857def SPIRV_C_AtomicFloat64AddEXT : I32EnumAttrCase<"AtomicFloat64AddEXT", 6034> { 858 list<Availability> availability = [ 859 Extension<[SPV_EXT_shader_atomic_float_add]> 860 ]; 861} 862def SPIRV_C_LongConstantCompositeINTEL : I32EnumAttrCase<"LongConstantCompositeINTEL", 6089> { 863 list<Availability> availability = [ 864 Extension<[SPV_INTEL_long_constant_composite]> 865 ]; 866} 867def SPIRV_C_OptNoneINTEL : I32EnumAttrCase<"OptNoneINTEL", 6094> { 868 list<Availability> availability = [ 869 Extension<[SPV_INTEL_optnone]> 870 ]; 871} 872def SPIRV_C_AtomicFloat16AddEXT : I32EnumAttrCase<"AtomicFloat16AddEXT", 6095> { 873 list<Availability> availability = [ 874 Extension<[SPV_EXT_shader_atomic_float16_add]> 875 ]; 876} 877def SPIRV_C_DebugInfoModuleINTEL : I32EnumAttrCase<"DebugInfoModuleINTEL", 6114> { 878 list<Availability> availability = [ 879 Extension<[SPV_INTEL_debug_module]> 880 ]; 881} 882def SPIRV_C_SplitBarrierINTEL : I32EnumAttrCase<"SplitBarrierINTEL", 6141> { 883 list<Availability> availability = [ 884 Extension<[SPV_INTEL_split_barrier]> 885 ]; 886} 887def SPIRV_C_GroupUniformArithmeticKHR : I32EnumAttrCase<"GroupUniformArithmeticKHR", 6400> { 888 list<Availability> availability = [ 889 Extension<[SPV_KHR_uniform_group_instructions]> 890 ]; 891} 892def SPIRV_C_Shader : I32EnumAttrCase<"Shader", 1> { 893 list<I32EnumAttrCase> implies = [SPIRV_C_Matrix]; 894} 895def SPIRV_C_Vector16 : I32EnumAttrCase<"Vector16", 7> { 896 list<I32EnumAttrCase> implies = [SPIRV_C_Kernel]; 897} 898def SPIRV_C_Float16Buffer : I32EnumAttrCase<"Float16Buffer", 8> { 899 list<I32EnumAttrCase> implies = [SPIRV_C_Kernel]; 900} 901def SPIRV_C_Int64Atomics : I32EnumAttrCase<"Int64Atomics", 12> { 902 list<I32EnumAttrCase> implies = [SPIRV_C_Int64]; 903} 904def SPIRV_C_ImageBasic : I32EnumAttrCase<"ImageBasic", 13> { 905 list<I32EnumAttrCase> implies = [SPIRV_C_Kernel]; 906} 907def SPIRV_C_Pipes : I32EnumAttrCase<"Pipes", 17> { 908 list<I32EnumAttrCase> implies = [SPIRV_C_Kernel]; 909} 910def SPIRV_C_DeviceEnqueue : I32EnumAttrCase<"DeviceEnqueue", 19> { 911 list<I32EnumAttrCase> implies = [SPIRV_C_Kernel]; 912} 913def SPIRV_C_LiteralSampler : I32EnumAttrCase<"LiteralSampler", 20> { 914 list<I32EnumAttrCase> implies = [SPIRV_C_Kernel]; 915} 916def SPIRV_C_GenericPointer : I32EnumAttrCase<"GenericPointer", 38> { 917 list<I32EnumAttrCase> implies = [SPIRV_C_Addresses]; 918} 919def SPIRV_C_Image1D : I32EnumAttrCase<"Image1D", 44> { 920 list<I32EnumAttrCase> implies = [SPIRV_C_Sampled1D]; 921} 922def SPIRV_C_ImageBuffer : I32EnumAttrCase<"ImageBuffer", 47> { 923 list<I32EnumAttrCase> implies = [SPIRV_C_SampledBuffer]; 924} 925def SPIRV_C_NamedBarrier : I32EnumAttrCase<"NamedBarrier", 59> { 926 list<I32EnumAttrCase> implies = [SPIRV_C_Kernel]; 927 list<Availability> availability = [ 928 MinVersion<SPIRV_V_1_1> 929 ]; 930} 931def SPIRV_C_GroupNonUniformVote : I32EnumAttrCase<"GroupNonUniformVote", 62> { 932 list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform]; 933 list<Availability> availability = [ 934 MinVersion<SPIRV_V_1_3> 935 ]; 936} 937def SPIRV_C_GroupNonUniformArithmetic : I32EnumAttrCase<"GroupNonUniformArithmetic", 63> { 938 list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform]; 939 list<Availability> availability = [ 940 MinVersion<SPIRV_V_1_3> 941 ]; 942} 943def SPIRV_C_GroupNonUniformBallot : I32EnumAttrCase<"GroupNonUniformBallot", 64> { 944 list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform]; 945 list<Availability> availability = [ 946 MinVersion<SPIRV_V_1_3> 947 ]; 948} 949def SPIRV_C_GroupNonUniformShuffle : I32EnumAttrCase<"GroupNonUniformShuffle", 65> { 950 list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform]; 951 list<Availability> availability = [ 952 MinVersion<SPIRV_V_1_3> 953 ]; 954} 955def SPIRV_C_GroupNonUniformShuffleRelative : I32EnumAttrCase<"GroupNonUniformShuffleRelative", 66> { 956 list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform]; 957 list<Availability> availability = [ 958 MinVersion<SPIRV_V_1_3> 959 ]; 960} 961def SPIRV_C_GroupNonUniformClustered : I32EnumAttrCase<"GroupNonUniformClustered", 67> { 962 list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform]; 963 list<Availability> availability = [ 964 MinVersion<SPIRV_V_1_3> 965 ]; 966} 967def SPIRV_C_GroupNonUniformQuad : I32EnumAttrCase<"GroupNonUniformQuad", 68> { 968 list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform]; 969 list<Availability> availability = [ 970 MinVersion<SPIRV_V_1_3> 971 ]; 972} 973def SPIRV_C_StorageUniform16 : I32EnumAttrCase<"StorageUniform16", 4434> { 974 list<I32EnumAttrCase> implies = [SPIRV_C_StorageBuffer16BitAccess]; 975 list<Availability> availability = [ 976 Extension<[SPV_KHR_16bit_storage]> 977 ]; 978} 979def SPIRV_C_UniformAndStorageBuffer8BitAccess : I32EnumAttrCase<"UniformAndStorageBuffer8BitAccess", 4449> { 980 list<I32EnumAttrCase> implies = [SPIRV_C_StorageBuffer8BitAccess]; 981 list<Availability> availability = [ 982 Extension<[SPV_KHR_8bit_storage]> 983 ]; 984} 985def SPIRV_C_UniformTexelBufferArrayDynamicIndexing : I32EnumAttrCase<"UniformTexelBufferArrayDynamicIndexing", 5304> { 986 list<I32EnumAttrCase> implies = [SPIRV_C_SampledBuffer]; 987 list<Availability> availability = [ 988 MinVersion<SPIRV_V_1_5> 989 ]; 990} 991def SPIRV_C_VectorComputeINTEL : I32EnumAttrCase<"VectorComputeINTEL", 5617> { 992 list<I32EnumAttrCase> implies = [SPIRV_C_VectorAnyINTEL]; 993 list<Availability> availability = [ 994 Extension<[SPV_INTEL_vector_compute]> 995 ]; 996} 997def SPIRV_C_FPFastMathModeINTEL : I32EnumAttrCase<"FPFastMathModeINTEL", 5837> { 998 list<I32EnumAttrCase> implies = [SPIRV_C_Kernel]; 999 list<Availability> availability = [ 1000 Extension<[SPV_INTEL_fp_fast_math_mode]> 1001 ]; 1002} 1003def SPIRV_C_GroupNonUniformRotateKHR : I32EnumAttrCase<"GroupNonUniformRotateKHR", 6026> { 1004 list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform]; 1005 list<Availability> availability = [ 1006 Extension<[SPV_KHR_subgroup_rotate]> 1007 ]; 1008} 1009def SPIRV_C_Geometry : I32EnumAttrCase<"Geometry", 2> { 1010 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1011} 1012def SPIRV_C_Tessellation : I32EnumAttrCase<"Tessellation", 3> { 1013 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1014} 1015def SPIRV_C_ImageReadWrite : I32EnumAttrCase<"ImageReadWrite", 14> { 1016 list<I32EnumAttrCase> implies = [SPIRV_C_ImageBasic]; 1017} 1018def SPIRV_C_ImageMipmap : I32EnumAttrCase<"ImageMipmap", 15> { 1019 list<I32EnumAttrCase> implies = [SPIRV_C_ImageBasic]; 1020} 1021def SPIRV_C_AtomicStorage : I32EnumAttrCase<"AtomicStorage", 21> { 1022 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1023} 1024def SPIRV_C_ImageGatherExtended : I32EnumAttrCase<"ImageGatherExtended", 25> { 1025 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1026} 1027def SPIRV_C_StorageImageMultisample : I32EnumAttrCase<"StorageImageMultisample", 27> { 1028 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1029} 1030def SPIRV_C_UniformBufferArrayDynamicIndexing : I32EnumAttrCase<"UniformBufferArrayDynamicIndexing", 28> { 1031 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1032} 1033def SPIRV_C_SampledImageArrayDynamicIndexing : I32EnumAttrCase<"SampledImageArrayDynamicIndexing", 29> { 1034 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1035} 1036def SPIRV_C_StorageBufferArrayDynamicIndexing : I32EnumAttrCase<"StorageBufferArrayDynamicIndexing", 30> { 1037 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1038} 1039def SPIRV_C_StorageImageArrayDynamicIndexing : I32EnumAttrCase<"StorageImageArrayDynamicIndexing", 31> { 1040 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1041} 1042def SPIRV_C_ClipDistance : I32EnumAttrCase<"ClipDistance", 32> { 1043 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1044} 1045def SPIRV_C_CullDistance : I32EnumAttrCase<"CullDistance", 33> { 1046 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1047} 1048def SPIRV_C_SampleRateShading : I32EnumAttrCase<"SampleRateShading", 35> { 1049 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1050} 1051def SPIRV_C_SampledRect : I32EnumAttrCase<"SampledRect", 37> { 1052 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1053} 1054def SPIRV_C_InputAttachment : I32EnumAttrCase<"InputAttachment", 40> { 1055 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1056} 1057def SPIRV_C_SparseResidency : I32EnumAttrCase<"SparseResidency", 41> { 1058 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1059} 1060def SPIRV_C_MinLod : I32EnumAttrCase<"MinLod", 42> { 1061 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1062} 1063def SPIRV_C_SampledCubeArray : I32EnumAttrCase<"SampledCubeArray", 45> { 1064 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1065} 1066def SPIRV_C_ImageMSArray : I32EnumAttrCase<"ImageMSArray", 48> { 1067 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1068} 1069def SPIRV_C_StorageImageExtendedFormats : I32EnumAttrCase<"StorageImageExtendedFormats", 49> { 1070 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1071} 1072def SPIRV_C_ImageQuery : I32EnumAttrCase<"ImageQuery", 50> { 1073 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1074} 1075def SPIRV_C_DerivativeControl : I32EnumAttrCase<"DerivativeControl", 51> { 1076 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1077} 1078def SPIRV_C_InterpolationFunction : I32EnumAttrCase<"InterpolationFunction", 52> { 1079 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1080} 1081def SPIRV_C_TransformFeedback : I32EnumAttrCase<"TransformFeedback", 53> { 1082 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1083} 1084def SPIRV_C_StorageImageReadWithoutFormat : I32EnumAttrCase<"StorageImageReadWithoutFormat", 55> { 1085 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1086} 1087def SPIRV_C_StorageImageWriteWithoutFormat : I32EnumAttrCase<"StorageImageWriteWithoutFormat", 56> { 1088 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1089} 1090def SPIRV_C_SubgroupDispatch : I32EnumAttrCase<"SubgroupDispatch", 58> { 1091 list<I32EnumAttrCase> implies = [SPIRV_C_DeviceEnqueue]; 1092 list<Availability> availability = [ 1093 MinVersion<SPIRV_V_1_1> 1094 ]; 1095} 1096def SPIRV_C_PipeStorage : I32EnumAttrCase<"PipeStorage", 60> { 1097 list<I32EnumAttrCase> implies = [SPIRV_C_Pipes]; 1098 list<Availability> availability = [ 1099 MinVersion<SPIRV_V_1_1> 1100 ]; 1101} 1102def SPIRV_C_FragmentShadingRateKHR : I32EnumAttrCase<"FragmentShadingRateKHR", 4422> { 1103 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1104 list<Availability> availability = [ 1105 Extension<[SPV_KHR_fragment_shading_rate]> 1106 ]; 1107} 1108def SPIRV_C_DrawParameters : I32EnumAttrCase<"DrawParameters", 4427> { 1109 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1110 list<Availability> availability = [ 1111 Extension<[SPV_KHR_shader_draw_parameters]> 1112 ]; 1113} 1114def SPIRV_C_WorkgroupMemoryExplicitLayoutKHR : I32EnumAttrCase<"WorkgroupMemoryExplicitLayoutKHR", 4428> { 1115 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1116 list<Availability> availability = [ 1117 Extension<[SPV_KHR_workgroup_memory_explicit_layout]> 1118 ]; 1119} 1120def SPIRV_C_WorkgroupMemoryExplicitLayout16BitAccessKHR : I32EnumAttrCase<"WorkgroupMemoryExplicitLayout16BitAccessKHR", 4430> { 1121 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1122 list<Availability> availability = [ 1123 Extension<[SPV_KHR_workgroup_memory_explicit_layout]> 1124 ]; 1125} 1126def SPIRV_C_MultiView : I32EnumAttrCase<"MultiView", 4439> { 1127 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1128 list<Availability> availability = [ 1129 Extension<[SPV_KHR_multiview]> 1130 ]; 1131} 1132def SPIRV_C_VariablePointersStorageBuffer : I32EnumAttrCase<"VariablePointersStorageBuffer", 4441> { 1133 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1134 list<Availability> availability = [ 1135 Extension<[SPV_KHR_variable_pointers]> 1136 ]; 1137} 1138def SPIRV_C_RayQueryProvisionalKHR : I32EnumAttrCase<"RayQueryProvisionalKHR", 4471> { 1139 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1140 list<Availability> availability = [ 1141 Extension<[SPV_KHR_ray_query]> 1142 ]; 1143} 1144def SPIRV_C_RayQueryKHR : I32EnumAttrCase<"RayQueryKHR", 4472> { 1145 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1146 list<Availability> availability = [ 1147 Extension<[SPV_KHR_ray_query]> 1148 ]; 1149} 1150def SPIRV_C_RayTracingKHR : I32EnumAttrCase<"RayTracingKHR", 4479> { 1151 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1152 list<Availability> availability = [ 1153 Extension<[SPV_KHR_ray_tracing]> 1154 ]; 1155} 1156def SPIRV_C_Float16ImageAMD : I32EnumAttrCase<"Float16ImageAMD", 5008> { 1157 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1158 list<Availability> availability = [ 1159 Extension<[SPV_AMD_gpu_shader_half_float_fetch]> 1160 ]; 1161} 1162def SPIRV_C_ImageGatherBiasLodAMD : I32EnumAttrCase<"ImageGatherBiasLodAMD", 5009> { 1163 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1164 list<Availability> availability = [ 1165 Extension<[SPV_AMD_texture_gather_bias_lod]> 1166 ]; 1167} 1168def SPIRV_C_FragmentMaskAMD : I32EnumAttrCase<"FragmentMaskAMD", 5010> { 1169 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1170 list<Availability> availability = [ 1171 Extension<[SPV_AMD_shader_fragment_mask]> 1172 ]; 1173} 1174def SPIRV_C_StencilExportEXT : I32EnumAttrCase<"StencilExportEXT", 5013> { 1175 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1176 list<Availability> availability = [ 1177 Extension<[SPV_EXT_shader_stencil_export]> 1178 ]; 1179} 1180def SPIRV_C_ImageReadWriteLodAMD : I32EnumAttrCase<"ImageReadWriteLodAMD", 5015> { 1181 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1182 list<Availability> availability = [ 1183 Extension<[SPV_AMD_shader_image_load_store_lod]> 1184 ]; 1185} 1186def SPIRV_C_Int64ImageEXT : I32EnumAttrCase<"Int64ImageEXT", 5016> { 1187 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1188 list<Availability> availability = [ 1189 Extension<[SPV_EXT_shader_image_int64]> 1190 ]; 1191} 1192def SPIRV_C_ShaderClockKHR : I32EnumAttrCase<"ShaderClockKHR", 5055> { 1193 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1194 list<Availability> availability = [ 1195 Extension<[SPV_KHR_shader_clock]> 1196 ]; 1197} 1198def SPIRV_C_FragmentFullyCoveredEXT : I32EnumAttrCase<"FragmentFullyCoveredEXT", 5265> { 1199 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1200 list<Availability> availability = [ 1201 Extension<[SPV_EXT_fragment_fully_covered]> 1202 ]; 1203} 1204def SPIRV_C_MeshShadingNV : I32EnumAttrCase<"MeshShadingNV", 5266> { 1205 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1206 list<Availability> availability = [ 1207 Extension<[SPV_NV_mesh_shader]> 1208 ]; 1209} 1210def SPIRV_C_FragmentDensityEXT : I32EnumAttrCase<"FragmentDensityEXT", 5291> { 1211 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1212 list<Availability> availability = [ 1213 Extension<[SPV_EXT_fragment_invocation_density, SPV_NV_shading_rate]> 1214 ]; 1215} 1216def SPIRV_C_ShaderNonUniform : I32EnumAttrCase<"ShaderNonUniform", 5301> { 1217 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1218 list<Availability> availability = [ 1219 MinVersion<SPIRV_V_1_5> 1220 ]; 1221} 1222def SPIRV_C_RuntimeDescriptorArray : I32EnumAttrCase<"RuntimeDescriptorArray", 5302> { 1223 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1224 list<Availability> availability = [ 1225 MinVersion<SPIRV_V_1_5> 1226 ]; 1227} 1228def SPIRV_C_StorageTexelBufferArrayDynamicIndexing : I32EnumAttrCase<"StorageTexelBufferArrayDynamicIndexing", 5305> { 1229 list<I32EnumAttrCase> implies = [SPIRV_C_ImageBuffer]; 1230 list<Availability> availability = [ 1231 MinVersion<SPIRV_V_1_5> 1232 ]; 1233} 1234def SPIRV_C_RayTracingNV : I32EnumAttrCase<"RayTracingNV", 5340> { 1235 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1236 list<Availability> availability = [ 1237 Extension<[SPV_NV_ray_tracing]> 1238 ]; 1239} 1240def SPIRV_C_RayTracingMotionBlurNV : I32EnumAttrCase<"RayTracingMotionBlurNV", 5341> { 1241 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1242 list<Availability> availability = [ 1243 Extension<[SPV_NV_ray_tracing_motion_blur]> 1244 ]; 1245} 1246def SPIRV_C_PhysicalStorageBufferAddresses : I32EnumAttrCase<"PhysicalStorageBufferAddresses", 5347> { 1247 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1248 list<Availability> availability = [ 1249 Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]> 1250 ]; 1251} 1252def SPIRV_C_RayTracingProvisionalKHR : I32EnumAttrCase<"RayTracingProvisionalKHR", 5353> { 1253 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1254 list<Availability> availability = [ 1255 Extension<[SPV_KHR_ray_tracing]> 1256 ]; 1257} 1258def SPIRV_C_FragmentShaderSampleInterlockEXT : I32EnumAttrCase<"FragmentShaderSampleInterlockEXT", 5363> { 1259 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1260 list<Availability> availability = [ 1261 Extension<[SPV_EXT_fragment_shader_interlock]> 1262 ]; 1263} 1264def SPIRV_C_FragmentShaderShadingRateInterlockEXT : I32EnumAttrCase<"FragmentShaderShadingRateInterlockEXT", 5372> { 1265 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1266 list<Availability> availability = [ 1267 Extension<[SPV_EXT_fragment_shader_interlock]> 1268 ]; 1269} 1270def SPIRV_C_ShaderSMBuiltinsNV : I32EnumAttrCase<"ShaderSMBuiltinsNV", 5373> { 1271 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1272 list<Availability> availability = [ 1273 Extension<[SPV_NV_shader_sm_builtins]> 1274 ]; 1275} 1276def SPIRV_C_FragmentShaderPixelInterlockEXT : I32EnumAttrCase<"FragmentShaderPixelInterlockEXT", 5378> { 1277 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1278 list<Availability> availability = [ 1279 Extension<[SPV_EXT_fragment_shader_interlock]> 1280 ]; 1281} 1282def SPIRV_C_DemoteToHelperInvocation : I32EnumAttrCase<"DemoteToHelperInvocation", 5379> { 1283 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1284 list<Availability> availability = [ 1285 MinVersion<SPIRV_V_1_6> 1286 ]; 1287} 1288def SPIRV_C_IntegerFunctions2INTEL : I32EnumAttrCase<"IntegerFunctions2INTEL", 5584> { 1289 list<I32EnumAttrCase> implies = [SPIRV_C_Shader]; 1290 list<Availability> availability = [ 1291 Extension<[SPV_INTEL_shader_integer_functions2]> 1292 ]; 1293} 1294def SPIRV_C_TessellationPointSize : I32EnumAttrCase<"TessellationPointSize", 23> { 1295 list<I32EnumAttrCase> implies = [SPIRV_C_Tessellation]; 1296} 1297def SPIRV_C_GeometryPointSize : I32EnumAttrCase<"GeometryPointSize", 24> { 1298 list<I32EnumAttrCase> implies = [SPIRV_C_Geometry]; 1299} 1300def SPIRV_C_ImageCubeArray : I32EnumAttrCase<"ImageCubeArray", 34> { 1301 list<I32EnumAttrCase> implies = [SPIRV_C_SampledCubeArray]; 1302} 1303def SPIRV_C_ImageRect : I32EnumAttrCase<"ImageRect", 36> { 1304 list<I32EnumAttrCase> implies = [SPIRV_C_SampledRect]; 1305} 1306def SPIRV_C_GeometryStreams : I32EnumAttrCase<"GeometryStreams", 54> { 1307 list<I32EnumAttrCase> implies = [SPIRV_C_Geometry]; 1308} 1309def SPIRV_C_MultiViewport : I32EnumAttrCase<"MultiViewport", 57> { 1310 list<I32EnumAttrCase> implies = [SPIRV_C_Geometry]; 1311} 1312def SPIRV_C_WorkgroupMemoryExplicitLayout8BitAccessKHR : I32EnumAttrCase<"WorkgroupMemoryExplicitLayout8BitAccessKHR", 4429> { 1313 list<I32EnumAttrCase> implies = [SPIRV_C_WorkgroupMemoryExplicitLayoutKHR]; 1314 list<Availability> availability = [ 1315 Extension<[SPV_KHR_workgroup_memory_explicit_layout]> 1316 ]; 1317} 1318def SPIRV_C_VariablePointers : I32EnumAttrCase<"VariablePointers", 4442> { 1319 list<I32EnumAttrCase> implies = [SPIRV_C_VariablePointersStorageBuffer]; 1320 list<Availability> availability = [ 1321 Extension<[SPV_KHR_variable_pointers]> 1322 ]; 1323} 1324def SPIRV_C_RayTraversalPrimitiveCullingKHR : I32EnumAttrCase<"RayTraversalPrimitiveCullingKHR", 4478> { 1325 list<I32EnumAttrCase> implies = [SPIRV_C_RayQueryKHR, SPIRV_C_RayTracingKHR]; 1326 list<Availability> availability = [ 1327 Extension<[SPV_KHR_ray_query, SPV_KHR_ray_tracing]> 1328 ]; 1329} 1330def SPIRV_C_SampleMaskOverrideCoverageNV : I32EnumAttrCase<"SampleMaskOverrideCoverageNV", 5249> { 1331 list<I32EnumAttrCase> implies = [SPIRV_C_SampleRateShading]; 1332 list<Availability> availability = [ 1333 Extension<[SPV_NV_sample_mask_override_coverage]> 1334 ]; 1335} 1336def SPIRV_C_GeometryShaderPassthroughNV : I32EnumAttrCase<"GeometryShaderPassthroughNV", 5251> { 1337 list<I32EnumAttrCase> implies = [SPIRV_C_Geometry]; 1338 list<Availability> availability = [ 1339 Extension<[SPV_NV_geometry_shader_passthrough]> 1340 ]; 1341} 1342def SPIRV_C_PerViewAttributesNV : I32EnumAttrCase<"PerViewAttributesNV", 5260> { 1343 list<I32EnumAttrCase> implies = [SPIRV_C_MultiView]; 1344 list<Availability> availability = [ 1345 Extension<[SPV_NVX_multiview_per_view_attributes]> 1346 ]; 1347} 1348def SPIRV_C_InputAttachmentArrayDynamicIndexing : I32EnumAttrCase<"InputAttachmentArrayDynamicIndexing", 5303> { 1349 list<I32EnumAttrCase> implies = [SPIRV_C_InputAttachment]; 1350 list<Availability> availability = [ 1351 MinVersion<SPIRV_V_1_5> 1352 ]; 1353} 1354def SPIRV_C_UniformBufferArrayNonUniformIndexing : I32EnumAttrCase<"UniformBufferArrayNonUniformIndexing", 5306> { 1355 list<I32EnumAttrCase> implies = [SPIRV_C_ShaderNonUniform]; 1356 list<Availability> availability = [ 1357 MinVersion<SPIRV_V_1_5> 1358 ]; 1359} 1360def SPIRV_C_SampledImageArrayNonUniformIndexing : I32EnumAttrCase<"SampledImageArrayNonUniformIndexing", 5307> { 1361 list<I32EnumAttrCase> implies = [SPIRV_C_ShaderNonUniform]; 1362 list<Availability> availability = [ 1363 MinVersion<SPIRV_V_1_5> 1364 ]; 1365} 1366def SPIRV_C_StorageBufferArrayNonUniformIndexing : I32EnumAttrCase<"StorageBufferArrayNonUniformIndexing", 5308> { 1367 list<I32EnumAttrCase> implies = [SPIRV_C_ShaderNonUniform]; 1368 list<Availability> availability = [ 1369 MinVersion<SPIRV_V_1_5> 1370 ]; 1371} 1372def SPIRV_C_StorageImageArrayNonUniformIndexing : I32EnumAttrCase<"StorageImageArrayNonUniformIndexing", 5309> { 1373 list<I32EnumAttrCase> implies = [SPIRV_C_ShaderNonUniform]; 1374 list<Availability> availability = [ 1375 MinVersion<SPIRV_V_1_5> 1376 ]; 1377} 1378def SPIRV_C_InputAttachmentArrayNonUniformIndexing : I32EnumAttrCase<"InputAttachmentArrayNonUniformIndexing", 5310> { 1379 list<I32EnumAttrCase> implies = [SPIRV_C_InputAttachment, SPIRV_C_ShaderNonUniform]; 1380 list<Availability> availability = [ 1381 MinVersion<SPIRV_V_1_5> 1382 ]; 1383} 1384def SPIRV_C_UniformTexelBufferArrayNonUniformIndexing : I32EnumAttrCase<"UniformTexelBufferArrayNonUniformIndexing", 5311> { 1385 list<I32EnumAttrCase> implies = [SPIRV_C_SampledBuffer, SPIRV_C_ShaderNonUniform]; 1386 list<Availability> availability = [ 1387 MinVersion<SPIRV_V_1_5> 1388 ]; 1389} 1390def SPIRV_C_StorageTexelBufferArrayNonUniformIndexing : I32EnumAttrCase<"StorageTexelBufferArrayNonUniformIndexing", 5312> { 1391 list<I32EnumAttrCase> implies = [SPIRV_C_ImageBuffer, SPIRV_C_ShaderNonUniform]; 1392 list<Availability> availability = [ 1393 MinVersion<SPIRV_V_1_5> 1394 ]; 1395} 1396def SPIRV_C_ShaderViewportIndexLayerEXT : I32EnumAttrCase<"ShaderViewportIndexLayerEXT", 5254> { 1397 list<I32EnumAttrCase> implies = [SPIRV_C_MultiViewport]; 1398 list<Availability> availability = [ 1399 Extension<[SPV_EXT_shader_viewport_index_layer]> 1400 ]; 1401} 1402def SPIRV_C_ShaderViewportMaskNV : I32EnumAttrCase<"ShaderViewportMaskNV", 5255> { 1403 list<I32EnumAttrCase> implies = [SPIRV_C_ShaderViewportIndexLayerEXT]; 1404 list<Availability> availability = [ 1405 Extension<[SPV_NV_viewport_array2]> 1406 ]; 1407} 1408def SPIRV_C_ShaderStereoViewNV : I32EnumAttrCase<"ShaderStereoViewNV", 5259> { 1409 list<I32EnumAttrCase> implies = [SPIRV_C_ShaderViewportMaskNV]; 1410 list<Availability> availability = [ 1411 Extension<[SPV_NV_stereo_view_rendering]> 1412 ]; 1413} 1414 1415def SPIRV_C_Bfloat16ConversionINTEL : I32EnumAttrCase<"Bfloat16ConversionINTEL", 6115> { 1416 list<Availability> availability = [ 1417 Extension<[SPV_INTEL_bfloat16_conversion]> 1418 ]; 1419} 1420 1421def SPIRV_C_CacheControlsINTEL : I32EnumAttrCase<"CacheControlsINTEL", 6441> { 1422 list<Availability> availability = [ 1423 Extension<[SPV_INTEL_cache_controls]> 1424 ]; 1425} 1426 1427def SPIRV_CapabilityAttr : 1428 SPIRV_I32EnumAttr<"Capability", "valid SPIR-V Capability", "capability", [ 1429 SPIRV_C_Matrix, SPIRV_C_Addresses, SPIRV_C_Linkage, SPIRV_C_Kernel, SPIRV_C_Float16, 1430 SPIRV_C_Float64, SPIRV_C_Int64, SPIRV_C_Groups, SPIRV_C_Int16, SPIRV_C_Int8, 1431 SPIRV_C_Sampled1D, SPIRV_C_SampledBuffer, SPIRV_C_GroupNonUniform, SPIRV_C_ShaderLayer, 1432 SPIRV_C_ShaderViewportIndex, SPIRV_C_UniformDecoration, SPIRV_C_SubgroupBallotKHR, 1433 SPIRV_C_SubgroupVoteKHR, SPIRV_C_StorageBuffer16BitAccess, 1434 SPIRV_C_StoragePushConstant16, SPIRV_C_StorageInputOutput16, SPIRV_C_DeviceGroup, 1435 SPIRV_C_AtomicStorageOps, SPIRV_C_SampleMaskPostDepthCoverage, 1436 SPIRV_C_StorageBuffer8BitAccess, SPIRV_C_StoragePushConstant8, 1437 SPIRV_C_DenormPreserve, SPIRV_C_DenormFlushToZero, SPIRV_C_SignedZeroInfNanPreserve, 1438 SPIRV_C_RoundingModeRTE, SPIRV_C_RoundingModeRTZ, SPIRV_C_ImageFootprintNV, 1439 SPIRV_C_FragmentBarycentricKHR, SPIRV_C_ComputeDerivativeGroupQuadsNV, 1440 SPIRV_C_GroupNonUniformPartitionedNV, SPIRV_C_VulkanMemoryModel, 1441 SPIRV_C_VulkanMemoryModelDeviceScope, SPIRV_C_ComputeDerivativeGroupLinearNV, 1442 SPIRV_C_BindlessTextureNV, SPIRV_C_SubgroupShuffleINTEL, 1443 SPIRV_C_SubgroupBufferBlockIOINTEL, SPIRV_C_SubgroupImageBlockIOINTEL, 1444 SPIRV_C_SubgroupImageMediaBlockIOINTEL, SPIRV_C_RoundToInfinityINTEL, 1445 SPIRV_C_FloatingPointModeINTEL, SPIRV_C_FunctionPointersINTEL, 1446 SPIRV_C_IndirectReferencesINTEL, SPIRV_C_AsmINTEL, SPIRV_C_AtomicFloat32MinMaxEXT, 1447 SPIRV_C_AtomicFloat64MinMaxEXT, SPIRV_C_AtomicFloat16MinMaxEXT, 1448 SPIRV_C_VectorAnyINTEL, SPIRV_C_ExpectAssumeKHR, 1449 SPIRV_C_SubgroupAvcMotionEstimationINTEL, 1450 SPIRV_C_SubgroupAvcMotionEstimationIntraINTEL, 1451 SPIRV_C_SubgroupAvcMotionEstimationChromaINTEL, SPIRV_C_VariableLengthArrayINTEL, 1452 SPIRV_C_FunctionFloatControlINTEL, SPIRV_C_FPGAMemoryAttributesINTEL, 1453 SPIRV_C_ArbitraryPrecisionIntegersINTEL, 1454 SPIRV_C_ArbitraryPrecisionFloatingPointINTEL, 1455 SPIRV_C_UnstructuredLoopControlsINTEL, SPIRV_C_FPGALoopControlsINTEL, 1456 SPIRV_C_KernelAttributesINTEL, SPIRV_C_FPGAKernelAttributesINTEL, 1457 SPIRV_C_FPGAMemoryAccessesINTEL, SPIRV_C_FPGAClusterAttributesINTEL, 1458 SPIRV_C_LoopFuseINTEL, SPIRV_C_MemoryAccessAliasingINTEL, 1459 SPIRV_C_FPGABufferLocationINTEL, SPIRV_C_ArbitraryPrecisionFixedPointINTEL, 1460 SPIRV_C_USMStorageClassesINTEL, SPIRV_C_IOPipesINTEL, SPIRV_C_BlockingPipesINTEL, 1461 SPIRV_C_FPGARegINTEL, SPIRV_C_DotProductInputAll, 1462 SPIRV_C_DotProductInput4x8BitPacked, SPIRV_C_DotProduct, SPIRV_C_RayCullMaskKHR, 1463 SPIRV_C_CooperativeMatrixKHR, 1464 SPIRV_C_BitInstructions, SPIRV_C_AtomicFloat32AddEXT, SPIRV_C_AtomicFloat64AddEXT, 1465 SPIRV_C_LongConstantCompositeINTEL, SPIRV_C_OptNoneINTEL, 1466 SPIRV_C_AtomicFloat16AddEXT, SPIRV_C_DebugInfoModuleINTEL, SPIRV_C_SplitBarrierINTEL, 1467 SPIRV_C_GroupUniformArithmeticKHR, SPIRV_C_Shader, SPIRV_C_Vector16, 1468 SPIRV_C_Float16Buffer, SPIRV_C_Int64Atomics, SPIRV_C_ImageBasic, SPIRV_C_Pipes, 1469 SPIRV_C_DeviceEnqueue, SPIRV_C_LiteralSampler, SPIRV_C_GenericPointer, SPIRV_C_Image1D, 1470 SPIRV_C_ImageBuffer, SPIRV_C_NamedBarrier, SPIRV_C_GroupNonUniformVote, 1471 SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformBallot, 1472 SPIRV_C_GroupNonUniformShuffle, SPIRV_C_GroupNonUniformShuffleRelative, 1473 SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformQuad, 1474 SPIRV_C_StorageUniform16, SPIRV_C_UniformAndStorageBuffer8BitAccess, 1475 SPIRV_C_UniformTexelBufferArrayDynamicIndexing, SPIRV_C_VectorComputeINTEL, 1476 SPIRV_C_FPFastMathModeINTEL, SPIRV_C_DotProductInput4x8Bit, 1477 SPIRV_C_GroupNonUniformRotateKHR, SPIRV_C_Geometry, SPIRV_C_Tessellation, 1478 SPIRV_C_ImageReadWrite, SPIRV_C_ImageMipmap, SPIRV_C_AtomicStorage, 1479 SPIRV_C_ImageGatherExtended, SPIRV_C_StorageImageMultisample, 1480 SPIRV_C_UniformBufferArrayDynamicIndexing, 1481 SPIRV_C_SampledImageArrayDynamicIndexing, 1482 SPIRV_C_StorageBufferArrayDynamicIndexing, 1483 SPIRV_C_StorageImageArrayDynamicIndexing, SPIRV_C_ClipDistance, SPIRV_C_CullDistance, 1484 SPIRV_C_SampleRateShading, SPIRV_C_SampledRect, SPIRV_C_InputAttachment, 1485 SPIRV_C_SparseResidency, SPIRV_C_MinLod, SPIRV_C_SampledCubeArray, 1486 SPIRV_C_ImageMSArray, SPIRV_C_StorageImageExtendedFormats, SPIRV_C_ImageQuery, 1487 SPIRV_C_DerivativeControl, SPIRV_C_InterpolationFunction, SPIRV_C_TransformFeedback, 1488 SPIRV_C_StorageImageReadWithoutFormat, SPIRV_C_StorageImageWriteWithoutFormat, 1489 SPIRV_C_SubgroupDispatch, SPIRV_C_PipeStorage, SPIRV_C_FragmentShadingRateKHR, 1490 SPIRV_C_DrawParameters, SPIRV_C_WorkgroupMemoryExplicitLayoutKHR, 1491 SPIRV_C_WorkgroupMemoryExplicitLayout16BitAccessKHR, SPIRV_C_MultiView, 1492 SPIRV_C_VariablePointersStorageBuffer, SPIRV_C_RayQueryProvisionalKHR, 1493 SPIRV_C_RayQueryKHR, SPIRV_C_RayTracingKHR, SPIRV_C_Float16ImageAMD, 1494 SPIRV_C_ImageGatherBiasLodAMD, SPIRV_C_FragmentMaskAMD, SPIRV_C_StencilExportEXT, 1495 SPIRV_C_ImageReadWriteLodAMD, SPIRV_C_Int64ImageEXT, SPIRV_C_ShaderClockKHR, 1496 SPIRV_C_FragmentFullyCoveredEXT, SPIRV_C_MeshShadingNV, SPIRV_C_FragmentDensityEXT, 1497 SPIRV_C_ShaderNonUniform, SPIRV_C_RuntimeDescriptorArray, 1498 SPIRV_C_StorageTexelBufferArrayDynamicIndexing, SPIRV_C_RayTracingNV, 1499 SPIRV_C_RayTracingMotionBlurNV, SPIRV_C_PhysicalStorageBufferAddresses, 1500 SPIRV_C_RayTracingProvisionalKHR, 1501 SPIRV_C_FragmentShaderSampleInterlockEXT, 1502 SPIRV_C_FragmentShaderShadingRateInterlockEXT, SPIRV_C_ShaderSMBuiltinsNV, 1503 SPIRV_C_FragmentShaderPixelInterlockEXT, SPIRV_C_DemoteToHelperInvocation, 1504 SPIRV_C_IntegerFunctions2INTEL, SPIRV_C_TessellationPointSize, 1505 SPIRV_C_GeometryPointSize, SPIRV_C_ImageCubeArray, SPIRV_C_ImageRect, 1506 SPIRV_C_GeometryStreams, SPIRV_C_MultiViewport, 1507 SPIRV_C_WorkgroupMemoryExplicitLayout8BitAccessKHR, SPIRV_C_VariablePointers, 1508 SPIRV_C_RayTraversalPrimitiveCullingKHR, SPIRV_C_SampleMaskOverrideCoverageNV, 1509 SPIRV_C_GeometryShaderPassthroughNV, SPIRV_C_PerViewAttributesNV, 1510 SPIRV_C_InputAttachmentArrayDynamicIndexing, 1511 SPIRV_C_UniformBufferArrayNonUniformIndexing, 1512 SPIRV_C_SampledImageArrayNonUniformIndexing, 1513 SPIRV_C_StorageBufferArrayNonUniformIndexing, 1514 SPIRV_C_StorageImageArrayNonUniformIndexing, 1515 SPIRV_C_InputAttachmentArrayNonUniformIndexing, 1516 SPIRV_C_UniformTexelBufferArrayNonUniformIndexing, 1517 SPIRV_C_StorageTexelBufferArrayNonUniformIndexing, 1518 SPIRV_C_ShaderViewportIndexLayerEXT, SPIRV_C_ShaderViewportMaskNV, 1519 SPIRV_C_ShaderStereoViewNV, SPIRV_C_Bfloat16ConversionINTEL, 1520 SPIRV_C_CacheControlsINTEL 1521 ]>; 1522 1523def SPIRV_AM_Logical : I32EnumAttrCase<"Logical", 0>; 1524def SPIRV_AM_Physical32 : I32EnumAttrCase<"Physical32", 1> { 1525 list<Availability> availability = [ 1526 Capability<[SPIRV_C_Addresses]> 1527 ]; 1528} 1529def SPIRV_AM_Physical64 : I32EnumAttrCase<"Physical64", 2> { 1530 list<Availability> availability = [ 1531 Capability<[SPIRV_C_Addresses]> 1532 ]; 1533} 1534def SPIRV_AM_PhysicalStorageBuffer64 : I32EnumAttrCase<"PhysicalStorageBuffer64", 5348> { 1535 list<Availability> availability = [ 1536 Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>, 1537 Capability<[SPIRV_C_PhysicalStorageBufferAddresses]> 1538 ]; 1539} 1540 1541def SPIRV_AddressingModelAttr : 1542 SPIRV_I32EnumAttr<"AddressingModel", "valid SPIR-V AddressingModel", "addressing_model", [ 1543 SPIRV_AM_Logical, SPIRV_AM_Physical32, SPIRV_AM_Physical64, 1544 SPIRV_AM_PhysicalStorageBuffer64 1545 ]>; 1546 1547def SPIRV_BI_Position : I32EnumAttrCase<"Position", 0> { 1548 list<Availability> availability = [ 1549 Capability<[SPIRV_C_Shader]> 1550 ]; 1551} 1552def SPIRV_BI_PointSize : I32EnumAttrCase<"PointSize", 1> { 1553 list<Availability> availability = [ 1554 Capability<[SPIRV_C_Shader]> 1555 ]; 1556} 1557def SPIRV_BI_ClipDistance : I32EnumAttrCase<"ClipDistance", 3> { 1558 list<Availability> availability = [ 1559 Capability<[SPIRV_C_ClipDistance]> 1560 ]; 1561} 1562def SPIRV_BI_CullDistance : I32EnumAttrCase<"CullDistance", 4> { 1563 list<Availability> availability = [ 1564 Capability<[SPIRV_C_CullDistance]> 1565 ]; 1566} 1567def SPIRV_BI_VertexId : I32EnumAttrCase<"VertexId", 5> { 1568 list<Availability> availability = [ 1569 Capability<[SPIRV_C_Shader]> 1570 ]; 1571} 1572def SPIRV_BI_InstanceId : I32EnumAttrCase<"InstanceId", 6> { 1573 list<Availability> availability = [ 1574 Capability<[SPIRV_C_Shader]> 1575 ]; 1576} 1577def SPIRV_BI_PrimitiveId : I32EnumAttrCase<"PrimitiveId", 7> { 1578 list<Availability> availability = [ 1579 Capability<[SPIRV_C_Geometry, SPIRV_C_MeshShadingNV, SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV, SPIRV_C_Tessellation]> 1580 ]; 1581} 1582def SPIRV_BI_InvocationId : I32EnumAttrCase<"InvocationId", 8> { 1583 list<Availability> availability = [ 1584 Capability<[SPIRV_C_Geometry, SPIRV_C_Tessellation]> 1585 ]; 1586} 1587def SPIRV_BI_Layer : I32EnumAttrCase<"Layer", 9> { 1588 list<Availability> availability = [ 1589 Capability<[SPIRV_C_Geometry, SPIRV_C_MeshShadingNV, SPIRV_C_ShaderLayer, SPIRV_C_ShaderViewportIndexLayerEXT]> 1590 ]; 1591} 1592def SPIRV_BI_ViewportIndex : I32EnumAttrCase<"ViewportIndex", 10> { 1593 list<Availability> availability = [ 1594 Capability<[SPIRV_C_MeshShadingNV, SPIRV_C_MultiViewport, SPIRV_C_ShaderViewportIndex, SPIRV_C_ShaderViewportIndexLayerEXT]> 1595 ]; 1596} 1597def SPIRV_BI_TessLevelOuter : I32EnumAttrCase<"TessLevelOuter", 11> { 1598 list<Availability> availability = [ 1599 Capability<[SPIRV_C_Tessellation]> 1600 ]; 1601} 1602def SPIRV_BI_TessLevelInner : I32EnumAttrCase<"TessLevelInner", 12> { 1603 list<Availability> availability = [ 1604 Capability<[SPIRV_C_Tessellation]> 1605 ]; 1606} 1607def SPIRV_BI_TessCoord : I32EnumAttrCase<"TessCoord", 13> { 1608 list<Availability> availability = [ 1609 Capability<[SPIRV_C_Tessellation]> 1610 ]; 1611} 1612def SPIRV_BI_PatchVertices : I32EnumAttrCase<"PatchVertices", 14> { 1613 list<Availability> availability = [ 1614 Capability<[SPIRV_C_Tessellation]> 1615 ]; 1616} 1617def SPIRV_BI_FragCoord : I32EnumAttrCase<"FragCoord", 15> { 1618 list<Availability> availability = [ 1619 Capability<[SPIRV_C_Shader]> 1620 ]; 1621} 1622def SPIRV_BI_PointCoord : I32EnumAttrCase<"PointCoord", 16> { 1623 list<Availability> availability = [ 1624 Capability<[SPIRV_C_Shader]> 1625 ]; 1626} 1627def SPIRV_BI_FrontFacing : I32EnumAttrCase<"FrontFacing", 17> { 1628 list<Availability> availability = [ 1629 Capability<[SPIRV_C_Shader]> 1630 ]; 1631} 1632def SPIRV_BI_SampleId : I32EnumAttrCase<"SampleId", 18> { 1633 list<Availability> availability = [ 1634 Capability<[SPIRV_C_SampleRateShading]> 1635 ]; 1636} 1637def SPIRV_BI_SamplePosition : I32EnumAttrCase<"SamplePosition", 19> { 1638 list<Availability> availability = [ 1639 Capability<[SPIRV_C_SampleRateShading]> 1640 ]; 1641} 1642def SPIRV_BI_SampleMask : I32EnumAttrCase<"SampleMask", 20> { 1643 list<Availability> availability = [ 1644 Capability<[SPIRV_C_Shader]> 1645 ]; 1646} 1647def SPIRV_BI_FragDepth : I32EnumAttrCase<"FragDepth", 22> { 1648 list<Availability> availability = [ 1649 Capability<[SPIRV_C_Shader]> 1650 ]; 1651} 1652def SPIRV_BI_HelperInvocation : I32EnumAttrCase<"HelperInvocation", 23> { 1653 list<Availability> availability = [ 1654 Capability<[SPIRV_C_Shader]> 1655 ]; 1656} 1657def SPIRV_BI_NumWorkgroups : I32EnumAttrCase<"NumWorkgroups", 24>; 1658def SPIRV_BI_WorkgroupSize : I32EnumAttrCase<"WorkgroupSize", 25>; 1659def SPIRV_BI_WorkgroupId : I32EnumAttrCase<"WorkgroupId", 26>; 1660def SPIRV_BI_LocalInvocationId : I32EnumAttrCase<"LocalInvocationId", 27>; 1661def SPIRV_BI_GlobalInvocationId : I32EnumAttrCase<"GlobalInvocationId", 28>; 1662def SPIRV_BI_LocalInvocationIndex : I32EnumAttrCase<"LocalInvocationIndex", 29>; 1663def SPIRV_BI_WorkDim : I32EnumAttrCase<"WorkDim", 30> { 1664 list<Availability> availability = [ 1665 Capability<[SPIRV_C_Kernel]> 1666 ]; 1667} 1668def SPIRV_BI_GlobalSize : I32EnumAttrCase<"GlobalSize", 31> { 1669 list<Availability> availability = [ 1670 Capability<[SPIRV_C_Kernel]> 1671 ]; 1672} 1673def SPIRV_BI_EnqueuedWorkgroupSize : I32EnumAttrCase<"EnqueuedWorkgroupSize", 32> { 1674 list<Availability> availability = [ 1675 Capability<[SPIRV_C_Kernel]> 1676 ]; 1677} 1678def SPIRV_BI_GlobalOffset : I32EnumAttrCase<"GlobalOffset", 33> { 1679 list<Availability> availability = [ 1680 Capability<[SPIRV_C_Kernel]> 1681 ]; 1682} 1683def SPIRV_BI_GlobalLinearId : I32EnumAttrCase<"GlobalLinearId", 34> { 1684 list<Availability> availability = [ 1685 Capability<[SPIRV_C_Kernel]> 1686 ]; 1687} 1688def SPIRV_BI_SubgroupSize : I32EnumAttrCase<"SubgroupSize", 36> { 1689 list<Availability> availability = [ 1690 Capability<[SPIRV_C_GroupNonUniform, SPIRV_C_Kernel, SPIRV_C_SubgroupBallotKHR]> 1691 ]; 1692} 1693def SPIRV_BI_SubgroupMaxSize : I32EnumAttrCase<"SubgroupMaxSize", 37> { 1694 list<Availability> availability = [ 1695 Capability<[SPIRV_C_Kernel]> 1696 ]; 1697} 1698def SPIRV_BI_NumSubgroups : I32EnumAttrCase<"NumSubgroups", 38> { 1699 list<Availability> availability = [ 1700 Capability<[SPIRV_C_GroupNonUniform, SPIRV_C_Kernel]> 1701 ]; 1702} 1703def SPIRV_BI_NumEnqueuedSubgroups : I32EnumAttrCase<"NumEnqueuedSubgroups", 39> { 1704 list<Availability> availability = [ 1705 Capability<[SPIRV_C_Kernel]> 1706 ]; 1707} 1708def SPIRV_BI_SubgroupId : I32EnumAttrCase<"SubgroupId", 40> { 1709 list<Availability> availability = [ 1710 Capability<[SPIRV_C_GroupNonUniform, SPIRV_C_Kernel]> 1711 ]; 1712} 1713def SPIRV_BI_SubgroupLocalInvocationId : I32EnumAttrCase<"SubgroupLocalInvocationId", 41> { 1714 list<Availability> availability = [ 1715 Capability<[SPIRV_C_GroupNonUniform, SPIRV_C_Kernel, SPIRV_C_SubgroupBallotKHR]> 1716 ]; 1717} 1718def SPIRV_BI_VertexIndex : I32EnumAttrCase<"VertexIndex", 42> { 1719 list<Availability> availability = [ 1720 Capability<[SPIRV_C_Shader]> 1721 ]; 1722} 1723def SPIRV_BI_InstanceIndex : I32EnumAttrCase<"InstanceIndex", 43> { 1724 list<Availability> availability = [ 1725 Capability<[SPIRV_C_Shader]> 1726 ]; 1727} 1728def SPIRV_BI_SubgroupEqMask : I32EnumAttrCase<"SubgroupEqMask", 4416> { 1729 list<Availability> availability = [ 1730 MinVersion<SPIRV_V_1_3>, 1731 Capability<[SPIRV_C_GroupNonUniformBallot, SPIRV_C_SubgroupBallotKHR]> 1732 ]; 1733} 1734def SPIRV_BI_SubgroupGeMask : I32EnumAttrCase<"SubgroupGeMask", 4417> { 1735 list<Availability> availability = [ 1736 MinVersion<SPIRV_V_1_3>, 1737 Capability<[SPIRV_C_GroupNonUniformBallot, SPIRV_C_SubgroupBallotKHR]> 1738 ]; 1739} 1740def SPIRV_BI_SubgroupGtMask : I32EnumAttrCase<"SubgroupGtMask", 4418> { 1741 list<Availability> availability = [ 1742 MinVersion<SPIRV_V_1_3>, 1743 Capability<[SPIRV_C_GroupNonUniformBallot, SPIRV_C_SubgroupBallotKHR]> 1744 ]; 1745} 1746def SPIRV_BI_SubgroupLeMask : I32EnumAttrCase<"SubgroupLeMask", 4419> { 1747 list<Availability> availability = [ 1748 MinVersion<SPIRV_V_1_3>, 1749 Capability<[SPIRV_C_GroupNonUniformBallot, SPIRV_C_SubgroupBallotKHR]> 1750 ]; 1751} 1752def SPIRV_BI_SubgroupLtMask : I32EnumAttrCase<"SubgroupLtMask", 4420> { 1753 list<Availability> availability = [ 1754 MinVersion<SPIRV_V_1_3>, 1755 Capability<[SPIRV_C_GroupNonUniformBallot, SPIRV_C_SubgroupBallotKHR]> 1756 ]; 1757} 1758def SPIRV_BI_BaseVertex : I32EnumAttrCase<"BaseVertex", 4424> { 1759 list<Availability> availability = [ 1760 Extension<[SPV_KHR_shader_draw_parameters]>, 1761 Capability<[SPIRV_C_DrawParameters]> 1762 ]; 1763} 1764def SPIRV_BI_BaseInstance : I32EnumAttrCase<"BaseInstance", 4425> { 1765 list<Availability> availability = [ 1766 Extension<[SPV_KHR_shader_draw_parameters]>, 1767 Capability<[SPIRV_C_DrawParameters]> 1768 ]; 1769} 1770def SPIRV_BI_DrawIndex : I32EnumAttrCase<"DrawIndex", 4426> { 1771 list<Availability> availability = [ 1772 Extension<[SPV_KHR_shader_draw_parameters, SPV_NV_mesh_shader]>, 1773 Capability<[SPIRV_C_DrawParameters, SPIRV_C_MeshShadingNV]> 1774 ]; 1775} 1776def SPIRV_BI_PrimitiveShadingRateKHR : I32EnumAttrCase<"PrimitiveShadingRateKHR", 4432> { 1777 list<Availability> availability = [ 1778 Extension<[SPV_KHR_fragment_shading_rate]>, 1779 Capability<[SPIRV_C_FragmentShadingRateKHR]> 1780 ]; 1781} 1782def SPIRV_BI_DeviceIndex : I32EnumAttrCase<"DeviceIndex", 4438> { 1783 list<Availability> availability = [ 1784 Extension<[SPV_KHR_device_group]>, 1785 Capability<[SPIRV_C_DeviceGroup]> 1786 ]; 1787} 1788def SPIRV_BI_ViewIndex : I32EnumAttrCase<"ViewIndex", 4440> { 1789 list<Availability> availability = [ 1790 Extension<[SPV_KHR_multiview]>, 1791 Capability<[SPIRV_C_MultiView]> 1792 ]; 1793} 1794def SPIRV_BI_ShadingRateKHR : I32EnumAttrCase<"ShadingRateKHR", 4444> { 1795 list<Availability> availability = [ 1796 Extension<[SPV_KHR_fragment_shading_rate]>, 1797 Capability<[SPIRV_C_FragmentShadingRateKHR]> 1798 ]; 1799} 1800def SPIRV_BI_BaryCoordNoPerspAMD : I32EnumAttrCase<"BaryCoordNoPerspAMD", 4992> { 1801 list<Availability> availability = [ 1802 Extension<[SPV_AMD_shader_explicit_vertex_parameter]> 1803 ]; 1804} 1805def SPIRV_BI_BaryCoordNoPerspCentroidAMD : I32EnumAttrCase<"BaryCoordNoPerspCentroidAMD", 4993> { 1806 list<Availability> availability = [ 1807 Extension<[SPV_AMD_shader_explicit_vertex_parameter]> 1808 ]; 1809} 1810def SPIRV_BI_BaryCoordNoPerspSampleAMD : I32EnumAttrCase<"BaryCoordNoPerspSampleAMD", 4994> { 1811 list<Availability> availability = [ 1812 Extension<[SPV_AMD_shader_explicit_vertex_parameter]> 1813 ]; 1814} 1815def SPIRV_BI_BaryCoordSmoothAMD : I32EnumAttrCase<"BaryCoordSmoothAMD", 4995> { 1816 list<Availability> availability = [ 1817 Extension<[SPV_AMD_shader_explicit_vertex_parameter]> 1818 ]; 1819} 1820def SPIRV_BI_BaryCoordSmoothCentroidAMD : I32EnumAttrCase<"BaryCoordSmoothCentroidAMD", 4996> { 1821 list<Availability> availability = [ 1822 Extension<[SPV_AMD_shader_explicit_vertex_parameter]> 1823 ]; 1824} 1825def SPIRV_BI_BaryCoordSmoothSampleAMD : I32EnumAttrCase<"BaryCoordSmoothSampleAMD", 4997> { 1826 list<Availability> availability = [ 1827 Extension<[SPV_AMD_shader_explicit_vertex_parameter]> 1828 ]; 1829} 1830def SPIRV_BI_BaryCoordPullModelAMD : I32EnumAttrCase<"BaryCoordPullModelAMD", 4998> { 1831 list<Availability> availability = [ 1832 Extension<[SPV_AMD_shader_explicit_vertex_parameter]> 1833 ]; 1834} 1835def SPIRV_BI_FragStencilRefEXT : I32EnumAttrCase<"FragStencilRefEXT", 5014> { 1836 list<Availability> availability = [ 1837 Extension<[SPV_EXT_shader_stencil_export]>, 1838 Capability<[SPIRV_C_StencilExportEXT]> 1839 ]; 1840} 1841def SPIRV_BI_ViewportMaskNV : I32EnumAttrCase<"ViewportMaskNV", 5253> { 1842 list<Availability> availability = [ 1843 Extension<[SPV_NV_mesh_shader, SPV_NV_viewport_array2]>, 1844 Capability<[SPIRV_C_MeshShadingNV, SPIRV_C_ShaderViewportMaskNV]> 1845 ]; 1846} 1847def SPIRV_BI_SecondaryPositionNV : I32EnumAttrCase<"SecondaryPositionNV", 5257> { 1848 list<Availability> availability = [ 1849 Extension<[SPV_NV_stereo_view_rendering]>, 1850 Capability<[SPIRV_C_ShaderStereoViewNV]> 1851 ]; 1852} 1853def SPIRV_BI_SecondaryViewportMaskNV : I32EnumAttrCase<"SecondaryViewportMaskNV", 5258> { 1854 list<Availability> availability = [ 1855 Extension<[SPV_NV_stereo_view_rendering]>, 1856 Capability<[SPIRV_C_ShaderStereoViewNV]> 1857 ]; 1858} 1859def SPIRV_BI_PositionPerViewNV : I32EnumAttrCase<"PositionPerViewNV", 5261> { 1860 list<Availability> availability = [ 1861 Extension<[SPV_NVX_multiview_per_view_attributes, SPV_NV_mesh_shader]>, 1862 Capability<[SPIRV_C_MeshShadingNV, SPIRV_C_PerViewAttributesNV]> 1863 ]; 1864} 1865def SPIRV_BI_ViewportMaskPerViewNV : I32EnumAttrCase<"ViewportMaskPerViewNV", 5262> { 1866 list<Availability> availability = [ 1867 Extension<[SPV_NVX_multiview_per_view_attributes, SPV_NV_mesh_shader]>, 1868 Capability<[SPIRV_C_MeshShadingNV, SPIRV_C_PerViewAttributesNV]> 1869 ]; 1870} 1871def SPIRV_BI_FullyCoveredEXT : I32EnumAttrCase<"FullyCoveredEXT", 5264> { 1872 list<Availability> availability = [ 1873 Extension<[SPV_EXT_fragment_fully_covered]>, 1874 Capability<[SPIRV_C_FragmentFullyCoveredEXT]> 1875 ]; 1876} 1877def SPIRV_BI_TaskCountNV : I32EnumAttrCase<"TaskCountNV", 5274> { 1878 list<Availability> availability = [ 1879 Extension<[SPV_NV_mesh_shader]>, 1880 Capability<[SPIRV_C_MeshShadingNV]> 1881 ]; 1882} 1883def SPIRV_BI_PrimitiveCountNV : I32EnumAttrCase<"PrimitiveCountNV", 5275> { 1884 list<Availability> availability = [ 1885 Extension<[SPV_NV_mesh_shader]>, 1886 Capability<[SPIRV_C_MeshShadingNV]> 1887 ]; 1888} 1889def SPIRV_BI_PrimitiveIndicesNV : I32EnumAttrCase<"PrimitiveIndicesNV", 5276> { 1890 list<Availability> availability = [ 1891 Extension<[SPV_NV_mesh_shader]>, 1892 Capability<[SPIRV_C_MeshShadingNV]> 1893 ]; 1894} 1895def SPIRV_BI_ClipDistancePerViewNV : I32EnumAttrCase<"ClipDistancePerViewNV", 5277> { 1896 list<Availability> availability = [ 1897 Extension<[SPV_NV_mesh_shader]>, 1898 Capability<[SPIRV_C_MeshShadingNV]> 1899 ]; 1900} 1901def SPIRV_BI_CullDistancePerViewNV : I32EnumAttrCase<"CullDistancePerViewNV", 5278> { 1902 list<Availability> availability = [ 1903 Extension<[SPV_NV_mesh_shader]>, 1904 Capability<[SPIRV_C_MeshShadingNV]> 1905 ]; 1906} 1907def SPIRV_BI_LayerPerViewNV : I32EnumAttrCase<"LayerPerViewNV", 5279> { 1908 list<Availability> availability = [ 1909 Extension<[SPV_NV_mesh_shader]>, 1910 Capability<[SPIRV_C_MeshShadingNV]> 1911 ]; 1912} 1913def SPIRV_BI_MeshViewCountNV : I32EnumAttrCase<"MeshViewCountNV", 5280> { 1914 list<Availability> availability = [ 1915 Extension<[SPV_NV_mesh_shader]>, 1916 Capability<[SPIRV_C_MeshShadingNV]> 1917 ]; 1918} 1919def SPIRV_BI_MeshViewIndicesNV : I32EnumAttrCase<"MeshViewIndicesNV", 5281> { 1920 list<Availability> availability = [ 1921 Extension<[SPV_NV_mesh_shader]>, 1922 Capability<[SPIRV_C_MeshShadingNV]> 1923 ]; 1924} 1925def SPIRV_BI_BaryCoordKHR : I32EnumAttrCase<"BaryCoordKHR", 5286> { 1926 list<Availability> availability = [ 1927 Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>, 1928 Capability<[SPIRV_C_FragmentBarycentricKHR]> 1929 ]; 1930} 1931def SPIRV_BI_BaryCoordNoPerspKHR : I32EnumAttrCase<"BaryCoordNoPerspKHR", 5287> { 1932 list<Availability> availability = [ 1933 Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>, 1934 Capability<[SPIRV_C_FragmentBarycentricKHR]> 1935 ]; 1936} 1937def SPIRV_BI_FragSizeEXT : I32EnumAttrCase<"FragSizeEXT", 5292> { 1938 list<Availability> availability = [ 1939 Extension<[SPV_EXT_fragment_invocation_density, SPV_NV_shading_rate]>, 1940 Capability<[SPIRV_C_FragmentDensityEXT]> 1941 ]; 1942} 1943def SPIRV_BI_FragInvocationCountEXT : I32EnumAttrCase<"FragInvocationCountEXT", 5293> { 1944 list<Availability> availability = [ 1945 Extension<[SPV_EXT_fragment_invocation_density, SPV_NV_shading_rate]>, 1946 Capability<[SPIRV_C_FragmentDensityEXT]> 1947 ]; 1948} 1949def SPIRV_BI_LaunchIdKHR : I32EnumAttrCase<"LaunchIdKHR", 5319> { 1950 list<Availability> availability = [ 1951 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 1952 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 1953 ]; 1954} 1955def SPIRV_BI_LaunchSizeKHR : I32EnumAttrCase<"LaunchSizeKHR", 5320> { 1956 list<Availability> availability = [ 1957 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 1958 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 1959 ]; 1960} 1961def SPIRV_BI_WorldRayOriginKHR : I32EnumAttrCase<"WorldRayOriginKHR", 5321> { 1962 list<Availability> availability = [ 1963 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 1964 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 1965 ]; 1966} 1967def SPIRV_BI_WorldRayDirectionKHR : I32EnumAttrCase<"WorldRayDirectionKHR", 5322> { 1968 list<Availability> availability = [ 1969 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 1970 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 1971 ]; 1972} 1973def SPIRV_BI_ObjectRayOriginKHR : I32EnumAttrCase<"ObjectRayOriginKHR", 5323> { 1974 list<Availability> availability = [ 1975 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 1976 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 1977 ]; 1978} 1979def SPIRV_BI_ObjectRayDirectionKHR : I32EnumAttrCase<"ObjectRayDirectionKHR", 5324> { 1980 list<Availability> availability = [ 1981 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 1982 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 1983 ]; 1984} 1985def SPIRV_BI_RayTminKHR : I32EnumAttrCase<"RayTminKHR", 5325> { 1986 list<Availability> availability = [ 1987 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 1988 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 1989 ]; 1990} 1991def SPIRV_BI_RayTmaxKHR : I32EnumAttrCase<"RayTmaxKHR", 5326> { 1992 list<Availability> availability = [ 1993 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 1994 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 1995 ]; 1996} 1997def SPIRV_BI_InstanceCustomIndexKHR : I32EnumAttrCase<"InstanceCustomIndexKHR", 5327> { 1998 list<Availability> availability = [ 1999 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 2000 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 2001 ]; 2002} 2003def SPIRV_BI_ObjectToWorldKHR : I32EnumAttrCase<"ObjectToWorldKHR", 5330> { 2004 list<Availability> availability = [ 2005 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 2006 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 2007 ]; 2008} 2009def SPIRV_BI_WorldToObjectKHR : I32EnumAttrCase<"WorldToObjectKHR", 5331> { 2010 list<Availability> availability = [ 2011 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 2012 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 2013 ]; 2014} 2015def SPIRV_BI_HitTNV : I32EnumAttrCase<"HitTNV", 5332> { 2016 list<Availability> availability = [ 2017 Extension<[SPV_NV_ray_tracing]>, 2018 Capability<[SPIRV_C_RayTracingNV]> 2019 ]; 2020} 2021def SPIRV_BI_HitKindKHR : I32EnumAttrCase<"HitKindKHR", 5333> { 2022 list<Availability> availability = [ 2023 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 2024 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 2025 ]; 2026} 2027def SPIRV_BI_CurrentRayTimeNV : I32EnumAttrCase<"CurrentRayTimeNV", 5334> { 2028 list<Availability> availability = [ 2029 Extension<[SPV_NV_ray_tracing_motion_blur]>, 2030 Capability<[SPIRV_C_RayTracingMotionBlurNV]> 2031 ]; 2032} 2033def SPIRV_BI_IncomingRayFlagsKHR : I32EnumAttrCase<"IncomingRayFlagsKHR", 5351> { 2034 list<Availability> availability = [ 2035 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 2036 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 2037 ]; 2038} 2039def SPIRV_BI_RayGeometryIndexKHR : I32EnumAttrCase<"RayGeometryIndexKHR", 5352> { 2040 list<Availability> availability = [ 2041 Extension<[SPV_KHR_ray_tracing]>, 2042 Capability<[SPIRV_C_RayTracingKHR]> 2043 ]; 2044} 2045def SPIRV_BI_WarpsPerSMNV : I32EnumAttrCase<"WarpsPerSMNV", 5374> { 2046 list<Availability> availability = [ 2047 Extension<[SPV_NV_shader_sm_builtins]>, 2048 Capability<[SPIRV_C_ShaderSMBuiltinsNV]> 2049 ]; 2050} 2051def SPIRV_BI_SMCountNV : I32EnumAttrCase<"SMCountNV", 5375> { 2052 list<Availability> availability = [ 2053 Extension<[SPV_NV_shader_sm_builtins]>, 2054 Capability<[SPIRV_C_ShaderSMBuiltinsNV]> 2055 ]; 2056} 2057def SPIRV_BI_WarpIDNV : I32EnumAttrCase<"WarpIDNV", 5376> { 2058 list<Availability> availability = [ 2059 Extension<[SPV_NV_shader_sm_builtins]>, 2060 Capability<[SPIRV_C_ShaderSMBuiltinsNV]> 2061 ]; 2062} 2063def SPIRV_BI_SMIDNV : I32EnumAttrCase<"SMIDNV", 5377> { 2064 list<Availability> availability = [ 2065 Extension<[SPV_NV_shader_sm_builtins]>, 2066 Capability<[SPIRV_C_ShaderSMBuiltinsNV]> 2067 ]; 2068} 2069def SPIRV_BI_CullMaskKHR : I32EnumAttrCase<"CullMaskKHR", 6021> { 2070 list<Availability> availability = [ 2071 Extension<[SPV_KHR_ray_cull_mask]>, 2072 Capability<[SPIRV_C_RayCullMaskKHR]> 2073 ]; 2074} 2075 2076def SPIRV_BuiltInAttr : 2077 SPIRV_I32EnumAttr<"BuiltIn", "valid SPIR-V BuiltIn", "built_in", [ 2078 SPIRV_BI_Position, SPIRV_BI_PointSize, SPIRV_BI_ClipDistance, SPIRV_BI_CullDistance, 2079 SPIRV_BI_VertexId, SPIRV_BI_InstanceId, SPIRV_BI_PrimitiveId, SPIRV_BI_InvocationId, 2080 SPIRV_BI_Layer, SPIRV_BI_ViewportIndex, SPIRV_BI_TessLevelOuter, 2081 SPIRV_BI_TessLevelInner, SPIRV_BI_TessCoord, SPIRV_BI_PatchVertices, 2082 SPIRV_BI_FragCoord, SPIRV_BI_PointCoord, SPIRV_BI_FrontFacing, SPIRV_BI_SampleId, 2083 SPIRV_BI_SamplePosition, SPIRV_BI_SampleMask, SPIRV_BI_FragDepth, 2084 SPIRV_BI_HelperInvocation, SPIRV_BI_NumWorkgroups, SPIRV_BI_WorkgroupSize, 2085 SPIRV_BI_WorkgroupId, SPIRV_BI_LocalInvocationId, SPIRV_BI_GlobalInvocationId, 2086 SPIRV_BI_LocalInvocationIndex, SPIRV_BI_WorkDim, SPIRV_BI_GlobalSize, 2087 SPIRV_BI_EnqueuedWorkgroupSize, SPIRV_BI_GlobalOffset, SPIRV_BI_GlobalLinearId, 2088 SPIRV_BI_SubgroupSize, SPIRV_BI_SubgroupMaxSize, SPIRV_BI_NumSubgroups, 2089 SPIRV_BI_NumEnqueuedSubgroups, SPIRV_BI_SubgroupId, 2090 SPIRV_BI_SubgroupLocalInvocationId, SPIRV_BI_VertexIndex, SPIRV_BI_InstanceIndex, 2091 SPIRV_BI_SubgroupEqMask, SPIRV_BI_SubgroupGeMask, SPIRV_BI_SubgroupGtMask, 2092 SPIRV_BI_SubgroupLeMask, SPIRV_BI_SubgroupLtMask, SPIRV_BI_BaseVertex, 2093 SPIRV_BI_BaseInstance, SPIRV_BI_DrawIndex, SPIRV_BI_PrimitiveShadingRateKHR, 2094 SPIRV_BI_DeviceIndex, SPIRV_BI_ViewIndex, SPIRV_BI_ShadingRateKHR, 2095 SPIRV_BI_BaryCoordNoPerspAMD, SPIRV_BI_BaryCoordNoPerspCentroidAMD, 2096 SPIRV_BI_BaryCoordNoPerspSampleAMD, SPIRV_BI_BaryCoordSmoothAMD, 2097 SPIRV_BI_BaryCoordSmoothCentroidAMD, SPIRV_BI_BaryCoordSmoothSampleAMD, 2098 SPIRV_BI_BaryCoordPullModelAMD, SPIRV_BI_FragStencilRefEXT, SPIRV_BI_ViewportMaskNV, 2099 SPIRV_BI_SecondaryPositionNV, SPIRV_BI_SecondaryViewportMaskNV, 2100 SPIRV_BI_PositionPerViewNV, SPIRV_BI_ViewportMaskPerViewNV, SPIRV_BI_FullyCoveredEXT, 2101 SPIRV_BI_TaskCountNV, SPIRV_BI_PrimitiveCountNV, SPIRV_BI_PrimitiveIndicesNV, 2102 SPIRV_BI_ClipDistancePerViewNV, SPIRV_BI_CullDistancePerViewNV, 2103 SPIRV_BI_LayerPerViewNV, SPIRV_BI_MeshViewCountNV, SPIRV_BI_MeshViewIndicesNV, 2104 SPIRV_BI_BaryCoordKHR, SPIRV_BI_BaryCoordNoPerspKHR, SPIRV_BI_FragSizeEXT, 2105 SPIRV_BI_FragInvocationCountEXT, SPIRV_BI_LaunchIdKHR, SPIRV_BI_LaunchSizeKHR, 2106 SPIRV_BI_WorldRayOriginKHR, SPIRV_BI_WorldRayDirectionKHR, 2107 SPIRV_BI_ObjectRayOriginKHR, SPIRV_BI_ObjectRayDirectionKHR, SPIRV_BI_RayTminKHR, 2108 SPIRV_BI_RayTmaxKHR, SPIRV_BI_InstanceCustomIndexKHR, SPIRV_BI_ObjectToWorldKHR, 2109 SPIRV_BI_WorldToObjectKHR, SPIRV_BI_HitTNV, SPIRV_BI_HitKindKHR, 2110 SPIRV_BI_CurrentRayTimeNV, SPIRV_BI_IncomingRayFlagsKHR, 2111 SPIRV_BI_RayGeometryIndexKHR, SPIRV_BI_WarpsPerSMNV, SPIRV_BI_SMCountNV, 2112 SPIRV_BI_WarpIDNV, SPIRV_BI_SMIDNV, SPIRV_BI_CullMaskKHR 2113 ]>; 2114 2115def SPIRV_D_RelaxedPrecision : I32EnumAttrCase<"RelaxedPrecision", 0> { 2116 list<Availability> availability = [ 2117 Capability<[SPIRV_C_Shader]> 2118 ]; 2119} 2120def SPIRV_D_SpecId : I32EnumAttrCase<"SpecId", 1> { 2121 list<Availability> availability = [ 2122 Capability<[SPIRV_C_Kernel, SPIRV_C_Shader]> 2123 ]; 2124} 2125def SPIRV_D_Block : I32EnumAttrCase<"Block", 2> { 2126 list<Availability> availability = [ 2127 Capability<[SPIRV_C_Shader]> 2128 ]; 2129} 2130def SPIRV_D_BufferBlock : I32EnumAttrCase<"BufferBlock", 3> { 2131 list<Availability> availability = [ 2132 MaxVersion<SPIRV_V_1_3>, 2133 Capability<[SPIRV_C_Shader]> 2134 ]; 2135} 2136def SPIRV_D_RowMajor : I32EnumAttrCase<"RowMajor", 4> { 2137 list<Availability> availability = [ 2138 Capability<[SPIRV_C_Matrix]> 2139 ]; 2140} 2141def SPIRV_D_ColMajor : I32EnumAttrCase<"ColMajor", 5> { 2142 list<Availability> availability = [ 2143 Capability<[SPIRV_C_Matrix]> 2144 ]; 2145} 2146def SPIRV_D_ArrayStride : I32EnumAttrCase<"ArrayStride", 6> { 2147 list<Availability> availability = [ 2148 Capability<[SPIRV_C_Shader]> 2149 ]; 2150} 2151def SPIRV_D_MatrixStride : I32EnumAttrCase<"MatrixStride", 7> { 2152 list<Availability> availability = [ 2153 Capability<[SPIRV_C_Matrix]> 2154 ]; 2155} 2156def SPIRV_D_GLSLShared : I32EnumAttrCase<"GLSLShared", 8> { 2157 list<Availability> availability = [ 2158 Capability<[SPIRV_C_Shader]> 2159 ]; 2160} 2161def SPIRV_D_GLSLPacked : I32EnumAttrCase<"GLSLPacked", 9> { 2162 list<Availability> availability = [ 2163 Capability<[SPIRV_C_Shader]> 2164 ]; 2165} 2166def SPIRV_D_CPacked : I32EnumAttrCase<"CPacked", 10> { 2167 list<Availability> availability = [ 2168 Capability<[SPIRV_C_Kernel]> 2169 ]; 2170} 2171def SPIRV_D_BuiltIn : I32EnumAttrCase<"BuiltIn", 11>; 2172def SPIRV_D_NoPerspective : I32EnumAttrCase<"NoPerspective", 13> { 2173 list<Availability> availability = [ 2174 Capability<[SPIRV_C_Shader]> 2175 ]; 2176} 2177def SPIRV_D_Flat : I32EnumAttrCase<"Flat", 14> { 2178 list<Availability> availability = [ 2179 Capability<[SPIRV_C_Shader]> 2180 ]; 2181} 2182def SPIRV_D_Patch : I32EnumAttrCase<"Patch", 15> { 2183 list<Availability> availability = [ 2184 Capability<[SPIRV_C_Tessellation]> 2185 ]; 2186} 2187def SPIRV_D_Centroid : I32EnumAttrCase<"Centroid", 16> { 2188 list<Availability> availability = [ 2189 Capability<[SPIRV_C_Shader]> 2190 ]; 2191} 2192def SPIRV_D_Sample : I32EnumAttrCase<"Sample", 17> { 2193 list<Availability> availability = [ 2194 Capability<[SPIRV_C_SampleRateShading]> 2195 ]; 2196} 2197def SPIRV_D_Invariant : I32EnumAttrCase<"Invariant", 18> { 2198 list<Availability> availability = [ 2199 Capability<[SPIRV_C_Shader]> 2200 ]; 2201} 2202def SPIRV_D_Restrict : I32EnumAttrCase<"Restrict", 19>; 2203def SPIRV_D_Aliased : I32EnumAttrCase<"Aliased", 20>; 2204def SPIRV_D_Volatile : I32EnumAttrCase<"Volatile", 21>; 2205def SPIRV_D_Constant : I32EnumAttrCase<"Constant", 22> { 2206 list<Availability> availability = [ 2207 Capability<[SPIRV_C_Kernel]> 2208 ]; 2209} 2210def SPIRV_D_Coherent : I32EnumAttrCase<"Coherent", 23>; 2211def SPIRV_D_NonWritable : I32EnumAttrCase<"NonWritable", 24>; 2212def SPIRV_D_NonReadable : I32EnumAttrCase<"NonReadable", 25>; 2213def SPIRV_D_Uniform : I32EnumAttrCase<"Uniform", 26> { 2214 list<Availability> availability = [ 2215 Capability<[SPIRV_C_Shader, SPIRV_C_UniformDecoration]> 2216 ]; 2217} 2218def SPIRV_D_UniformId : I32EnumAttrCase<"UniformId", 27> { 2219 list<Availability> availability = [ 2220 MinVersion<SPIRV_V_1_4>, 2221 Capability<[SPIRV_C_Shader, SPIRV_C_UniformDecoration]> 2222 ]; 2223} 2224def SPIRV_D_SaturatedConversion : I32EnumAttrCase<"SaturatedConversion", 28> { 2225 list<Availability> availability = [ 2226 Capability<[SPIRV_C_Kernel]> 2227 ]; 2228} 2229def SPIRV_D_Stream : I32EnumAttrCase<"Stream", 29> { 2230 list<Availability> availability = [ 2231 Capability<[SPIRV_C_GeometryStreams]> 2232 ]; 2233} 2234def SPIRV_D_Location : I32EnumAttrCase<"Location", 30> { 2235 list<Availability> availability = [ 2236 Capability<[SPIRV_C_Shader]> 2237 ]; 2238} 2239def SPIRV_D_Component : I32EnumAttrCase<"Component", 31> { 2240 list<Availability> availability = [ 2241 Capability<[SPIRV_C_Shader]> 2242 ]; 2243} 2244def SPIRV_D_Index : I32EnumAttrCase<"Index", 32> { 2245 list<Availability> availability = [ 2246 Capability<[SPIRV_C_Shader]> 2247 ]; 2248} 2249def SPIRV_D_Binding : I32EnumAttrCase<"Binding", 33> { 2250 list<Availability> availability = [ 2251 Capability<[SPIRV_C_Shader]> 2252 ]; 2253} 2254def SPIRV_D_DescriptorSet : I32EnumAttrCase<"DescriptorSet", 34> { 2255 list<Availability> availability = [ 2256 Capability<[SPIRV_C_Shader]> 2257 ]; 2258} 2259def SPIRV_D_Offset : I32EnumAttrCase<"Offset", 35> { 2260 list<Availability> availability = [ 2261 Capability<[SPIRV_C_Shader]> 2262 ]; 2263} 2264def SPIRV_D_XfbBuffer : I32EnumAttrCase<"XfbBuffer", 36> { 2265 list<Availability> availability = [ 2266 Capability<[SPIRV_C_TransformFeedback]> 2267 ]; 2268} 2269def SPIRV_D_XfbStride : I32EnumAttrCase<"XfbStride", 37> { 2270 list<Availability> availability = [ 2271 Capability<[SPIRV_C_TransformFeedback]> 2272 ]; 2273} 2274def SPIRV_D_FuncParamAttr : I32EnumAttrCase<"FuncParamAttr", 38> { 2275 list<Availability> availability = [ 2276 Capability<[SPIRV_C_Kernel]> 2277 ]; 2278} 2279def SPIRV_D_FPRoundingMode : I32EnumAttrCase<"FPRoundingMode", 39>; 2280def SPIRV_D_FPFastMathMode : I32EnumAttrCase<"FPFastMathMode", 40> { 2281 list<Availability> availability = [ 2282 Capability<[SPIRV_C_Kernel]> 2283 ]; 2284} 2285def SPIRV_D_LinkageAttributes : I32EnumAttrCase<"LinkageAttributes", 41> { 2286 list<Availability> availability = [ 2287 Capability<[SPIRV_C_Linkage]> 2288 ]; 2289} 2290def SPIRV_D_NoContraction : I32EnumAttrCase<"NoContraction", 42> { 2291 list<Availability> availability = [ 2292 Capability<[SPIRV_C_Shader]> 2293 ]; 2294} 2295def SPIRV_D_InputAttachmentIndex : I32EnumAttrCase<"InputAttachmentIndex", 43> { 2296 list<Availability> availability = [ 2297 Capability<[SPIRV_C_InputAttachment]> 2298 ]; 2299} 2300def SPIRV_D_Alignment : I32EnumAttrCase<"Alignment", 44> { 2301 list<Availability> availability = [ 2302 Capability<[SPIRV_C_Kernel]> 2303 ]; 2304} 2305def SPIRV_D_MaxByteOffset : I32EnumAttrCase<"MaxByteOffset", 45> { 2306 list<Availability> availability = [ 2307 MinVersion<SPIRV_V_1_1>, 2308 Capability<[SPIRV_C_Addresses]> 2309 ]; 2310} 2311def SPIRV_D_AlignmentId : I32EnumAttrCase<"AlignmentId", 46> { 2312 list<Availability> availability = [ 2313 MinVersion<SPIRV_V_1_2>, 2314 Capability<[SPIRV_C_Kernel]> 2315 ]; 2316} 2317def SPIRV_D_MaxByteOffsetId : I32EnumAttrCase<"MaxByteOffsetId", 47> { 2318 list<Availability> availability = [ 2319 MinVersion<SPIRV_V_1_2>, 2320 Capability<[SPIRV_C_Addresses]> 2321 ]; 2322} 2323def SPIRV_D_NoSignedWrap : I32EnumAttrCase<"NoSignedWrap", 4469> { 2324 list<Availability> availability = [ 2325 Extension<[SPV_KHR_no_integer_wrap_decoration]> 2326 ]; 2327} 2328def SPIRV_D_NoUnsignedWrap : I32EnumAttrCase<"NoUnsignedWrap", 4470> { 2329 list<Availability> availability = [ 2330 Extension<[SPV_KHR_no_integer_wrap_decoration]> 2331 ]; 2332} 2333def SPIRV_D_ExplicitInterpAMD : I32EnumAttrCase<"ExplicitInterpAMD", 4999> { 2334 list<Availability> availability = [ 2335 Extension<[SPV_AMD_shader_explicit_vertex_parameter]> 2336 ]; 2337} 2338def SPIRV_D_OverrideCoverageNV : I32EnumAttrCase<"OverrideCoverageNV", 5248> { 2339 list<Availability> availability = [ 2340 Extension<[SPV_NV_sample_mask_override_coverage]>, 2341 Capability<[SPIRV_C_SampleMaskOverrideCoverageNV]> 2342 ]; 2343} 2344def SPIRV_D_PassthroughNV : I32EnumAttrCase<"PassthroughNV", 5250> { 2345 list<Availability> availability = [ 2346 Extension<[SPV_NV_geometry_shader_passthrough]>, 2347 Capability<[SPIRV_C_GeometryShaderPassthroughNV]> 2348 ]; 2349} 2350def SPIRV_D_ViewportRelativeNV : I32EnumAttrCase<"ViewportRelativeNV", 5252> { 2351 list<Availability> availability = [ 2352 Capability<[SPIRV_C_ShaderViewportMaskNV]> 2353 ]; 2354} 2355def SPIRV_D_SecondaryViewportRelativeNV : I32EnumAttrCase<"SecondaryViewportRelativeNV", 5256> { 2356 list<Availability> availability = [ 2357 Extension<[SPV_NV_stereo_view_rendering]>, 2358 Capability<[SPIRV_C_ShaderStereoViewNV]> 2359 ]; 2360} 2361def SPIRV_D_PerPrimitiveNV : I32EnumAttrCase<"PerPrimitiveNV", 5271> { 2362 list<Availability> availability = [ 2363 Extension<[SPV_NV_mesh_shader]>, 2364 Capability<[SPIRV_C_MeshShadingNV]> 2365 ]; 2366} 2367def SPIRV_D_PerViewNV : I32EnumAttrCase<"PerViewNV", 5272> { 2368 list<Availability> availability = [ 2369 Extension<[SPV_NV_mesh_shader]>, 2370 Capability<[SPIRV_C_MeshShadingNV]> 2371 ]; 2372} 2373def SPIRV_D_PerTaskNV : I32EnumAttrCase<"PerTaskNV", 5273> { 2374 list<Availability> availability = [ 2375 Extension<[SPV_NV_mesh_shader]>, 2376 Capability<[SPIRV_C_MeshShadingNV]> 2377 ]; 2378} 2379def SPIRV_D_PerVertexKHR : I32EnumAttrCase<"PerVertexKHR", 5285> { 2380 list<Availability> availability = [ 2381 Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>, 2382 Capability<[SPIRV_C_FragmentBarycentricKHR]> 2383 ]; 2384} 2385def SPIRV_D_NonUniform : I32EnumAttrCase<"NonUniform", 5300> { 2386 list<Availability> availability = [ 2387 MinVersion<SPIRV_V_1_5>, 2388 Capability<[SPIRV_C_ShaderNonUniform]> 2389 ]; 2390} 2391def SPIRV_D_RestrictPointer : I32EnumAttrCase<"RestrictPointer", 5355> { 2392 list<Availability> availability = [ 2393 Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>, 2394 Capability<[SPIRV_C_PhysicalStorageBufferAddresses]> 2395 ]; 2396} 2397def SPIRV_D_AliasedPointer : I32EnumAttrCase<"AliasedPointer", 5356> { 2398 list<Availability> availability = [ 2399 Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>, 2400 Capability<[SPIRV_C_PhysicalStorageBufferAddresses]> 2401 ]; 2402} 2403def SPIRV_D_BindlessSamplerNV : I32EnumAttrCase<"BindlessSamplerNV", 5398> { 2404 list<Availability> availability = [ 2405 Capability<[SPIRV_C_BindlessTextureNV]> 2406 ]; 2407} 2408def SPIRV_D_BindlessImageNV : I32EnumAttrCase<"BindlessImageNV", 5399> { 2409 list<Availability> availability = [ 2410 Capability<[SPIRV_C_BindlessTextureNV]> 2411 ]; 2412} 2413def SPIRV_D_BoundSamplerNV : I32EnumAttrCase<"BoundSamplerNV", 5400> { 2414 list<Availability> availability = [ 2415 Capability<[SPIRV_C_BindlessTextureNV]> 2416 ]; 2417} 2418def SPIRV_D_BoundImageNV : I32EnumAttrCase<"BoundImageNV", 5401> { 2419 list<Availability> availability = [ 2420 Capability<[SPIRV_C_BindlessTextureNV]> 2421 ]; 2422} 2423def SPIRV_D_SIMTCallINTEL : I32EnumAttrCase<"SIMTCallINTEL", 5599> { 2424 list<Availability> availability = [ 2425 Capability<[SPIRV_C_VectorComputeINTEL]> 2426 ]; 2427} 2428def SPIRV_D_ReferencedIndirectlyINTEL : I32EnumAttrCase<"ReferencedIndirectlyINTEL", 5602> { 2429 list<Availability> availability = [ 2430 Extension<[SPV_INTEL_function_pointers]>, 2431 Capability<[SPIRV_C_IndirectReferencesINTEL]> 2432 ]; 2433} 2434def SPIRV_D_ClobberINTEL : I32EnumAttrCase<"ClobberINTEL", 5607> { 2435 list<Availability> availability = [ 2436 Capability<[SPIRV_C_AsmINTEL]> 2437 ]; 2438} 2439def SPIRV_D_SideEffectsINTEL : I32EnumAttrCase<"SideEffectsINTEL", 5608> { 2440 list<Availability> availability = [ 2441 Capability<[SPIRV_C_AsmINTEL]> 2442 ]; 2443} 2444def SPIRV_D_VectorComputeVariableINTEL : I32EnumAttrCase<"VectorComputeVariableINTEL", 5624> { 2445 list<Availability> availability = [ 2446 Capability<[SPIRV_C_VectorComputeINTEL]> 2447 ]; 2448} 2449def SPIRV_D_FuncParamIOKindINTEL : I32EnumAttrCase<"FuncParamIOKindINTEL", 5625> { 2450 list<Availability> availability = [ 2451 Capability<[SPIRV_C_VectorComputeINTEL]> 2452 ]; 2453} 2454def SPIRV_D_VectorComputeFunctionINTEL : I32EnumAttrCase<"VectorComputeFunctionINTEL", 5626> { 2455 list<Availability> availability = [ 2456 Capability<[SPIRV_C_VectorComputeINTEL]> 2457 ]; 2458} 2459def SPIRV_D_StackCallINTEL : I32EnumAttrCase<"StackCallINTEL", 5627> { 2460 list<Availability> availability = [ 2461 Capability<[SPIRV_C_VectorComputeINTEL]> 2462 ]; 2463} 2464def SPIRV_D_GlobalVariableOffsetINTEL : I32EnumAttrCase<"GlobalVariableOffsetINTEL", 5628> { 2465 list<Availability> availability = [ 2466 Capability<[SPIRV_C_VectorComputeINTEL]> 2467 ]; 2468} 2469def SPIRV_D_CounterBuffer : I32EnumAttrCase<"CounterBuffer", 5634> { 2470 list<Availability> availability = [ 2471 MinVersion<SPIRV_V_1_4> 2472 ]; 2473} 2474def SPIRV_D_UserSemantic : I32EnumAttrCase<"UserSemantic", 5635> { 2475 list<Availability> availability = [ 2476 MinVersion<SPIRV_V_1_4> 2477 ]; 2478} 2479def SPIRV_D_UserTypeGOOGLE : I32EnumAttrCase<"UserTypeGOOGLE", 5636> { 2480 list<Availability> availability = [ 2481 Extension<[SPV_GOOGLE_user_type]> 2482 ]; 2483} 2484def SPIRV_D_FunctionRoundingModeINTEL : I32EnumAttrCase<"FunctionRoundingModeINTEL", 5822> { 2485 list<Availability> availability = [ 2486 Capability<[SPIRV_C_FunctionFloatControlINTEL]> 2487 ]; 2488} 2489def SPIRV_D_FunctionDenormModeINTEL : I32EnumAttrCase<"FunctionDenormModeINTEL", 5823> { 2490 list<Availability> availability = [ 2491 Capability<[SPIRV_C_FunctionFloatControlINTEL]> 2492 ]; 2493} 2494def SPIRV_D_RegisterINTEL : I32EnumAttrCase<"RegisterINTEL", 5825> { 2495 list<Availability> availability = [ 2496 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2497 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2498 ]; 2499} 2500def SPIRV_D_MemoryINTEL : I32EnumAttrCase<"MemoryINTEL", 5826> { 2501 list<Availability> availability = [ 2502 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2503 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2504 ]; 2505} 2506def SPIRV_D_NumbanksINTEL : I32EnumAttrCase<"NumbanksINTEL", 5827> { 2507 list<Availability> availability = [ 2508 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2509 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2510 ]; 2511} 2512def SPIRV_D_BankwidthINTEL : I32EnumAttrCase<"BankwidthINTEL", 5828> { 2513 list<Availability> availability = [ 2514 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2515 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2516 ]; 2517} 2518def SPIRV_D_MaxPrivateCopiesINTEL : I32EnumAttrCase<"MaxPrivateCopiesINTEL", 5829> { 2519 list<Availability> availability = [ 2520 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2521 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2522 ]; 2523} 2524def SPIRV_D_SinglepumpINTEL : I32EnumAttrCase<"SinglepumpINTEL", 5830> { 2525 list<Availability> availability = [ 2526 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2527 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2528 ]; 2529} 2530def SPIRV_D_DoublepumpINTEL : I32EnumAttrCase<"DoublepumpINTEL", 5831> { 2531 list<Availability> availability = [ 2532 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2533 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2534 ]; 2535} 2536def SPIRV_D_MaxReplicatesINTEL : I32EnumAttrCase<"MaxReplicatesINTEL", 5832> { 2537 list<Availability> availability = [ 2538 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2539 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2540 ]; 2541} 2542def SPIRV_D_SimpleDualPortINTEL : I32EnumAttrCase<"SimpleDualPortINTEL", 5833> { 2543 list<Availability> availability = [ 2544 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2545 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2546 ]; 2547} 2548def SPIRV_D_MergeINTEL : I32EnumAttrCase<"MergeINTEL", 5834> { 2549 list<Availability> availability = [ 2550 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2551 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2552 ]; 2553} 2554def SPIRV_D_BankBitsINTEL : I32EnumAttrCase<"BankBitsINTEL", 5835> { 2555 list<Availability> availability = [ 2556 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2557 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2558 ]; 2559} 2560def SPIRV_D_ForcePow2DepthINTEL : I32EnumAttrCase<"ForcePow2DepthINTEL", 5836> { 2561 list<Availability> availability = [ 2562 Extension<[SPV_INTEL_fpga_memory_attributes]>, 2563 Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]> 2564 ]; 2565} 2566def SPIRV_D_BurstCoalesceINTEL : I32EnumAttrCase<"BurstCoalesceINTEL", 5899> { 2567 list<Availability> availability = [ 2568 Capability<[SPIRV_C_FPGAMemoryAccessesINTEL]> 2569 ]; 2570} 2571def SPIRV_D_CacheSizeINTEL : I32EnumAttrCase<"CacheSizeINTEL", 5900> { 2572 list<Availability> availability = [ 2573 Capability<[SPIRV_C_FPGAMemoryAccessesINTEL]> 2574 ]; 2575} 2576def SPIRV_D_DontStaticallyCoalesceINTEL : I32EnumAttrCase<"DontStaticallyCoalesceINTEL", 5901> { 2577 list<Availability> availability = [ 2578 Capability<[SPIRV_C_FPGAMemoryAccessesINTEL]> 2579 ]; 2580} 2581def SPIRV_D_PrefetchINTEL : I32EnumAttrCase<"PrefetchINTEL", 5902> { 2582 list<Availability> availability = [ 2583 Capability<[SPIRV_C_FPGAMemoryAccessesINTEL]> 2584 ]; 2585} 2586def SPIRV_D_StallEnableINTEL : I32EnumAttrCase<"StallEnableINTEL", 5905> { 2587 list<Availability> availability = [ 2588 Capability<[SPIRV_C_FPGAClusterAttributesINTEL]> 2589 ]; 2590} 2591def SPIRV_D_FuseLoopsInFunctionINTEL : I32EnumAttrCase<"FuseLoopsInFunctionINTEL", 5907> { 2592 list<Availability> availability = [ 2593 Capability<[SPIRV_C_LoopFuseINTEL]> 2594 ]; 2595} 2596def SPIRV_D_AliasScopeINTEL : I32EnumAttrCase<"AliasScopeINTEL", 5914> { 2597 list<Availability> availability = [ 2598 Capability<[SPIRV_C_MemoryAccessAliasingINTEL]> 2599 ]; 2600} 2601def SPIRV_D_NoAliasINTEL : I32EnumAttrCase<"NoAliasINTEL", 5915> { 2602 list<Availability> availability = [ 2603 Capability<[SPIRV_C_MemoryAccessAliasingINTEL]> 2604 ]; 2605} 2606def SPIRV_D_BufferLocationINTEL : I32EnumAttrCase<"BufferLocationINTEL", 5921> { 2607 list<Availability> availability = [ 2608 Capability<[SPIRV_C_FPGABufferLocationINTEL]> 2609 ]; 2610} 2611def SPIRV_D_IOPipeStorageINTEL : I32EnumAttrCase<"IOPipeStorageINTEL", 5944> { 2612 list<Availability> availability = [ 2613 Capability<[SPIRV_C_IOPipesINTEL]> 2614 ]; 2615} 2616def SPIRV_D_FunctionFloatingPointModeINTEL : I32EnumAttrCase<"FunctionFloatingPointModeINTEL", 6080> { 2617 list<Availability> availability = [ 2618 Capability<[SPIRV_C_FunctionFloatControlINTEL]> 2619 ]; 2620} 2621def SPIRV_D_SingleElementVectorINTEL : I32EnumAttrCase<"SingleElementVectorINTEL", 6085> { 2622 list<Availability> availability = [ 2623 Capability<[SPIRV_C_VectorComputeINTEL]> 2624 ]; 2625} 2626def SPIRV_D_VectorComputeCallableFunctionINTEL : I32EnumAttrCase<"VectorComputeCallableFunctionINTEL", 6087> { 2627 list<Availability> availability = [ 2628 Capability<[SPIRV_C_VectorComputeINTEL]> 2629 ]; 2630} 2631def SPIRV_D_MediaBlockIOINTEL : I32EnumAttrCase<"MediaBlockIOINTEL", 6140> { 2632 list<Availability> availability = [ 2633 Capability<[SPIRV_C_VectorComputeINTEL]> 2634 ]; 2635} 2636def SPIRV_D_CacheControlLoadINTEL : I32EnumAttrCase<"CacheControlLoadINTEL", 6442> { 2637 list<Availability> availability = [ 2638 Capability<[SPIRV_C_CacheControlsINTEL]> 2639 ]; 2640} 2641def SPIRV_D_CacheControlStoreINTEL : I32EnumAttrCase<"CacheControlStoreINTEL", 6443> { 2642 list<Availability> availability = [ 2643 Capability<[SPIRV_C_CacheControlsINTEL]> 2644 ]; 2645} 2646 2647def SPIRV_DecorationAttr : 2648 SPIRV_I32EnumAttr<"Decoration", "valid SPIR-V Decoration", "decoration", [ 2649 SPIRV_D_RelaxedPrecision, SPIRV_D_SpecId, SPIRV_D_Block, SPIRV_D_BufferBlock, 2650 SPIRV_D_RowMajor, SPIRV_D_ColMajor, SPIRV_D_ArrayStride, SPIRV_D_MatrixStride, 2651 SPIRV_D_GLSLShared, SPIRV_D_GLSLPacked, SPIRV_D_CPacked, SPIRV_D_BuiltIn, 2652 SPIRV_D_NoPerspective, SPIRV_D_Flat, SPIRV_D_Patch, SPIRV_D_Centroid, SPIRV_D_Sample, 2653 SPIRV_D_Invariant, SPIRV_D_Restrict, SPIRV_D_Aliased, SPIRV_D_Volatile, SPIRV_D_Constant, 2654 SPIRV_D_Coherent, SPIRV_D_NonWritable, SPIRV_D_NonReadable, SPIRV_D_Uniform, 2655 SPIRV_D_UniformId, SPIRV_D_SaturatedConversion, SPIRV_D_Stream, SPIRV_D_Location, 2656 SPIRV_D_Component, SPIRV_D_Index, SPIRV_D_Binding, SPIRV_D_DescriptorSet, SPIRV_D_Offset, 2657 SPIRV_D_XfbBuffer, SPIRV_D_XfbStride, SPIRV_D_FuncParamAttr, SPIRV_D_FPRoundingMode, 2658 SPIRV_D_FPFastMathMode, SPIRV_D_LinkageAttributes, SPIRV_D_NoContraction, 2659 SPIRV_D_InputAttachmentIndex, SPIRV_D_Alignment, SPIRV_D_MaxByteOffset, 2660 SPIRV_D_AlignmentId, SPIRV_D_MaxByteOffsetId, SPIRV_D_NoSignedWrap, 2661 SPIRV_D_NoUnsignedWrap, SPIRV_D_ExplicitInterpAMD, SPIRV_D_OverrideCoverageNV, 2662 SPIRV_D_PassthroughNV, SPIRV_D_ViewportRelativeNV, 2663 SPIRV_D_SecondaryViewportRelativeNV, SPIRV_D_PerPrimitiveNV, SPIRV_D_PerViewNV, 2664 SPIRV_D_PerTaskNV, SPIRV_D_PerVertexKHR, SPIRV_D_NonUniform, SPIRV_D_RestrictPointer, 2665 SPIRV_D_AliasedPointer, SPIRV_D_BindlessSamplerNV, SPIRV_D_BindlessImageNV, 2666 SPIRV_D_BoundSamplerNV, SPIRV_D_BoundImageNV, SPIRV_D_SIMTCallINTEL, 2667 SPIRV_D_ReferencedIndirectlyINTEL, SPIRV_D_ClobberINTEL, SPIRV_D_SideEffectsINTEL, 2668 SPIRV_D_VectorComputeVariableINTEL, SPIRV_D_FuncParamIOKindINTEL, 2669 SPIRV_D_VectorComputeFunctionINTEL, SPIRV_D_StackCallINTEL, 2670 SPIRV_D_GlobalVariableOffsetINTEL, SPIRV_D_CounterBuffer, SPIRV_D_UserSemantic, 2671 SPIRV_D_UserTypeGOOGLE, SPIRV_D_FunctionRoundingModeINTEL, 2672 SPIRV_D_FunctionDenormModeINTEL, SPIRV_D_RegisterINTEL, SPIRV_D_MemoryINTEL, 2673 SPIRV_D_NumbanksINTEL, SPIRV_D_BankwidthINTEL, SPIRV_D_MaxPrivateCopiesINTEL, 2674 SPIRV_D_SinglepumpINTEL, SPIRV_D_DoublepumpINTEL, SPIRV_D_MaxReplicatesINTEL, 2675 SPIRV_D_SimpleDualPortINTEL, SPIRV_D_MergeINTEL, SPIRV_D_BankBitsINTEL, 2676 SPIRV_D_ForcePow2DepthINTEL, SPIRV_D_BurstCoalesceINTEL, SPIRV_D_CacheSizeINTEL, 2677 SPIRV_D_DontStaticallyCoalesceINTEL, SPIRV_D_PrefetchINTEL, SPIRV_D_StallEnableINTEL, 2678 SPIRV_D_FuseLoopsInFunctionINTEL, SPIRV_D_AliasScopeINTEL, SPIRV_D_NoAliasINTEL, 2679 SPIRV_D_BufferLocationINTEL, SPIRV_D_IOPipeStorageINTEL, 2680 SPIRV_D_FunctionFloatingPointModeINTEL, SPIRV_D_SingleElementVectorINTEL, 2681 SPIRV_D_VectorComputeCallableFunctionINTEL, SPIRV_D_MediaBlockIOINTEL, 2682 SPIRV_D_CacheControlLoadINTEL, SPIRV_D_CacheControlStoreINTEL 2683 ]>; 2684 2685def SPIRV_D_1D : I32EnumAttrCase<"Dim1D", 0> { 2686 list<Availability> availability = [ 2687 Capability<[SPIRV_C_Image1D, SPIRV_C_Sampled1D]> 2688 ]; 2689} 2690def SPIRV_D_2D : I32EnumAttrCase<"Dim2D", 1> { 2691 list<Availability> availability = [ 2692 Capability<[SPIRV_C_ImageMSArray, SPIRV_C_Kernel, SPIRV_C_Shader]> 2693 ]; 2694} 2695def SPIRV_D_3D : I32EnumAttrCase<"Dim3D", 2>; 2696def SPIRV_D_Cube : I32EnumAttrCase<"Cube", 3> { 2697 list<Availability> availability = [ 2698 Capability<[SPIRV_C_ImageCubeArray, SPIRV_C_Shader]> 2699 ]; 2700} 2701def SPIRV_D_Rect : I32EnumAttrCase<"Rect", 4> { 2702 list<Availability> availability = [ 2703 Capability<[SPIRV_C_ImageRect, SPIRV_C_SampledRect]> 2704 ]; 2705} 2706def SPIRV_D_Buffer : I32EnumAttrCase<"Buffer", 5> { 2707 list<Availability> availability = [ 2708 Capability<[SPIRV_C_ImageBuffer, SPIRV_C_SampledBuffer]> 2709 ]; 2710} 2711def SPIRV_D_SubpassData : I32EnumAttrCase<"SubpassData", 6> { 2712 list<Availability> availability = [ 2713 Capability<[SPIRV_C_InputAttachment]> 2714 ]; 2715} 2716 2717def SPIRV_DimAttr : 2718 SPIRV_I32EnumAttr<"Dim", "valid SPIR-V Dim", "dim", [ 2719 SPIRV_D_1D, SPIRV_D_2D, SPIRV_D_3D, SPIRV_D_Cube, SPIRV_D_Rect, SPIRV_D_Buffer, 2720 SPIRV_D_SubpassData 2721 ]>; 2722 2723def SPIRV_EM_Invocations : I32EnumAttrCase<"Invocations", 0> { 2724 list<Availability> availability = [ 2725 Capability<[SPIRV_C_Geometry]> 2726 ]; 2727} 2728def SPIRV_EM_SpacingEqual : I32EnumAttrCase<"SpacingEqual", 1> { 2729 list<Availability> availability = [ 2730 Capability<[SPIRV_C_Tessellation]> 2731 ]; 2732} 2733def SPIRV_EM_SpacingFractionalEven : I32EnumAttrCase<"SpacingFractionalEven", 2> { 2734 list<Availability> availability = [ 2735 Capability<[SPIRV_C_Tessellation]> 2736 ]; 2737} 2738def SPIRV_EM_SpacingFractionalOdd : I32EnumAttrCase<"SpacingFractionalOdd", 3> { 2739 list<Availability> availability = [ 2740 Capability<[SPIRV_C_Tessellation]> 2741 ]; 2742} 2743def SPIRV_EM_VertexOrderCw : I32EnumAttrCase<"VertexOrderCw", 4> { 2744 list<Availability> availability = [ 2745 Capability<[SPIRV_C_Tessellation]> 2746 ]; 2747} 2748def SPIRV_EM_VertexOrderCcw : I32EnumAttrCase<"VertexOrderCcw", 5> { 2749 list<Availability> availability = [ 2750 Capability<[SPIRV_C_Tessellation]> 2751 ]; 2752} 2753def SPIRV_EM_PixelCenterInteger : I32EnumAttrCase<"PixelCenterInteger", 6> { 2754 list<Availability> availability = [ 2755 Capability<[SPIRV_C_Shader]> 2756 ]; 2757} 2758def SPIRV_EM_OriginUpperLeft : I32EnumAttrCase<"OriginUpperLeft", 7> { 2759 list<Availability> availability = [ 2760 Capability<[SPIRV_C_Shader]> 2761 ]; 2762} 2763def SPIRV_EM_OriginLowerLeft : I32EnumAttrCase<"OriginLowerLeft", 8> { 2764 list<Availability> availability = [ 2765 Capability<[SPIRV_C_Shader]> 2766 ]; 2767} 2768def SPIRV_EM_EarlyFragmentTests : I32EnumAttrCase<"EarlyFragmentTests", 9> { 2769 list<Availability> availability = [ 2770 Capability<[SPIRV_C_Shader]> 2771 ]; 2772} 2773def SPIRV_EM_PointMode : I32EnumAttrCase<"PointMode", 10> { 2774 list<Availability> availability = [ 2775 Capability<[SPIRV_C_Tessellation]> 2776 ]; 2777} 2778def SPIRV_EM_Xfb : I32EnumAttrCase<"Xfb", 11> { 2779 list<Availability> availability = [ 2780 Capability<[SPIRV_C_TransformFeedback]> 2781 ]; 2782} 2783def SPIRV_EM_DepthReplacing : I32EnumAttrCase<"DepthReplacing", 12> { 2784 list<Availability> availability = [ 2785 Capability<[SPIRV_C_Shader]> 2786 ]; 2787} 2788def SPIRV_EM_DepthGreater : I32EnumAttrCase<"DepthGreater", 14> { 2789 list<Availability> availability = [ 2790 Capability<[SPIRV_C_Shader]> 2791 ]; 2792} 2793def SPIRV_EM_DepthLess : I32EnumAttrCase<"DepthLess", 15> { 2794 list<Availability> availability = [ 2795 Capability<[SPIRV_C_Shader]> 2796 ]; 2797} 2798def SPIRV_EM_DepthUnchanged : I32EnumAttrCase<"DepthUnchanged", 16> { 2799 list<Availability> availability = [ 2800 Capability<[SPIRV_C_Shader]> 2801 ]; 2802} 2803def SPIRV_EM_LocalSize : I32EnumAttrCase<"LocalSize", 17>; 2804def SPIRV_EM_LocalSizeHint : I32EnumAttrCase<"LocalSizeHint", 18> { 2805 list<Availability> availability = [ 2806 Capability<[SPIRV_C_Kernel]> 2807 ]; 2808} 2809def SPIRV_EM_InputPoints : I32EnumAttrCase<"InputPoints", 19> { 2810 list<Availability> availability = [ 2811 Capability<[SPIRV_C_Geometry]> 2812 ]; 2813} 2814def SPIRV_EM_InputLines : I32EnumAttrCase<"InputLines", 20> { 2815 list<Availability> availability = [ 2816 Capability<[SPIRV_C_Geometry]> 2817 ]; 2818} 2819def SPIRV_EM_InputLinesAdjacency : I32EnumAttrCase<"InputLinesAdjacency", 21> { 2820 list<Availability> availability = [ 2821 Capability<[SPIRV_C_Geometry]> 2822 ]; 2823} 2824def SPIRV_EM_Triangles : I32EnumAttrCase<"Triangles", 22> { 2825 list<Availability> availability = [ 2826 Capability<[SPIRV_C_Geometry, SPIRV_C_Tessellation]> 2827 ]; 2828} 2829def SPIRV_EM_InputTrianglesAdjacency : I32EnumAttrCase<"InputTrianglesAdjacency", 23> { 2830 list<Availability> availability = [ 2831 Capability<[SPIRV_C_Geometry]> 2832 ]; 2833} 2834def SPIRV_EM_Quads : I32EnumAttrCase<"Quads", 24> { 2835 list<Availability> availability = [ 2836 Capability<[SPIRV_C_Tessellation]> 2837 ]; 2838} 2839def SPIRV_EM_Isolines : I32EnumAttrCase<"Isolines", 25> { 2840 list<Availability> availability = [ 2841 Capability<[SPIRV_C_Tessellation]> 2842 ]; 2843} 2844def SPIRV_EM_OutputVertices : I32EnumAttrCase<"OutputVertices", 26> { 2845 list<Availability> availability = [ 2846 Capability<[SPIRV_C_Geometry, SPIRV_C_MeshShadingNV, SPIRV_C_Tessellation]> 2847 ]; 2848} 2849def SPIRV_EM_OutputPoints : I32EnumAttrCase<"OutputPoints", 27> { 2850 list<Availability> availability = [ 2851 Capability<[SPIRV_C_Geometry, SPIRV_C_MeshShadingNV]> 2852 ]; 2853} 2854def SPIRV_EM_OutputLineStrip : I32EnumAttrCase<"OutputLineStrip", 28> { 2855 list<Availability> availability = [ 2856 Capability<[SPIRV_C_Geometry]> 2857 ]; 2858} 2859def SPIRV_EM_OutputTriangleStrip : I32EnumAttrCase<"OutputTriangleStrip", 29> { 2860 list<Availability> availability = [ 2861 Capability<[SPIRV_C_Geometry]> 2862 ]; 2863} 2864def SPIRV_EM_VecTypeHint : I32EnumAttrCase<"VecTypeHint", 30> { 2865 list<Availability> availability = [ 2866 Capability<[SPIRV_C_Kernel]> 2867 ]; 2868} 2869def SPIRV_EM_ContractionOff : I32EnumAttrCase<"ContractionOff", 31> { 2870 list<Availability> availability = [ 2871 Capability<[SPIRV_C_Kernel]> 2872 ]; 2873} 2874def SPIRV_EM_Initializer : I32EnumAttrCase<"Initializer", 33> { 2875 list<Availability> availability = [ 2876 MinVersion<SPIRV_V_1_1>, 2877 Capability<[SPIRV_C_Kernel]> 2878 ]; 2879} 2880def SPIRV_EM_Finalizer : I32EnumAttrCase<"Finalizer", 34> { 2881 list<Availability> availability = [ 2882 MinVersion<SPIRV_V_1_1>, 2883 Capability<[SPIRV_C_Kernel]> 2884 ]; 2885} 2886def SPIRV_EM_SubgroupSize : I32EnumAttrCase<"SubgroupSize", 35> { 2887 list<Availability> availability = [ 2888 MinVersion<SPIRV_V_1_1>, 2889 Capability<[SPIRV_C_SubgroupDispatch]> 2890 ]; 2891} 2892def SPIRV_EM_SubgroupsPerWorkgroup : I32EnumAttrCase<"SubgroupsPerWorkgroup", 36> { 2893 list<Availability> availability = [ 2894 MinVersion<SPIRV_V_1_1>, 2895 Capability<[SPIRV_C_SubgroupDispatch]> 2896 ]; 2897} 2898def SPIRV_EM_SubgroupsPerWorkgroupId : I32EnumAttrCase<"SubgroupsPerWorkgroupId", 37> { 2899 list<Availability> availability = [ 2900 MinVersion<SPIRV_V_1_2>, 2901 Capability<[SPIRV_C_SubgroupDispatch]> 2902 ]; 2903} 2904def SPIRV_EM_LocalSizeId : I32EnumAttrCase<"LocalSizeId", 38> { 2905 list<Availability> availability = [ 2906 MinVersion<SPIRV_V_1_2> 2907 ]; 2908} 2909def SPIRV_EM_LocalSizeHintId : I32EnumAttrCase<"LocalSizeHintId", 39> { 2910 list<Availability> availability = [ 2911 MinVersion<SPIRV_V_1_2>, 2912 Capability<[SPIRV_C_Kernel]> 2913 ]; 2914} 2915def SPIRV_EM_SubgroupUniformControlFlowKHR : I32EnumAttrCase<"SubgroupUniformControlFlowKHR", 4421> { 2916 list<Availability> availability = [ 2917 Extension<[SPV_KHR_subgroup_uniform_control_flow]>, 2918 Capability<[SPIRV_C_Shader]> 2919 ]; 2920} 2921def SPIRV_EM_PostDepthCoverage : I32EnumAttrCase<"PostDepthCoverage", 4446> { 2922 list<Availability> availability = [ 2923 Extension<[SPV_KHR_post_depth_coverage]>, 2924 Capability<[SPIRV_C_SampleMaskPostDepthCoverage]> 2925 ]; 2926} 2927def SPIRV_EM_DenormPreserve : I32EnumAttrCase<"DenormPreserve", 4459> { 2928 list<Availability> availability = [ 2929 Extension<[SPV_KHR_float_controls]>, 2930 Capability<[SPIRV_C_DenormPreserve]> 2931 ]; 2932} 2933def SPIRV_EM_DenormFlushToZero : I32EnumAttrCase<"DenormFlushToZero", 4460> { 2934 list<Availability> availability = [ 2935 Extension<[SPV_KHR_float_controls]>, 2936 Capability<[SPIRV_C_DenormFlushToZero]> 2937 ]; 2938} 2939def SPIRV_EM_SignedZeroInfNanPreserve : I32EnumAttrCase<"SignedZeroInfNanPreserve", 4461> { 2940 list<Availability> availability = [ 2941 Extension<[SPV_KHR_float_controls]>, 2942 Capability<[SPIRV_C_SignedZeroInfNanPreserve]> 2943 ]; 2944} 2945def SPIRV_EM_RoundingModeRTE : I32EnumAttrCase<"RoundingModeRTE", 4462> { 2946 list<Availability> availability = [ 2947 Extension<[SPV_KHR_float_controls]>, 2948 Capability<[SPIRV_C_RoundingModeRTE]> 2949 ]; 2950} 2951def SPIRV_EM_RoundingModeRTZ : I32EnumAttrCase<"RoundingModeRTZ", 4463> { 2952 list<Availability> availability = [ 2953 Extension<[SPV_KHR_float_controls]>, 2954 Capability<[SPIRV_C_RoundingModeRTZ]> 2955 ]; 2956} 2957def SPIRV_EM_EarlyAndLateFragmentTestsAMD : I32EnumAttrCase<"EarlyAndLateFragmentTestsAMD", 5017> { 2958 list<Availability> availability = [ 2959 Extension<[SPV_AMD_shader_early_and_late_fragment_tests]>, 2960 Capability<[SPIRV_C_Shader]> 2961 ]; 2962} 2963def SPIRV_EM_StencilRefReplacingEXT : I32EnumAttrCase<"StencilRefReplacingEXT", 5027> { 2964 list<Availability> availability = [ 2965 Extension<[SPV_EXT_shader_stencil_export]>, 2966 Capability<[SPIRV_C_StencilExportEXT]> 2967 ]; 2968} 2969def SPIRV_EM_StencilRefUnchangedFrontAMD : I32EnumAttrCase<"StencilRefUnchangedFrontAMD", 5079> { 2970 list<Availability> availability = [ 2971 Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>, 2972 Capability<[SPIRV_C_StencilExportEXT]> 2973 ]; 2974} 2975def SPIRV_EM_StencilRefGreaterFrontAMD : I32EnumAttrCase<"StencilRefGreaterFrontAMD", 5080> { 2976 list<Availability> availability = [ 2977 Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>, 2978 Capability<[SPIRV_C_StencilExportEXT]> 2979 ]; 2980} 2981def SPIRV_EM_StencilRefLessFrontAMD : I32EnumAttrCase<"StencilRefLessFrontAMD", 5081> { 2982 list<Availability> availability = [ 2983 Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>, 2984 Capability<[SPIRV_C_StencilExportEXT]> 2985 ]; 2986} 2987def SPIRV_EM_StencilRefUnchangedBackAMD : I32EnumAttrCase<"StencilRefUnchangedBackAMD", 5082> { 2988 list<Availability> availability = [ 2989 Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>, 2990 Capability<[SPIRV_C_StencilExportEXT]> 2991 ]; 2992} 2993def SPIRV_EM_StencilRefGreaterBackAMD : I32EnumAttrCase<"StencilRefGreaterBackAMD", 5083> { 2994 list<Availability> availability = [ 2995 Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>, 2996 Capability<[SPIRV_C_StencilExportEXT]> 2997 ]; 2998} 2999def SPIRV_EM_StencilRefLessBackAMD : I32EnumAttrCase<"StencilRefLessBackAMD", 5084> { 3000 list<Availability> availability = [ 3001 Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>, 3002 Capability<[SPIRV_C_StencilExportEXT]> 3003 ]; 3004} 3005def SPIRV_EM_OutputLinesNV : I32EnumAttrCase<"OutputLinesNV", 5269> { 3006 list<Availability> availability = [ 3007 Extension<[SPV_NV_mesh_shader]>, 3008 Capability<[SPIRV_C_MeshShadingNV]> 3009 ]; 3010} 3011def SPIRV_EM_OutputPrimitivesNV : I32EnumAttrCase<"OutputPrimitivesNV", 5270> { 3012 list<Availability> availability = [ 3013 Extension<[SPV_NV_mesh_shader]>, 3014 Capability<[SPIRV_C_MeshShadingNV]> 3015 ]; 3016} 3017def SPIRV_EM_DerivativeGroupQuadsNV : I32EnumAttrCase<"DerivativeGroupQuadsNV", 5289> { 3018 list<Availability> availability = [ 3019 Extension<[SPV_NV_compute_shader_derivatives]>, 3020 Capability<[SPIRV_C_ComputeDerivativeGroupQuadsNV]> 3021 ]; 3022} 3023def SPIRV_EM_DerivativeGroupLinearNV : I32EnumAttrCase<"DerivativeGroupLinearNV", 5290> { 3024 list<Availability> availability = [ 3025 Extension<[SPV_NV_compute_shader_derivatives]>, 3026 Capability<[SPIRV_C_ComputeDerivativeGroupLinearNV]> 3027 ]; 3028} 3029def SPIRV_EM_OutputTrianglesNV : I32EnumAttrCase<"OutputTrianglesNV", 5298> { 3030 list<Availability> availability = [ 3031 Extension<[SPV_NV_mesh_shader]>, 3032 Capability<[SPIRV_C_MeshShadingNV]> 3033 ]; 3034} 3035def SPIRV_EM_PixelInterlockOrderedEXT : I32EnumAttrCase<"PixelInterlockOrderedEXT", 5366> { 3036 list<Availability> availability = [ 3037 Extension<[SPV_EXT_fragment_shader_interlock]>, 3038 Capability<[SPIRV_C_FragmentShaderPixelInterlockEXT]> 3039 ]; 3040} 3041def SPIRV_EM_PixelInterlockUnorderedEXT : I32EnumAttrCase<"PixelInterlockUnorderedEXT", 5367> { 3042 list<Availability> availability = [ 3043 Extension<[SPV_EXT_fragment_shader_interlock]>, 3044 Capability<[SPIRV_C_FragmentShaderPixelInterlockEXT]> 3045 ]; 3046} 3047def SPIRV_EM_SampleInterlockOrderedEXT : I32EnumAttrCase<"SampleInterlockOrderedEXT", 5368> { 3048 list<Availability> availability = [ 3049 Extension<[SPV_EXT_fragment_shader_interlock]>, 3050 Capability<[SPIRV_C_FragmentShaderSampleInterlockEXT]> 3051 ]; 3052} 3053def SPIRV_EM_SampleInterlockUnorderedEXT : I32EnumAttrCase<"SampleInterlockUnorderedEXT", 5369> { 3054 list<Availability> availability = [ 3055 Extension<[SPV_EXT_fragment_shader_interlock]>, 3056 Capability<[SPIRV_C_FragmentShaderSampleInterlockEXT]> 3057 ]; 3058} 3059def SPIRV_EM_ShadingRateInterlockOrderedEXT : I32EnumAttrCase<"ShadingRateInterlockOrderedEXT", 5370> { 3060 list<Availability> availability = [ 3061 Extension<[SPV_EXT_fragment_shader_interlock]>, 3062 Capability<[SPIRV_C_FragmentShaderShadingRateInterlockEXT]> 3063 ]; 3064} 3065def SPIRV_EM_ShadingRateInterlockUnorderedEXT : I32EnumAttrCase<"ShadingRateInterlockUnorderedEXT", 5371> { 3066 list<Availability> availability = [ 3067 Extension<[SPV_EXT_fragment_shader_interlock]>, 3068 Capability<[SPIRV_C_FragmentShaderShadingRateInterlockEXT]> 3069 ]; 3070} 3071def SPIRV_EM_SharedLocalMemorySizeINTEL : I32EnumAttrCase<"SharedLocalMemorySizeINTEL", 5618> { 3072 list<Availability> availability = [ 3073 Capability<[SPIRV_C_VectorComputeINTEL]> 3074 ]; 3075} 3076def SPIRV_EM_RoundingModeRTPINTEL : I32EnumAttrCase<"RoundingModeRTPINTEL", 5620> { 3077 list<Availability> availability = [ 3078 Capability<[SPIRV_C_RoundToInfinityINTEL]> 3079 ]; 3080} 3081def SPIRV_EM_RoundingModeRTNINTEL : I32EnumAttrCase<"RoundingModeRTNINTEL", 5621> { 3082 list<Availability> availability = [ 3083 Capability<[SPIRV_C_RoundToInfinityINTEL]> 3084 ]; 3085} 3086def SPIRV_EM_FloatingPointModeALTINTEL : I32EnumAttrCase<"FloatingPointModeALTINTEL", 5622> { 3087 list<Availability> availability = [ 3088 Capability<[SPIRV_C_RoundToInfinityINTEL]> 3089 ]; 3090} 3091def SPIRV_EM_FloatingPointModeIEEEINTEL : I32EnumAttrCase<"FloatingPointModeIEEEINTEL", 5623> { 3092 list<Availability> availability = [ 3093 Capability<[SPIRV_C_RoundToInfinityINTEL]> 3094 ]; 3095} 3096def SPIRV_EM_MaxWorkgroupSizeINTEL : I32EnumAttrCase<"MaxWorkgroupSizeINTEL", 5893> { 3097 list<Availability> availability = [ 3098 Extension<[SPV_INTEL_kernel_attributes]>, 3099 Capability<[SPIRV_C_KernelAttributesINTEL]> 3100 ]; 3101} 3102def SPIRV_EM_MaxWorkDimINTEL : I32EnumAttrCase<"MaxWorkDimINTEL", 5894> { 3103 list<Availability> availability = [ 3104 Extension<[SPV_INTEL_kernel_attributes]>, 3105 Capability<[SPIRV_C_KernelAttributesINTEL]> 3106 ]; 3107} 3108def SPIRV_EM_NoGlobalOffsetINTEL : I32EnumAttrCase<"NoGlobalOffsetINTEL", 5895> { 3109 list<Availability> availability = [ 3110 Extension<[SPV_INTEL_kernel_attributes]>, 3111 Capability<[SPIRV_C_KernelAttributesINTEL]> 3112 ]; 3113} 3114def SPIRV_EM_NumSIMDWorkitemsINTEL : I32EnumAttrCase<"NumSIMDWorkitemsINTEL", 5896> { 3115 list<Availability> availability = [ 3116 Extension<[SPV_INTEL_kernel_attributes]>, 3117 Capability<[SPIRV_C_FPGAKernelAttributesINTEL]> 3118 ]; 3119} 3120def SPIRV_EM_SchedulerTargetFmaxMhzINTEL : I32EnumAttrCase<"SchedulerTargetFmaxMhzINTEL", 5903> { 3121 list<Availability> availability = [ 3122 Capability<[SPIRV_C_FPGAKernelAttributesINTEL]> 3123 ]; 3124} 3125def SPIRV_EM_StreamingInterfaceINTEL : I32EnumAttrCase<"StreamingInterfaceINTEL", 6154> { 3126 list<Availability> availability = [ 3127 Capability<[SPIRV_C_FPGAKernelAttributesINTEL]> 3128 ]; 3129} 3130def SPIRV_EM_NamedBarrierCountINTEL : I32EnumAttrCase<"NamedBarrierCountINTEL", 6417> { 3131 list<Availability> availability = [ 3132 Capability<[SPIRV_C_VectorComputeINTEL]> 3133 ]; 3134} 3135 3136def SPIRV_ExecutionModeAttr : 3137 SPIRV_I32EnumAttr<"ExecutionMode", "valid SPIR-V ExecutionMode", "execution_mode", [ 3138 SPIRV_EM_Invocations, SPIRV_EM_SpacingEqual, SPIRV_EM_SpacingFractionalEven, 3139 SPIRV_EM_SpacingFractionalOdd, SPIRV_EM_VertexOrderCw, SPIRV_EM_VertexOrderCcw, 3140 SPIRV_EM_PixelCenterInteger, SPIRV_EM_OriginUpperLeft, SPIRV_EM_OriginLowerLeft, 3141 SPIRV_EM_EarlyFragmentTests, SPIRV_EM_PointMode, SPIRV_EM_Xfb, SPIRV_EM_DepthReplacing, 3142 SPIRV_EM_DepthGreater, SPIRV_EM_DepthLess, SPIRV_EM_DepthUnchanged, SPIRV_EM_LocalSize, 3143 SPIRV_EM_LocalSizeHint, SPIRV_EM_InputPoints, SPIRV_EM_InputLines, 3144 SPIRV_EM_InputLinesAdjacency, SPIRV_EM_Triangles, SPIRV_EM_InputTrianglesAdjacency, 3145 SPIRV_EM_Quads, SPIRV_EM_Isolines, SPIRV_EM_OutputVertices, SPIRV_EM_OutputPoints, 3146 SPIRV_EM_OutputLineStrip, SPIRV_EM_OutputTriangleStrip, SPIRV_EM_VecTypeHint, 3147 SPIRV_EM_ContractionOff, SPIRV_EM_Initializer, SPIRV_EM_Finalizer, 3148 SPIRV_EM_SubgroupSize, SPIRV_EM_SubgroupsPerWorkgroup, 3149 SPIRV_EM_SubgroupsPerWorkgroupId, SPIRV_EM_LocalSizeId, SPIRV_EM_LocalSizeHintId, 3150 SPIRV_EM_SubgroupUniformControlFlowKHR, SPIRV_EM_PostDepthCoverage, 3151 SPIRV_EM_DenormPreserve, SPIRV_EM_DenormFlushToZero, 3152 SPIRV_EM_SignedZeroInfNanPreserve, SPIRV_EM_RoundingModeRTE, 3153 SPIRV_EM_RoundingModeRTZ, SPIRV_EM_EarlyAndLateFragmentTestsAMD, 3154 SPIRV_EM_StencilRefReplacingEXT, SPIRV_EM_StencilRefUnchangedFrontAMD, 3155 SPIRV_EM_StencilRefGreaterFrontAMD, SPIRV_EM_StencilRefLessFrontAMD, 3156 SPIRV_EM_StencilRefUnchangedBackAMD, SPIRV_EM_StencilRefGreaterBackAMD, 3157 SPIRV_EM_StencilRefLessBackAMD, SPIRV_EM_OutputLinesNV, SPIRV_EM_OutputPrimitivesNV, 3158 SPIRV_EM_DerivativeGroupQuadsNV, SPIRV_EM_DerivativeGroupLinearNV, 3159 SPIRV_EM_OutputTrianglesNV, SPIRV_EM_PixelInterlockOrderedEXT, 3160 SPIRV_EM_PixelInterlockUnorderedEXT, SPIRV_EM_SampleInterlockOrderedEXT, 3161 SPIRV_EM_SampleInterlockUnorderedEXT, SPIRV_EM_ShadingRateInterlockOrderedEXT, 3162 SPIRV_EM_ShadingRateInterlockUnorderedEXT, SPIRV_EM_SharedLocalMemorySizeINTEL, 3163 SPIRV_EM_RoundingModeRTPINTEL, SPIRV_EM_RoundingModeRTNINTEL, 3164 SPIRV_EM_FloatingPointModeALTINTEL, SPIRV_EM_FloatingPointModeIEEEINTEL, 3165 SPIRV_EM_MaxWorkgroupSizeINTEL, SPIRV_EM_MaxWorkDimINTEL, 3166 SPIRV_EM_NoGlobalOffsetINTEL, SPIRV_EM_NumSIMDWorkitemsINTEL, 3167 SPIRV_EM_SchedulerTargetFmaxMhzINTEL, SPIRV_EM_StreamingInterfaceINTEL, 3168 SPIRV_EM_NamedBarrierCountINTEL 3169 ]>; 3170 3171def SPIRV_EM_Vertex : I32EnumAttrCase<"Vertex", 0> { 3172 list<Availability> availability = [ 3173 Capability<[SPIRV_C_Shader]> 3174 ]; 3175} 3176def SPIRV_EM_TessellationControl : I32EnumAttrCase<"TessellationControl", 1> { 3177 list<Availability> availability = [ 3178 Capability<[SPIRV_C_Tessellation]> 3179 ]; 3180} 3181def SPIRV_EM_TessellationEvaluation : I32EnumAttrCase<"TessellationEvaluation", 2> { 3182 list<Availability> availability = [ 3183 Capability<[SPIRV_C_Tessellation]> 3184 ]; 3185} 3186def SPIRV_EM_Geometry : I32EnumAttrCase<"Geometry", 3> { 3187 list<Availability> availability = [ 3188 Capability<[SPIRV_C_Geometry]> 3189 ]; 3190} 3191def SPIRV_EM_Fragment : I32EnumAttrCase<"Fragment", 4> { 3192 list<Availability> availability = [ 3193 Capability<[SPIRV_C_Shader]> 3194 ]; 3195} 3196def SPIRV_EM_GLCompute : I32EnumAttrCase<"GLCompute", 5> { 3197 list<Availability> availability = [ 3198 Capability<[SPIRV_C_Shader]> 3199 ]; 3200} 3201def SPIRV_EM_Kernel : I32EnumAttrCase<"Kernel", 6> { 3202 list<Availability> availability = [ 3203 Capability<[SPIRV_C_Kernel]> 3204 ]; 3205} 3206def SPIRV_EM_TaskNV : I32EnumAttrCase<"TaskNV", 5267> { 3207 list<Availability> availability = [ 3208 Capability<[SPIRV_C_MeshShadingNV]> 3209 ]; 3210} 3211def SPIRV_EM_MeshNV : I32EnumAttrCase<"MeshNV", 5268> { 3212 list<Availability> availability = [ 3213 Capability<[SPIRV_C_MeshShadingNV]> 3214 ]; 3215} 3216def SPIRV_EM_RayGenerationKHR : I32EnumAttrCase<"RayGenerationKHR", 5313> { 3217 list<Availability> availability = [ 3218 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3219 ]; 3220} 3221def SPIRV_EM_IntersectionKHR : I32EnumAttrCase<"IntersectionKHR", 5314> { 3222 list<Availability> availability = [ 3223 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3224 ]; 3225} 3226def SPIRV_EM_AnyHitKHR : I32EnumAttrCase<"AnyHitKHR", 5315> { 3227 list<Availability> availability = [ 3228 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3229 ]; 3230} 3231def SPIRV_EM_ClosestHitKHR : I32EnumAttrCase<"ClosestHitKHR", 5316> { 3232 list<Availability> availability = [ 3233 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3234 ]; 3235} 3236def SPIRV_EM_MissKHR : I32EnumAttrCase<"MissKHR", 5317> { 3237 list<Availability> availability = [ 3238 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3239 ]; 3240} 3241def SPIRV_EM_CallableKHR : I32EnumAttrCase<"CallableKHR", 5318> { 3242 list<Availability> availability = [ 3243 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3244 ]; 3245} 3246 3247def SPIRV_ExecutionModelAttr : 3248 SPIRV_I32EnumAttr<"ExecutionModel", "valid SPIR-V ExecutionModel", "execution_model", [ 3249 SPIRV_EM_Vertex, SPIRV_EM_TessellationControl, SPIRV_EM_TessellationEvaluation, 3250 SPIRV_EM_Geometry, SPIRV_EM_Fragment, SPIRV_EM_GLCompute, SPIRV_EM_Kernel, 3251 SPIRV_EM_TaskNV, SPIRV_EM_MeshNV, SPIRV_EM_RayGenerationKHR, SPIRV_EM_IntersectionKHR, 3252 SPIRV_EM_AnyHitKHR, SPIRV_EM_ClosestHitKHR, SPIRV_EM_MissKHR, SPIRV_EM_CallableKHR 3253 ]>; 3254 3255def SPIRV_FC_None : I32BitEnumAttrCaseNone<"None">; 3256def SPIRV_FC_Inline : I32BitEnumAttrCaseBit<"Inline", 0>; 3257def SPIRV_FC_DontInline : I32BitEnumAttrCaseBit<"DontInline", 1>; 3258def SPIRV_FC_Pure : I32BitEnumAttrCaseBit<"Pure", 2>; 3259def SPIRV_FC_Const : I32BitEnumAttrCaseBit<"Const", 3>; 3260def SPIRV_FC_OptNoneINTEL : I32BitEnumAttrCaseBit<"OptNoneINTEL", 16> { 3261 list<Availability> availability = [ 3262 Capability<[SPIRV_C_OptNoneINTEL]> 3263 ]; 3264} 3265 3266def SPIRV_FPRM_RTE : I32EnumAttrCase<"RTE", 0>; 3267def SPIRV_FPRM_RTZ : I32EnumAttrCase<"RTZ", 1>; 3268def SPIRV_FPRM_RTP : I32EnumAttrCase<"RTP", 2>; 3269def SPIRV_FPRM_RTN : I32EnumAttrCase<"RTN", 3>; 3270 3271// TODO: Enforce SPIR-V spec validation rule for Shader capability: only permit 3272// FPRoundingMode on a value stored to certain storage classes? 3273// (The OpenCL environment also has FPRoundingMode rules, but different.) 3274def SPIRV_FPRoundingModeAttr : 3275 SPIRV_I32EnumAttr<"FPRoundingMode", "valid SPIR-V FPRoundingMode", "fp_rounding_mode", [ 3276 SPIRV_FPRM_RTE, SPIRV_FPRM_RTZ, SPIRV_FPRM_RTP, SPIRV_FPRM_RTN 3277 ]>; 3278 3279def SPIRV_FunctionControlAttr : 3280 SPIRV_BitEnumAttr<"FunctionControl", "valid SPIR-V FunctionControl", "function_control", [ 3281 SPIRV_FC_None, SPIRV_FC_Inline, SPIRV_FC_DontInline, SPIRV_FC_Pure, SPIRV_FC_Const, 3282 SPIRV_FC_OptNoneINTEL 3283 ]>; 3284 3285def SPIRV_GO_Reduce : I32EnumAttrCase<"Reduce", 0> { 3286 list<Availability> availability = [ 3287 Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformBallot, SPIRV_C_Kernel]> 3288 ]; 3289} 3290def SPIRV_GO_InclusiveScan : I32EnumAttrCase<"InclusiveScan", 1> { 3291 list<Availability> availability = [ 3292 Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformBallot, SPIRV_C_Kernel]> 3293 ]; 3294} 3295def SPIRV_GO_ExclusiveScan : I32EnumAttrCase<"ExclusiveScan", 2> { 3296 list<Availability> availability = [ 3297 Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformBallot, SPIRV_C_Kernel]> 3298 ]; 3299} 3300def SPIRV_GO_ClusteredReduce : I32EnumAttrCase<"ClusteredReduce", 3> { 3301 list<Availability> availability = [ 3302 MinVersion<SPIRV_V_1_3>, 3303 Capability<[SPIRV_C_GroupNonUniformClustered]> 3304 ]; 3305} 3306def SPIRV_GO_PartitionedReduceNV : I32EnumAttrCase<"PartitionedReduceNV", 6> { 3307 list<Availability> availability = [ 3308 Extension<[SPV_NV_shader_subgroup_partitioned]>, 3309 Capability<[SPIRV_C_GroupNonUniformPartitionedNV]> 3310 ]; 3311} 3312def SPIRV_GO_PartitionedInclusiveScanNV : I32EnumAttrCase<"PartitionedInclusiveScanNV", 7> { 3313 list<Availability> availability = [ 3314 Extension<[SPV_NV_shader_subgroup_partitioned]>, 3315 Capability<[SPIRV_C_GroupNonUniformPartitionedNV]> 3316 ]; 3317} 3318def SPIRV_GO_PartitionedExclusiveScanNV : I32EnumAttrCase<"PartitionedExclusiveScanNV", 8> { 3319 list<Availability> availability = [ 3320 Extension<[SPV_NV_shader_subgroup_partitioned]>, 3321 Capability<[SPIRV_C_GroupNonUniformPartitionedNV]> 3322 ]; 3323} 3324 3325def SPIRV_GroupOperationAttr : 3326 SPIRV_I32EnumAttr<"GroupOperation", "valid SPIR-V GroupOperation", "group_operation", [ 3327 SPIRV_GO_Reduce, SPIRV_GO_InclusiveScan, SPIRV_GO_ExclusiveScan, 3328 SPIRV_GO_ClusteredReduce, SPIRV_GO_PartitionedReduceNV, 3329 SPIRV_GO_PartitionedInclusiveScanNV, SPIRV_GO_PartitionedExclusiveScanNV 3330 ]>; 3331 3332def SPIRV_IF_Unknown : I32EnumAttrCase<"Unknown", 0>; 3333def SPIRV_IF_Rgba32f : I32EnumAttrCase<"Rgba32f", 1> { 3334 list<Availability> availability = [ 3335 Capability<[SPIRV_C_Shader]> 3336 ]; 3337} 3338def SPIRV_IF_Rgba16f : I32EnumAttrCase<"Rgba16f", 2> { 3339 list<Availability> availability = [ 3340 Capability<[SPIRV_C_Shader]> 3341 ]; 3342} 3343def SPIRV_IF_R32f : I32EnumAttrCase<"R32f", 3> { 3344 list<Availability> availability = [ 3345 Capability<[SPIRV_C_Shader]> 3346 ]; 3347} 3348def SPIRV_IF_Rgba8 : I32EnumAttrCase<"Rgba8", 4> { 3349 list<Availability> availability = [ 3350 Capability<[SPIRV_C_Shader]> 3351 ]; 3352} 3353def SPIRV_IF_Rgba8Snorm : I32EnumAttrCase<"Rgba8Snorm", 5> { 3354 list<Availability> availability = [ 3355 Capability<[SPIRV_C_Shader]> 3356 ]; 3357} 3358def SPIRV_IF_Rg32f : I32EnumAttrCase<"Rg32f", 6> { 3359 list<Availability> availability = [ 3360 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3361 ]; 3362} 3363def SPIRV_IF_Rg16f : I32EnumAttrCase<"Rg16f", 7> { 3364 list<Availability> availability = [ 3365 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3366 ]; 3367} 3368def SPIRV_IF_R11fG11fB10f : I32EnumAttrCase<"R11fG11fB10f", 8> { 3369 list<Availability> availability = [ 3370 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3371 ]; 3372} 3373def SPIRV_IF_R16f : I32EnumAttrCase<"R16f", 9> { 3374 list<Availability> availability = [ 3375 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3376 ]; 3377} 3378def SPIRV_IF_Rgba16 : I32EnumAttrCase<"Rgba16", 10> { 3379 list<Availability> availability = [ 3380 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3381 ]; 3382} 3383def SPIRV_IF_Rgb10A2 : I32EnumAttrCase<"Rgb10A2", 11> { 3384 list<Availability> availability = [ 3385 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3386 ]; 3387} 3388def SPIRV_IF_Rg16 : I32EnumAttrCase<"Rg16", 12> { 3389 list<Availability> availability = [ 3390 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3391 ]; 3392} 3393def SPIRV_IF_Rg8 : I32EnumAttrCase<"Rg8", 13> { 3394 list<Availability> availability = [ 3395 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3396 ]; 3397} 3398def SPIRV_IF_R16 : I32EnumAttrCase<"R16", 14> { 3399 list<Availability> availability = [ 3400 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3401 ]; 3402} 3403def SPIRV_IF_R8 : I32EnumAttrCase<"R8", 15> { 3404 list<Availability> availability = [ 3405 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3406 ]; 3407} 3408def SPIRV_IF_Rgba16Snorm : I32EnumAttrCase<"Rgba16Snorm", 16> { 3409 list<Availability> availability = [ 3410 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3411 ]; 3412} 3413def SPIRV_IF_Rg16Snorm : I32EnumAttrCase<"Rg16Snorm", 17> { 3414 list<Availability> availability = [ 3415 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3416 ]; 3417} 3418def SPIRV_IF_Rg8Snorm : I32EnumAttrCase<"Rg8Snorm", 18> { 3419 list<Availability> availability = [ 3420 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3421 ]; 3422} 3423def SPIRV_IF_R16Snorm : I32EnumAttrCase<"R16Snorm", 19> { 3424 list<Availability> availability = [ 3425 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3426 ]; 3427} 3428def SPIRV_IF_R8Snorm : I32EnumAttrCase<"R8Snorm", 20> { 3429 list<Availability> availability = [ 3430 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3431 ]; 3432} 3433def SPIRV_IF_Rgba32i : I32EnumAttrCase<"Rgba32i", 21> { 3434 list<Availability> availability = [ 3435 Capability<[SPIRV_C_Shader]> 3436 ]; 3437} 3438def SPIRV_IF_Rgba16i : I32EnumAttrCase<"Rgba16i", 22> { 3439 list<Availability> availability = [ 3440 Capability<[SPIRV_C_Shader]> 3441 ]; 3442} 3443def SPIRV_IF_Rgba8i : I32EnumAttrCase<"Rgba8i", 23> { 3444 list<Availability> availability = [ 3445 Capability<[SPIRV_C_Shader]> 3446 ]; 3447} 3448def SPIRV_IF_R32i : I32EnumAttrCase<"R32i", 24> { 3449 list<Availability> availability = [ 3450 Capability<[SPIRV_C_Shader]> 3451 ]; 3452} 3453def SPIRV_IF_Rg32i : I32EnumAttrCase<"Rg32i", 25> { 3454 list<Availability> availability = [ 3455 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3456 ]; 3457} 3458def SPIRV_IF_Rg16i : I32EnumAttrCase<"Rg16i", 26> { 3459 list<Availability> availability = [ 3460 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3461 ]; 3462} 3463def SPIRV_IF_Rg8i : I32EnumAttrCase<"Rg8i", 27> { 3464 list<Availability> availability = [ 3465 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3466 ]; 3467} 3468def SPIRV_IF_R16i : I32EnumAttrCase<"R16i", 28> { 3469 list<Availability> availability = [ 3470 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3471 ]; 3472} 3473def SPIRV_IF_R8i : I32EnumAttrCase<"R8i", 29> { 3474 list<Availability> availability = [ 3475 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3476 ]; 3477} 3478def SPIRV_IF_Rgba32ui : I32EnumAttrCase<"Rgba32ui", 30> { 3479 list<Availability> availability = [ 3480 Capability<[SPIRV_C_Shader]> 3481 ]; 3482} 3483def SPIRV_IF_Rgba16ui : I32EnumAttrCase<"Rgba16ui", 31> { 3484 list<Availability> availability = [ 3485 Capability<[SPIRV_C_Shader]> 3486 ]; 3487} 3488def SPIRV_IF_Rgba8ui : I32EnumAttrCase<"Rgba8ui", 32> { 3489 list<Availability> availability = [ 3490 Capability<[SPIRV_C_Shader]> 3491 ]; 3492} 3493def SPIRV_IF_R32ui : I32EnumAttrCase<"R32ui", 33> { 3494 list<Availability> availability = [ 3495 Capability<[SPIRV_C_Shader]> 3496 ]; 3497} 3498def SPIRV_IF_Rgb10a2ui : I32EnumAttrCase<"Rgb10a2ui", 34> { 3499 list<Availability> availability = [ 3500 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3501 ]; 3502} 3503def SPIRV_IF_Rg32ui : I32EnumAttrCase<"Rg32ui", 35> { 3504 list<Availability> availability = [ 3505 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3506 ]; 3507} 3508def SPIRV_IF_Rg16ui : I32EnumAttrCase<"Rg16ui", 36> { 3509 list<Availability> availability = [ 3510 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3511 ]; 3512} 3513def SPIRV_IF_Rg8ui : I32EnumAttrCase<"Rg8ui", 37> { 3514 list<Availability> availability = [ 3515 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3516 ]; 3517} 3518def SPIRV_IF_R16ui : I32EnumAttrCase<"R16ui", 38> { 3519 list<Availability> availability = [ 3520 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3521 ]; 3522} 3523def SPIRV_IF_R8ui : I32EnumAttrCase<"R8ui", 39> { 3524 list<Availability> availability = [ 3525 Capability<[SPIRV_C_StorageImageExtendedFormats]> 3526 ]; 3527} 3528def SPIRV_IF_R64ui : I32EnumAttrCase<"R64ui", 40> { 3529 list<Availability> availability = [ 3530 Capability<[SPIRV_C_Int64ImageEXT]> 3531 ]; 3532} 3533def SPIRV_IF_R64i : I32EnumAttrCase<"R64i", 41> { 3534 list<Availability> availability = [ 3535 Capability<[SPIRV_C_Int64ImageEXT]> 3536 ]; 3537} 3538 3539def SPIRV_ImageFormatAttr : 3540 SPIRV_I32EnumAttr<"ImageFormat", "valid SPIR-V ImageFormat", "image_format", [ 3541 SPIRV_IF_Unknown, SPIRV_IF_Rgba32f, SPIRV_IF_Rgba16f, SPIRV_IF_R32f, SPIRV_IF_Rgba8, 3542 SPIRV_IF_Rgba8Snorm, SPIRV_IF_Rg32f, SPIRV_IF_Rg16f, SPIRV_IF_R11fG11fB10f, 3543 SPIRV_IF_R16f, SPIRV_IF_Rgba16, SPIRV_IF_Rgb10A2, SPIRV_IF_Rg16, SPIRV_IF_Rg8, 3544 SPIRV_IF_R16, SPIRV_IF_R8, SPIRV_IF_Rgba16Snorm, SPIRV_IF_Rg16Snorm, SPIRV_IF_Rg8Snorm, 3545 SPIRV_IF_R16Snorm, SPIRV_IF_R8Snorm, SPIRV_IF_Rgba32i, SPIRV_IF_Rgba16i, SPIRV_IF_Rgba8i, 3546 SPIRV_IF_R32i, SPIRV_IF_Rg32i, SPIRV_IF_Rg16i, SPIRV_IF_Rg8i, SPIRV_IF_R16i, SPIRV_IF_R8i, 3547 SPIRV_IF_Rgba32ui, SPIRV_IF_Rgba16ui, SPIRV_IF_Rgba8ui, SPIRV_IF_R32ui, 3548 SPIRV_IF_Rgb10a2ui, SPIRV_IF_Rg32ui, SPIRV_IF_Rg16ui, SPIRV_IF_Rg8ui, SPIRV_IF_R16ui, 3549 SPIRV_IF_R8ui, SPIRV_IF_R64ui, SPIRV_IF_R64i 3550 ]>; 3551 3552def SPIRV_IO_None : I32BitEnumAttrCaseNone<"None">; 3553def SPIRV_IO_Bias : I32BitEnumAttrCaseBit<"Bias", 0> { 3554 list<Availability> availability = [ 3555 Capability<[SPIRV_C_Shader]> 3556 ]; 3557} 3558def SPIRV_IO_Lod : I32BitEnumAttrCaseBit<"Lod", 1>; 3559def SPIRV_IO_Grad : I32BitEnumAttrCaseBit<"Grad", 2>; 3560def SPIRV_IO_ConstOffset : I32BitEnumAttrCaseBit<"ConstOffset", 3>; 3561def SPIRV_IO_Offset : I32BitEnumAttrCaseBit<"Offset", 4> { 3562 list<Availability> availability = [ 3563 Capability<[SPIRV_C_ImageGatherExtended]> 3564 ]; 3565} 3566def SPIRV_IO_ConstOffsets : I32BitEnumAttrCaseBit<"ConstOffsets", 5> { 3567 list<Availability> availability = [ 3568 Capability<[SPIRV_C_ImageGatherExtended]> 3569 ]; 3570} 3571def SPIRV_IO_Sample : I32BitEnumAttrCaseBit<"Sample", 6>; 3572def SPIRV_IO_MinLod : I32BitEnumAttrCaseBit<"MinLod", 7> { 3573 list<Availability> availability = [ 3574 Capability<[SPIRV_C_MinLod]> 3575 ]; 3576} 3577def SPIRV_IO_MakeTexelAvailable : I32BitEnumAttrCaseBit<"MakeTexelAvailable", 8> { 3578 list<Availability> availability = [ 3579 MinVersion<SPIRV_V_1_5>, 3580 Capability<[SPIRV_C_VulkanMemoryModel]> 3581 ]; 3582} 3583def SPIRV_IO_MakeTexelVisible : I32BitEnumAttrCaseBit<"MakeTexelVisible", 9> { 3584 list<Availability> availability = [ 3585 MinVersion<SPIRV_V_1_5>, 3586 Capability<[SPIRV_C_VulkanMemoryModel]> 3587 ]; 3588} 3589def SPIRV_IO_NonPrivateTexel : I32BitEnumAttrCaseBit<"NonPrivateTexel", 10> { 3590 list<Availability> availability = [ 3591 MinVersion<SPIRV_V_1_5>, 3592 Capability<[SPIRV_C_VulkanMemoryModel]> 3593 ]; 3594} 3595def SPIRV_IO_VolatileTexel : I32BitEnumAttrCaseBit<"VolatileTexel", 11> { 3596 list<Availability> availability = [ 3597 MinVersion<SPIRV_V_1_5>, 3598 Capability<[SPIRV_C_VulkanMemoryModel]> 3599 ]; 3600} 3601def SPIRV_IO_SignExtend : I32BitEnumAttrCaseBit<"SignExtend", 12> { 3602 list<Availability> availability = [ 3603 MinVersion<SPIRV_V_1_4> 3604 ]; 3605} 3606def SPIRV_IO_Offsets : I32BitEnumAttrCaseBit<"Offsets", 16>; 3607def SPIRV_IO_ZeroExtend : I32BitEnumAttrCaseBit<"ZeroExtend", 13> { 3608 list<Availability> availability = [ 3609 MinVersion<SPIRV_V_1_4> 3610 ]; 3611} 3612def SPIRV_IO_Nontemporal : I32BitEnumAttrCaseBit<"Nontemporal", 14> { 3613 list<Availability> availability = [ 3614 MinVersion<SPIRV_V_1_6> 3615 ]; 3616} 3617 3618def SPIRV_ImageOperandsAttr : 3619 SPIRV_BitEnumAttr<"ImageOperands", "valid SPIR-V ImageOperands", "image_operands", [ 3620 SPIRV_IO_None, SPIRV_IO_Bias, SPIRV_IO_Lod, SPIRV_IO_Grad, SPIRV_IO_ConstOffset, 3621 SPIRV_IO_Offset, SPIRV_IO_ConstOffsets, SPIRV_IO_Sample, SPIRV_IO_MinLod, 3622 SPIRV_IO_MakeTexelAvailable, SPIRV_IO_MakeTexelVisible, SPIRV_IO_NonPrivateTexel, 3623 SPIRV_IO_VolatileTexel, SPIRV_IO_SignExtend, SPIRV_IO_Offsets, SPIRV_IO_ZeroExtend, 3624 SPIRV_IO_Nontemporal 3625 ]>; 3626 3627def SPIRV_LT_Export : I32EnumAttrCase<"Export", 0> { 3628 list<Availability> availability = [ 3629 Capability<[SPIRV_C_Linkage]> 3630 ]; 3631} 3632def SPIRV_LT_Import : I32EnumAttrCase<"Import", 1> { 3633 list<Availability> availability = [ 3634 Capability<[SPIRV_C_Linkage]> 3635 ]; 3636} 3637def SPIRV_LT_LinkOnceODR : I32EnumAttrCase<"LinkOnceODR", 2> { 3638 list<Availability> availability = [ 3639 Extension<[SPV_KHR_linkonce_odr]>, 3640 Capability<[SPIRV_C_Linkage]> 3641 ]; 3642} 3643 3644def SPIRV_LinkageTypeAttr : 3645 SPIRV_I32EnumAttr<"LinkageType", "valid SPIR-V LinkageType", "linkage_type", [ 3646 SPIRV_LT_Export, SPIRV_LT_Import, SPIRV_LT_LinkOnceODR 3647 ]>; 3648 3649def SPIRV_LC_None : I32BitEnumAttrCaseNone<"None">; 3650def SPIRV_LC_Unroll : I32BitEnumAttrCaseBit<"Unroll", 0>; 3651def SPIRV_LC_DontUnroll : I32BitEnumAttrCaseBit<"DontUnroll", 1>; 3652def SPIRV_LC_DependencyInfinite : I32BitEnumAttrCaseBit<"DependencyInfinite", 2> { 3653 list<Availability> availability = [ 3654 MinVersion<SPIRV_V_1_1> 3655 ]; 3656} 3657def SPIRV_LC_DependencyLength : I32BitEnumAttrCaseBit<"DependencyLength", 3> { 3658 list<Availability> availability = [ 3659 MinVersion<SPIRV_V_1_1> 3660 ]; 3661} 3662def SPIRV_LC_MinIterations : I32BitEnumAttrCaseBit<"MinIterations", 4> { 3663 list<Availability> availability = [ 3664 MinVersion<SPIRV_V_1_4> 3665 ]; 3666} 3667def SPIRV_LC_MaxIterations : I32BitEnumAttrCaseBit<"MaxIterations", 5> { 3668 list<Availability> availability = [ 3669 MinVersion<SPIRV_V_1_4> 3670 ]; 3671} 3672def SPIRV_LC_IterationMultiple : I32BitEnumAttrCaseBit<"IterationMultiple", 6> { 3673 list<Availability> availability = [ 3674 MinVersion<SPIRV_V_1_4> 3675 ]; 3676} 3677def SPIRV_LC_PeelCount : I32BitEnumAttrCaseBit<"PeelCount", 7> { 3678 list<Availability> availability = [ 3679 MinVersion<SPIRV_V_1_4> 3680 ]; 3681} 3682def SPIRV_LC_PartialCount : I32BitEnumAttrCaseBit<"PartialCount", 8> { 3683 list<Availability> availability = [ 3684 MinVersion<SPIRV_V_1_4> 3685 ]; 3686} 3687def SPIRV_LC_InitiationIntervalINTEL : I32BitEnumAttrCaseBit<"InitiationIntervalINTEL", 16> { 3688 list<Availability> availability = [ 3689 Extension<[SPV_INTEL_fpga_loop_controls]>, 3690 Capability<[SPIRV_C_FPGALoopControlsINTEL]> 3691 ]; 3692} 3693def SPIRV_LC_LoopCoalesceINTEL : I32BitEnumAttrCaseBit<"LoopCoalesceINTEL", 20> { 3694 list<Availability> availability = [ 3695 Extension<[SPV_INTEL_fpga_loop_controls]>, 3696 Capability<[SPIRV_C_FPGALoopControlsINTEL]> 3697 ]; 3698} 3699def SPIRV_LC_MaxConcurrencyINTEL : I32BitEnumAttrCaseBit<"MaxConcurrencyINTEL", 17> { 3700 list<Availability> availability = [ 3701 Extension<[SPV_INTEL_fpga_loop_controls]>, 3702 Capability<[SPIRV_C_FPGALoopControlsINTEL]> 3703 ]; 3704} 3705def SPIRV_LC_MaxInterleavingINTEL : I32BitEnumAttrCaseBit<"MaxInterleavingINTEL", 21> { 3706 list<Availability> availability = [ 3707 Extension<[SPV_INTEL_fpga_loop_controls]>, 3708 Capability<[SPIRV_C_FPGALoopControlsINTEL]> 3709 ]; 3710} 3711def SPIRV_LC_DependencyArrayINTEL : I32BitEnumAttrCaseBit<"DependencyArrayINTEL", 18> { 3712 list<Availability> availability = [ 3713 Extension<[SPV_INTEL_fpga_loop_controls]>, 3714 Capability<[SPIRV_C_FPGALoopControlsINTEL]> 3715 ]; 3716} 3717def SPIRV_LC_SpeculatedIterationsINTEL : I32BitEnumAttrCaseBit<"SpeculatedIterationsINTEL", 22> { 3718 list<Availability> availability = [ 3719 Extension<[SPV_INTEL_fpga_loop_controls]>, 3720 Capability<[SPIRV_C_FPGALoopControlsINTEL]> 3721 ]; 3722} 3723def SPIRV_LC_PipelineEnableINTEL : I32BitEnumAttrCaseBit<"PipelineEnableINTEL", 19> { 3724 list<Availability> availability = [ 3725 Extension<[SPV_INTEL_fpga_loop_controls]>, 3726 Capability<[SPIRV_C_FPGALoopControlsINTEL]> 3727 ]; 3728} 3729def SPIRV_LC_NoFusionINTEL : I32BitEnumAttrCaseBit<"NoFusionINTEL", 23> { 3730 list<Availability> availability = [ 3731 Extension<[SPV_INTEL_fpga_loop_controls]>, 3732 Capability<[SPIRV_C_FPGALoopControlsINTEL]> 3733 ]; 3734} 3735 3736def SPIRV_LoopControlAttr : 3737 SPIRV_BitEnumAttr<"LoopControl", "valid SPIR-V LoopControl", "loop_control", [ 3738 SPIRV_LC_None, SPIRV_LC_Unroll, SPIRV_LC_DontUnroll, SPIRV_LC_DependencyInfinite, 3739 SPIRV_LC_DependencyLength, SPIRV_LC_MinIterations, SPIRV_LC_MaxIterations, 3740 SPIRV_LC_IterationMultiple, SPIRV_LC_PeelCount, SPIRV_LC_PartialCount, 3741 SPIRV_LC_InitiationIntervalINTEL, SPIRV_LC_LoopCoalesceINTEL, 3742 SPIRV_LC_MaxConcurrencyINTEL, SPIRV_LC_MaxInterleavingINTEL, 3743 SPIRV_LC_DependencyArrayINTEL, SPIRV_LC_SpeculatedIterationsINTEL, 3744 SPIRV_LC_PipelineEnableINTEL, SPIRV_LC_NoFusionINTEL 3745 ]>; 3746 3747def SPIRV_MA_None : I32BitEnumAttrCaseNone<"None">; 3748def SPIRV_MA_Volatile : I32BitEnumAttrCaseBit<"Volatile", 0>; 3749def SPIRV_MA_Aligned : I32BitEnumAttrCaseBit<"Aligned", 1>; 3750def SPIRV_MA_Nontemporal : I32BitEnumAttrCaseBit<"Nontemporal", 2>; 3751def SPIRV_MA_MakePointerAvailable : I32BitEnumAttrCaseBit<"MakePointerAvailable", 3> { 3752 list<Availability> availability = [ 3753 MinVersion<SPIRV_V_1_5>, 3754 Capability<[SPIRV_C_VulkanMemoryModel]> 3755 ]; 3756} 3757def SPIRV_MA_MakePointerVisible : I32BitEnumAttrCaseBit<"MakePointerVisible", 4> { 3758 list<Availability> availability = [ 3759 MinVersion<SPIRV_V_1_5>, 3760 Capability<[SPIRV_C_VulkanMemoryModel]> 3761 ]; 3762} 3763def SPIRV_MA_NonPrivatePointer : I32BitEnumAttrCaseBit<"NonPrivatePointer", 5> { 3764 list<Availability> availability = [ 3765 MinVersion<SPIRV_V_1_5>, 3766 Capability<[SPIRV_C_VulkanMemoryModel]> 3767 ]; 3768} 3769def SPIRV_MA_AliasScopeINTELMask : I32BitEnumAttrCaseBit<"AliasScopeINTELMask", 16> { 3770 list<Availability> availability = [ 3771 Extension<[SPV_INTEL_memory_access_aliasing]>, 3772 Capability<[SPIRV_C_MemoryAccessAliasingINTEL]> 3773 ]; 3774} 3775def SPIRV_MA_NoAliasINTELMask : I32BitEnumAttrCaseBit<"NoAliasINTELMask", 17> { 3776 list<Availability> availability = [ 3777 Extension<[SPV_INTEL_memory_access_aliasing]>, 3778 Capability<[SPIRV_C_MemoryAccessAliasingINTEL]> 3779 ]; 3780} 3781 3782def SPIRV_MemoryAccessAttr : 3783 SPIRV_BitEnumAttr<"MemoryAccess", "valid SPIR-V MemoryAccess", "memory_access", [ 3784 SPIRV_MA_None, SPIRV_MA_Volatile, SPIRV_MA_Aligned, SPIRV_MA_Nontemporal, 3785 SPIRV_MA_MakePointerAvailable, SPIRV_MA_MakePointerVisible, 3786 SPIRV_MA_NonPrivatePointer, SPIRV_MA_AliasScopeINTELMask, SPIRV_MA_NoAliasINTELMask 3787 ]>; 3788 3789def SPIRV_MM_Simple : I32EnumAttrCase<"Simple", 0> { 3790 list<Availability> availability = [ 3791 Capability<[SPIRV_C_Shader]> 3792 ]; 3793} 3794def SPIRV_MM_GLSL450 : I32EnumAttrCase<"GLSL450", 1> { 3795 list<Availability> availability = [ 3796 Capability<[SPIRV_C_Shader]> 3797 ]; 3798} 3799def SPIRV_MM_OpenCL : I32EnumAttrCase<"OpenCL", 2> { 3800 list<Availability> availability = [ 3801 Capability<[SPIRV_C_Kernel]> 3802 ]; 3803} 3804def SPIRV_MM_Vulkan : I32EnumAttrCase<"Vulkan", 3> { 3805 list<Availability> availability = [ 3806 Extension<[SPV_KHR_vulkan_memory_model]>, 3807 Capability<[SPIRV_C_VulkanMemoryModel]> 3808 ]; 3809} 3810 3811def SPIRV_MemoryModelAttr : 3812 SPIRV_I32EnumAttr<"MemoryModel", "valid SPIR-V MemoryModel", "memory_model", [ 3813 SPIRV_MM_Simple, SPIRV_MM_GLSL450, SPIRV_MM_OpenCL, SPIRV_MM_Vulkan 3814 ]>; 3815 3816def SPIRV_MS_None : I32BitEnumAttrCaseNone<"None">; 3817def SPIRV_MS_Acquire : I32BitEnumAttrCaseBit<"Acquire", 1>; 3818def SPIRV_MS_Release : I32BitEnumAttrCaseBit<"Release", 2>; 3819def SPIRV_MS_AcquireRelease : I32BitEnumAttrCaseBit<"AcquireRelease", 3>; 3820def SPIRV_MS_SequentiallyConsistent : I32BitEnumAttrCaseBit<"SequentiallyConsistent", 4>; 3821def SPIRV_MS_UniformMemory : I32BitEnumAttrCaseBit<"UniformMemory", 6> { 3822 list<Availability> availability = [ 3823 Capability<[SPIRV_C_Shader]> 3824 ]; 3825} 3826def SPIRV_MS_SubgroupMemory : I32BitEnumAttrCaseBit<"SubgroupMemory", 7>; 3827def SPIRV_MS_WorkgroupMemory : I32BitEnumAttrCaseBit<"WorkgroupMemory", 8>; 3828def SPIRV_MS_CrossWorkgroupMemory : I32BitEnumAttrCaseBit<"CrossWorkgroupMemory", 9>; 3829def SPIRV_MS_AtomicCounterMemory : I32BitEnumAttrCaseBit<"AtomicCounterMemory", 10> { 3830 list<Availability> availability = [ 3831 Capability<[SPIRV_C_AtomicStorage]> 3832 ]; 3833} 3834def SPIRV_MS_ImageMemory : I32BitEnumAttrCaseBit<"ImageMemory", 11>; 3835def SPIRV_MS_OutputMemory : I32BitEnumAttrCaseBit<"OutputMemory", 12> { 3836 list<Availability> availability = [ 3837 MinVersion<SPIRV_V_1_5>, 3838 Capability<[SPIRV_C_VulkanMemoryModel]> 3839 ]; 3840} 3841def SPIRV_MS_MakeAvailable : I32BitEnumAttrCaseBit<"MakeAvailable", 13> { 3842 list<Availability> availability = [ 3843 MinVersion<SPIRV_V_1_5>, 3844 Capability<[SPIRV_C_VulkanMemoryModel]> 3845 ]; 3846} 3847def SPIRV_MS_MakeVisible : I32BitEnumAttrCaseBit<"MakeVisible", 14> { 3848 list<Availability> availability = [ 3849 MinVersion<SPIRV_V_1_5>, 3850 Capability<[SPIRV_C_VulkanMemoryModel]> 3851 ]; 3852} 3853def SPIRV_MS_Volatile : I32BitEnumAttrCaseBit<"Volatile", 15> { 3854 list<Availability> availability = [ 3855 Extension<[SPV_KHR_vulkan_memory_model]>, 3856 Capability<[SPIRV_C_VulkanMemoryModel]> 3857 ]; 3858} 3859 3860def SPIRV_MemorySemanticsAttr : 3861 SPIRV_BitEnumAttr<"MemorySemantics", "valid SPIR-V MemorySemantics", "memory_semantics", [ 3862 SPIRV_MS_None, SPIRV_MS_Acquire, SPIRV_MS_Release, SPIRV_MS_AcquireRelease, 3863 SPIRV_MS_SequentiallyConsistent, SPIRV_MS_UniformMemory, SPIRV_MS_SubgroupMemory, 3864 SPIRV_MS_WorkgroupMemory, SPIRV_MS_CrossWorkgroupMemory, 3865 SPIRV_MS_AtomicCounterMemory, SPIRV_MS_ImageMemory, SPIRV_MS_OutputMemory, 3866 SPIRV_MS_MakeAvailable, SPIRV_MS_MakeVisible, SPIRV_MS_Volatile 3867 ]>; 3868 3869def SPIRV_S_CrossDevice : I32EnumAttrCase<"CrossDevice", 0>; 3870def SPIRV_S_Device : I32EnumAttrCase<"Device", 1>; 3871def SPIRV_S_Workgroup : I32EnumAttrCase<"Workgroup", 2>; 3872def SPIRV_S_Subgroup : I32EnumAttrCase<"Subgroup", 3>; 3873def SPIRV_S_Invocation : I32EnumAttrCase<"Invocation", 4>; 3874def SPIRV_S_QueueFamily : I32EnumAttrCase<"QueueFamily", 5> { 3875 list<Availability> availability = [ 3876 MinVersion<SPIRV_V_1_5>, 3877 Capability<[SPIRV_C_VulkanMemoryModel]> 3878 ]; 3879} 3880def SPIRV_S_ShaderCallKHR : I32EnumAttrCase<"ShaderCallKHR", 6> { 3881 list<Availability> availability = [ 3882 Capability<[SPIRV_C_RayTracingKHR]> 3883 ]; 3884} 3885 3886def SPIRV_ScopeAttr : 3887 SPIRV_I32EnumAttr<"Scope", "valid SPIR-V Scope", "scope", [ 3888 SPIRV_S_CrossDevice, SPIRV_S_Device, SPIRV_S_Workgroup, SPIRV_S_Subgroup, 3889 SPIRV_S_Invocation, SPIRV_S_QueueFamily, SPIRV_S_ShaderCallKHR 3890 ]>; 3891 3892def SPIRV_SC_None : I32BitEnumAttrCaseNone<"None">; 3893def SPIRV_SC_Flatten : I32BitEnumAttrCaseBit<"Flatten", 0>; 3894def SPIRV_SC_DontFlatten : I32BitEnumAttrCaseBit<"DontFlatten", 1>; 3895 3896def SPIRV_SelectionControlAttr : 3897 SPIRV_BitEnumAttr<"SelectionControl", "valid SPIR-V SelectionControl", "selection_control", [ 3898 SPIRV_SC_None, SPIRV_SC_Flatten, SPIRV_SC_DontFlatten 3899 ]>; 3900 3901def SPIRV_SC_UniformConstant : I32EnumAttrCase<"UniformConstant", 0>; 3902def SPIRV_SC_Input : I32EnumAttrCase<"Input", 1>; 3903def SPIRV_SC_Uniform : I32EnumAttrCase<"Uniform", 2> { 3904 list<Availability> availability = [ 3905 Capability<[SPIRV_C_Shader]> 3906 ]; 3907} 3908def SPIRV_SC_Output : I32EnumAttrCase<"Output", 3> { 3909 list<Availability> availability = [ 3910 Capability<[SPIRV_C_Shader]> 3911 ]; 3912} 3913def SPIRV_SC_Workgroup : I32EnumAttrCase<"Workgroup", 4>; 3914def SPIRV_SC_CrossWorkgroup : I32EnumAttrCase<"CrossWorkgroup", 5>; 3915def SPIRV_SC_Private : I32EnumAttrCase<"Private", 6> { 3916 list<Availability> availability = [ 3917 Capability<[SPIRV_C_Shader, SPIRV_C_VectorComputeINTEL]> 3918 ]; 3919} 3920def SPIRV_SC_Function : I32EnumAttrCase<"Function", 7>; 3921def SPIRV_SC_Generic : I32EnumAttrCase<"Generic", 8> { 3922 list<Availability> availability = [ 3923 Capability<[SPIRV_C_GenericPointer]> 3924 ]; 3925} 3926def SPIRV_SC_PushConstant : I32EnumAttrCase<"PushConstant", 9> { 3927 list<Availability> availability = [ 3928 Capability<[SPIRV_C_Shader]> 3929 ]; 3930} 3931def SPIRV_SC_AtomicCounter : I32EnumAttrCase<"AtomicCounter", 10> { 3932 list<Availability> availability = [ 3933 Capability<[SPIRV_C_AtomicStorage]> 3934 ]; 3935} 3936def SPIRV_SC_Image : I32EnumAttrCase<"Image", 11>; 3937def SPIRV_SC_StorageBuffer : I32EnumAttrCase<"StorageBuffer", 12> { 3938 list<Availability> availability = [ 3939 Extension<[SPV_KHR_storage_buffer_storage_class, SPV_KHR_variable_pointers]>, 3940 Capability<[SPIRV_C_Shader]> 3941 ]; 3942} 3943def SPIRV_SC_CallableDataKHR : I32EnumAttrCase<"CallableDataKHR", 5328> { 3944 list<Availability> availability = [ 3945 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 3946 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3947 ]; 3948} 3949def SPIRV_SC_IncomingCallableDataKHR : I32EnumAttrCase<"IncomingCallableDataKHR", 5329> { 3950 list<Availability> availability = [ 3951 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 3952 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3953 ]; 3954} 3955def SPIRV_SC_RayPayloadKHR : I32EnumAttrCase<"RayPayloadKHR", 5338> { 3956 list<Availability> availability = [ 3957 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 3958 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3959 ]; 3960} 3961def SPIRV_SC_HitAttributeKHR : I32EnumAttrCase<"HitAttributeKHR", 5339> { 3962 list<Availability> availability = [ 3963 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 3964 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3965 ]; 3966} 3967def SPIRV_SC_IncomingRayPayloadKHR : I32EnumAttrCase<"IncomingRayPayloadKHR", 5342> { 3968 list<Availability> availability = [ 3969 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 3970 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3971 ]; 3972} 3973def SPIRV_SC_ShaderRecordBufferKHR : I32EnumAttrCase<"ShaderRecordBufferKHR", 5343> { 3974 list<Availability> availability = [ 3975 Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>, 3976 Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]> 3977 ]; 3978} 3979def SPIRV_SC_PhysicalStorageBuffer : I32EnumAttrCase<"PhysicalStorageBuffer", 5349> { 3980 list<Availability> availability = [ 3981 Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>, 3982 Capability<[SPIRV_C_PhysicalStorageBufferAddresses]> 3983 ]; 3984} 3985def SPIRV_SC_CodeSectionINTEL : I32EnumAttrCase<"CodeSectionINTEL", 5605> { 3986 list<Availability> availability = [ 3987 Extension<[SPV_INTEL_function_pointers]>, 3988 Capability<[SPIRV_C_FunctionPointersINTEL]> 3989 ]; 3990} 3991def SPIRV_SC_DeviceOnlyINTEL : I32EnumAttrCase<"DeviceOnlyINTEL", 5936> { 3992 list<Availability> availability = [ 3993 Extension<[SPV_INTEL_usm_storage_classes]>, 3994 Capability<[SPIRV_C_USMStorageClassesINTEL]> 3995 ]; 3996} 3997def SPIRV_SC_HostOnlyINTEL : I32EnumAttrCase<"HostOnlyINTEL", 5937> { 3998 list<Availability> availability = [ 3999 Extension<[SPV_INTEL_usm_storage_classes]>, 4000 Capability<[SPIRV_C_USMStorageClassesINTEL]> 4001 ]; 4002} 4003 4004def SPIRV_StorageClassAttr : 4005 SPIRV_I32EnumAttr<"StorageClass", "valid SPIR-V StorageClass", "storage_class", [ 4006 SPIRV_SC_UniformConstant, SPIRV_SC_Input, SPIRV_SC_Uniform, SPIRV_SC_Output, 4007 SPIRV_SC_Workgroup, SPIRV_SC_CrossWorkgroup, SPIRV_SC_Private, SPIRV_SC_Function, 4008 SPIRV_SC_Generic, SPIRV_SC_PushConstant, SPIRV_SC_AtomicCounter, SPIRV_SC_Image, 4009 SPIRV_SC_StorageBuffer, SPIRV_SC_CallableDataKHR, SPIRV_SC_IncomingCallableDataKHR, 4010 SPIRV_SC_RayPayloadKHR, SPIRV_SC_HitAttributeKHR, SPIRV_SC_IncomingRayPayloadKHR, 4011 SPIRV_SC_ShaderRecordBufferKHR, SPIRV_SC_PhysicalStorageBuffer, 4012 SPIRV_SC_CodeSectionINTEL, SPIRV_SC_DeviceOnlyINTEL, SPIRV_SC_HostOnlyINTEL 4013 ]>; 4014 4015def SPIRV_PVF_PackedVectorFormat4x8Bit : I32EnumAttrCase<"PackedVectorFormat4x8Bit", 0> { 4016 list<Availability> availability = [ 4017 MinVersion<SPIRV_V_1_6>, 4018 Extension<[SPV_KHR_integer_dot_product]> 4019 ]; 4020} 4021 4022def SPIRV_PackedVectorFormatAttr : 4023 SPIRV_I32EnumAttr<"PackedVectorFormat", "valid SPIR-V PackedVectorFormat", "packed_vector_format", [ 4024 SPIRV_PVF_PackedVectorFormat4x8Bit 4025 ]>; 4026 4027// End enum section. Generated from SPIR-V spec; DO NOT MODIFY! 4028 4029// Enums added manually that are not part of SPIR-V spec 4030 4031def SPIRV_IDI_NoDepth : I32EnumAttrCase<"NoDepth", 0>; 4032def SPIRV_IDI_IsDepth : I32EnumAttrCase<"IsDepth", 1>; 4033def SPIRV_IDI_DepthUnknown : I32EnumAttrCase<"DepthUnknown", 2>; 4034 4035def SPIRV_DepthAttr : SPIRV_I32EnumAttr< 4036 "ImageDepthInfo", "valid SPIR-V Image Depth specification", 4037 "image_depth_info", [SPIRV_IDI_NoDepth, SPIRV_IDI_IsDepth, SPIRV_IDI_DepthUnknown]>; 4038 4039def SPIRV_IAI_NonArrayed : I32EnumAttrCase<"NonArrayed", 0>; 4040def SPIRV_IAI_Arrayed : I32EnumAttrCase<"Arrayed", 1>; 4041 4042def SPIRV_ArrayedAttr : SPIRV_I32EnumAttr< 4043 "ImageArrayedInfo", "valid SPIR-V Image Arrayed specification", 4044 "image_arrayed_info", [SPIRV_IAI_NonArrayed, SPIRV_IAI_Arrayed]>; 4045 4046def SPIRV_ISI_SingleSampled : I32EnumAttrCase<"SingleSampled", 0>; 4047def SPIRV_ISI_MultiSampled : I32EnumAttrCase<"MultiSampled", 1>; 4048 4049def SPIRV_SamplingAttr : SPIRV_I32EnumAttr< 4050 "ImageSamplingInfo", "valid SPIR-V Image Sampling specification", 4051 "image_sampling_info", [SPIRV_ISI_SingleSampled, SPIRV_ISI_MultiSampled]>; 4052 4053def SPIRV_ISUI_SamplerUnknown : I32EnumAttrCase<"SamplerUnknown", 0>; 4054def SPIRV_ISUI_NeedSampler : I32EnumAttrCase<"NeedSampler", 1>; 4055def SPIRV_ISUI_NoSampler : I32EnumAttrCase<"NoSampler", 2>; 4056 4057def SPIRV_SamplerUseAttr: SPIRV_I32EnumAttr< 4058 "ImageSamplerUseInfo", "valid SPIR-V Sampler Use specification", 4059 "image_sampler_use_info", 4060 [SPIRV_ISUI_SamplerUnknown, SPIRV_ISUI_NeedSampler, SPIRV_ISUI_NoSampler]>; 4061 4062def SPIRV_ML_ColumnMajor : I32EnumAttrCase<"ColumnMajor", 0>; 4063def SPIRV_ML_RowMajor : I32EnumAttrCase<"RowMajor", 1>; 4064def SPIRV_ML_PackedA : I32EnumAttrCase<"PackedA", 2>; 4065def SPIRV_ML_PackedB : I32EnumAttrCase<"PackedB", 3>; 4066 4067def SPIRV_MatrixLayoutAttr : 4068 SPIRV_I32EnumAttr<"MatrixLayout", "valid SPIR-V MatrixLayout", "matrixLayout", [ 4069 SPIRV_ML_ColumnMajor, SPIRV_ML_RowMajor, SPIRV_ML_PackedA, SPIRV_ML_PackedB 4070 ]>; 4071 4072// Cooperative Matrix Use for the SPV_KHR_cooperative_matrix extension. 4073def SPIRV_KHR_CMU_MatrixA : I32EnumAttrCase<"MatrixA", 0>; 4074def SPIRV_KHR_CMU_MatrixB : I32EnumAttrCase<"MatrixB", 1>; 4075def SPIRV_KHR_CMU_MatrixAcc : I32EnumAttrCase<"MatrixAcc", 2>; 4076 4077// NOTE: This is an attribute in the SPIR-V *dialect* but a constant (<id>) in 4078// SPIR-V proper. 4079def SPIRV_KHR_CooperativeMatrixUseAttr : 4080 SPIRV_I32EnumAttr<"CooperativeMatrixUseKHR", 4081 "valid SPIR-V Cooperative Matrix Use (KHR)", 4082 "coop_matrix_use_khr", [ 4083 SPIRV_KHR_CMU_MatrixA, SPIRV_KHR_CMU_MatrixB, SPIRV_KHR_CMU_MatrixAcc 4084 ]>; 4085 4086// Cooperative Matrix Layout for the SPV_KHR_cooperative_matrix extension. 4087def SPIRV_KHR_CML_RowMajor : I32EnumAttrCase<"RowMajor", 0>; 4088def SPIRV_KHR_CML_ColumnMajor : I32EnumAttrCase<"ColumnMajor", 1>; 4089 4090// NOTE: This is an attribute in the SPIR-V *dialect* but a constant (<id>) in 4091// SPIR-V proper. 4092def SPIRV_KHR_CooperativeMatrixLayoutAttr : 4093 SPIRV_I32EnumAttr<"CooperativeMatrixLayoutKHR", 4094 "valid SPIR-V Cooperative Matrix Layout (KHR)", 4095 "coop_matrix_layout_khr", [ 4096 SPIRV_KHR_CML_RowMajor, SPIRV_KHR_CML_ColumnMajor 4097 ]>; 4098 4099// Cooperative Matrix Operands for the SPV_KHR_cooperative_matrix extension. 4100def SPIRV_KHR_CMO_None : I32BitEnumAttrCaseNone<"None">; 4101def SPIRV_KHR_CMO_MatrixA_Signed : I32BitEnumAttrCaseBit<"ASigned", 0>; 4102def SPIRV_KHR_CMO_MatrixB_Signed : I32BitEnumAttrCaseBit<"BSigned", 1>; 4103def SPIRV_KHR_CMO_MatrixC_Signed : I32BitEnumAttrCaseBit<"CSigned", 2>; 4104def SPIRV_KHR_CMO_Result_Signed : I32BitEnumAttrCaseBit<"ResultSigned", 3>; 4105def SPIRV_KHR_CMO_AccSat : I32BitEnumAttrCaseBit<"AccSat", 4>; 4106 4107def SPIRV_KHR_CooperativeMatrixOperandsAttr : 4108 SPIRV_BitEnumAttr<"CooperativeMatrixOperandsKHR", 4109 "valid SPIR-V Cooperative Matrix Operands (KHR)", 4110 "cooperative_matrix_operands_khr", [ 4111 SPIRV_KHR_CMO_None, SPIRV_KHR_CMO_MatrixA_Signed, 4112 SPIRV_KHR_CMO_MatrixB_Signed, SPIRV_KHR_CMO_MatrixC_Signed, 4113 SPIRV_KHR_CMO_Result_Signed, SPIRV_KHR_CMO_AccSat 4114 ]>; 4115 4116def SPIRV_INTEL_LCC_Uncached : I32EnumAttrCase<"Uncached", 0>; 4117def SPIRV_INTEL_LCC_Cached : I32EnumAttrCase<"Cached", 1>; 4118def SPIRV_INTEL_LCC_Streaming : I32EnumAttrCase<"Streaming", 2>; 4119def SPIRV_INTEL_LCC_InvalidateAfterRead : I32EnumAttrCase<"InvalidateAfterR", 3>; 4120def SPIRV_INTEL_LCC_ConstCached : I32EnumAttrCase<"ConstCached", 4>; 4121 4122def SPIRV_INTEL_LoadCacheControlAttr : 4123 SPIRV_I32EnumAttr<"LoadCacheControl", "valid SPIR-V LoadCacheControl", 4124 "load_cache_control", [ 4125 SPIRV_INTEL_LCC_Uncached, SPIRV_INTEL_LCC_Cached, 4126 SPIRV_INTEL_LCC_Streaming, SPIRV_INTEL_LCC_InvalidateAfterRead, 4127 SPIRV_INTEL_LCC_ConstCached 4128 ]>; 4129 4130def SPIRV_INTEL_SCC_Uncached : I32EnumAttrCase<"Uncached", 0>; 4131def SPIRV_INTEL_SCC_WriteThrough : I32EnumAttrCase<"WriteThrough", 1>; 4132def SPIRV_INTEL_SCC_WriteBack : I32EnumAttrCase<"WriteBack", 2>; 4133def SPIRV_INTEL_SCC_Streaming : I32EnumAttrCase<"Streaming", 3>; 4134 4135def SPIRV_INTEL_StoreCacheControlAttr : 4136 SPIRV_I32EnumAttr<"StoreCacheControl", "valid SPIR-V StoreCacheControl", 4137 "store_cache_control", [ 4138 SPIRV_INTEL_SCC_Uncached, SPIRV_INTEL_SCC_WriteThrough, 4139 SPIRV_INTEL_SCC_WriteBack, SPIRV_INTEL_SCC_Streaming 4140 ]>; 4141 4142//===----------------------------------------------------------------------===// 4143// SPIR-V attribute definitions 4144//===----------------------------------------------------------------------===// 4145 4146def SPIRV_VerCapExtAttr : DialectAttr< 4147 SPIRV_Dialect, 4148 CPred<"::llvm::isa<::mlir::spirv::VerCapExtAttr>($_self)">, 4149 "version-capability-extension attribute"> { 4150 let storageType = "::mlir::spirv::VerCapExtAttr"; 4151 let returnType = "::mlir::spirv::VerCapExtAttr"; 4152 let convertFromStorage = "$_self"; 4153} 4154 4155//===----------------------------------------------------------------------===// 4156// SPIR-V type definitions 4157//===----------------------------------------------------------------------===// 4158 4159class IOrUI<int width> 4160 : Type<Or<[CPred<"$_self.isSignlessInteger(" # width # ")">, 4161 CPred<"$_self.isUnsignedInteger(" # width # ")">]>, 4162 width # "-bit signless/unsigned integer"> { 4163 int bitwidth = width; 4164} 4165 4166class SignlessOrUnsignedIntOfWidths<list<int> widths> : 4167 AnyTypeOf<!foreach(w, widths, IOrUI<w>), 4168 !interleave(widths, "/") # "-bit signless/unsigned integer">; 4169 4170def SPIRV_IsArrayType : CPred<"::llvm::isa<::mlir::spirv::ArrayType>($_self)">; 4171def SPIRV_IsCooperativeMatrixType : 4172 CPred<"::llvm::isa<::mlir::spirv::CooperativeMatrixType>($_self)">; 4173def SPIRV_IsImageType : CPred<"::llvm::isa<::mlir::spirv::ImageType>($_self)">; 4174def SPIRV_IsVectorType : CPred<"::llvm::isa<::mlir::VectorType>($_self)">; 4175def SPIRV_IsMatrixType : CPred<"::llvm::isa<::mlir::spirv::MatrixType>($_self)">; 4176def SPIRV_IsPtrType : CPred<"::llvm::isa<::mlir::spirv::PointerType>($_self)">; 4177def SPIRV_IsRTArrayType : CPred<"::llvm::isa<::mlir::spirv::RuntimeArrayType>($_self)">; 4178def SPIRV_IsSampledImageType : CPred<"::llvm::isa<::mlir::spirv::SampledImageType>($_self)">; 4179def SPIRV_IsStructType : CPred<"::llvm::isa<::mlir::spirv::StructType>($_self)">; 4180 4181 4182// See https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_types 4183// for the definition of the following types and type categories. 4184 4185def SPIRV_Void : TypeAlias<NoneType, "void">; 4186def SPIRV_Bool : TypeAlias<I1, "bool">; 4187def SPIRV_Integer : AnyIntOfWidths<[8, 16, 32, 64]>; 4188def SPIRV_Int16 : TypeAlias<I16, "Int16">; 4189def SPIRV_Int32 : TypeAlias<I32, "Int32">; 4190def SPIRV_Float32 : TypeAlias<F32, "Float32">; 4191def SPIRV_Float : FloatOfWidths<[16, 32, 64]>; 4192def SPIRV_Float16or32 : FloatOfWidths<[16, 32]>; 4193def SPIRV_Vector : VectorOfLengthAndType<[2, 3, 4, 8, 16], 4194 [SPIRV_Bool, SPIRV_Integer, SPIRV_Float]>; 4195// Component type check is done in the type parser for the following SPIR-V 4196// dialect-specific types so we use "Any" here. 4197def SPIRV_AnyPtr : DialectType<SPIRV_Dialect, SPIRV_IsPtrType, 4198 "any SPIR-V pointer type">; 4199def SPIRV_AnyArray : DialectType<SPIRV_Dialect, SPIRV_IsArrayType, 4200 "any SPIR-V array type">; 4201def SPIRV_AnyCooperativeMatrix : DialectType<SPIRV_Dialect, 4202 SPIRV_IsCooperativeMatrixType, 4203 "any SPIR-V cooperative matrix type">; 4204def SPIRV_AnyImage : DialectType<SPIRV_Dialect, SPIRV_IsImageType, 4205 "any SPIR-V image type">; 4206def SPIRV_AnyVector : DialectType<SPIRV_Dialect, SPIRV_IsVectorType, 4207 "any SPIR-V vector type">; 4208def SPIRV_AnyMatrix : DialectType<SPIRV_Dialect, SPIRV_IsMatrixType, 4209 "any SPIR-V matrix type">; 4210def SPIRV_AnyRTArray : DialectType<SPIRV_Dialect, SPIRV_IsRTArrayType, 4211 "any SPIR-V runtime array type">; 4212def SPIRV_AnyStruct : DialectType<SPIRV_Dialect, SPIRV_IsStructType, 4213 "any SPIR-V struct type">; 4214def SPIRV_AnySampledImage : DialectType<SPIRV_Dialect, SPIRV_IsSampledImageType, 4215 "any SPIR-V sampled image type">; 4216 4217def SPIRV_Numerical : AnyTypeOf<[SPIRV_Integer, SPIRV_Float]>; 4218def SPIRV_Scalar : AnyTypeOf<[SPIRV_Numerical, SPIRV_Bool]>; 4219def SPIRV_Aggregate : AnyTypeOf<[SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct]>; 4220def SPIRV_Composite : 4221 AnyTypeOf<[SPIRV_Vector, SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct, 4222 SPIRV_AnyCooperativeMatrix, SPIRV_AnyMatrix]>; 4223def SPIRV_Type : AnyTypeOf<[ 4224 SPIRV_Void, SPIRV_Bool, SPIRV_Integer, SPIRV_Float, SPIRV_Vector, 4225 SPIRV_AnyPtr, SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct, 4226 SPIRV_AnyCooperativeMatrix, SPIRV_AnyMatrix, SPIRV_AnySampledImage 4227 ]>; 4228 4229def SPIRV_SignedInt : SignedIntOfWidths<[8, 16, 32, 64]>; 4230def SPIRV_SignlessOrUnsignedInt : SignlessOrUnsignedIntOfWidths<[8, 16, 32, 64]>; 4231 4232class SPIRV_CoopMatrixOfType<list<Type> allowedTypes> : 4233 ContainerType<AnyTypeOf<allowedTypes>, SPIRV_IsCooperativeMatrixType, 4234 "::llvm::cast<::mlir::spirv::CooperativeMatrixType>($_self).getElementType()", 4235 "Cooperative Matrix">; 4236 4237class SPIRV_MatrixOfType<list<Type> allowedTypes> : 4238 ContainerType<AnyTypeOf<allowedTypes>, SPIRV_IsMatrixType, 4239 "::llvm::cast<::mlir::spirv::MatrixType>($_self).getElementType()", 4240 "Matrix">; 4241 4242class SPIRV_VectorOf<Type type> : 4243 VectorOfLengthAndType<[2, 3, 4, 8, 16], [type]>; 4244 4245class SPIRV_ScalarOrVectorOf<Type type> : 4246 AnyTypeOf<[type, SPIRV_VectorOf<type>]>; 4247 4248class SPIRV_ScalarOrVectorOrCoopMatrixOf<Type type> : 4249 AnyTypeOf<[type, SPIRV_VectorOf<type>, 4250 SPIRV_CoopMatrixOfType<[type]>]>; 4251 4252class SPIRV_MatrixOrCoopMatrixOf<Type type> : 4253 AnyTypeOf<[SPIRV_AnyMatrix, 4254 SPIRV_CoopMatrixOfType<[type]>]>; 4255 4256class SPIRV_MatrixOf<Type type> : 4257 SPIRV_MatrixOfType<[type]>; 4258 4259def SPIRV_ScalarOrVector : AnyTypeOf<[SPIRV_Scalar, SPIRV_Vector]>; 4260def SPIRV_ScalarOrVectorOrPtr : AnyTypeOf<[SPIRV_ScalarOrVector, SPIRV_AnyPtr]>; 4261 4262class SPIRV_Vec4<Type type> : VectorOfLengthAndType<[4], [type]>; 4263def SPIRV_IntVec4 : SPIRV_Vec4<SPIRV_Integer>; 4264def SPIRV_IOrUIVec4 : SPIRV_Vec4<SPIRV_SignlessOrUnsignedInt>; 4265def SPIRV_Int32Vec4 : SPIRV_Vec4<AnyI32>; 4266 4267// TODO: From 1.4, this should also include Composite type. 4268def SPIRV_SelectType : AnyTypeOf<[SPIRV_Scalar, SPIRV_Vector, SPIRV_AnyPtr]>; 4269 4270//===----------------------------------------------------------------------===// 4271// SPIR-V OpTrait definitions 4272//===----------------------------------------------------------------------===// 4273 4274// Check that an op can only be used within the scope of a function-like op. 4275def InFunctionScope : PredOpTrait< 4276 "op must appear in a function-like op's block", 4277 CPred<"isNestedInFunctionOpInterface($_op.getParentOp())">>; 4278 4279// Check that an op can only be used within the scope of a module-like op. 4280def InModuleScope : PredOpTrait< 4281 "op must appear in a module-like op's block", 4282 CPred<"isDirectInModuleLikeOp($_op.getParentOp())">>; 4283 4284def UnsignedOp : NativeOpTrait<"spirv::UnsignedOp">; 4285 4286def SignedOp : NativeOpTrait<"spirv::SignedOp">; 4287 4288def UsableInSpecConstantOp : NativeOpTrait<"spirv::UsableInSpecConstantOp">; 4289 4290//===----------------------------------------------------------------------===// 4291// SPIR-V opcode specification 4292//===----------------------------------------------------------------------===// 4293 4294class SPIRV_OpCode<string name, int val> { 4295 // Name used as reference to retrieve the opcode 4296 string opname = name; 4297 4298 // Opcode associated with the name 4299 int opcode = val; 4300} 4301 4302// Begin opcode section. Generated from SPIR-V spec; DO NOT MODIFY! 4303 4304def SPIRV_OC_OpNop : I32EnumAttrCase<"OpNop", 0>; 4305def SPIRV_OC_OpUndef : I32EnumAttrCase<"OpUndef", 1>; 4306def SPIRV_OC_OpSourceContinued : I32EnumAttrCase<"OpSourceContinued", 2>; 4307def SPIRV_OC_OpSource : I32EnumAttrCase<"OpSource", 3>; 4308def SPIRV_OC_OpSourceExtension : I32EnumAttrCase<"OpSourceExtension", 4>; 4309def SPIRV_OC_OpName : I32EnumAttrCase<"OpName", 5>; 4310def SPIRV_OC_OpMemberName : I32EnumAttrCase<"OpMemberName", 6>; 4311def SPIRV_OC_OpString : I32EnumAttrCase<"OpString", 7>; 4312def SPIRV_OC_OpLine : I32EnumAttrCase<"OpLine", 8>; 4313def SPIRV_OC_OpExtension : I32EnumAttrCase<"OpExtension", 10>; 4314def SPIRV_OC_OpExtInstImport : I32EnumAttrCase<"OpExtInstImport", 11>; 4315def SPIRV_OC_OpExtInst : I32EnumAttrCase<"OpExtInst", 12>; 4316def SPIRV_OC_OpMemoryModel : I32EnumAttrCase<"OpMemoryModel", 14>; 4317def SPIRV_OC_OpEntryPoint : I32EnumAttrCase<"OpEntryPoint", 15>; 4318def SPIRV_OC_OpExecutionMode : I32EnumAttrCase<"OpExecutionMode", 16>; 4319def SPIRV_OC_OpCapability : I32EnumAttrCase<"OpCapability", 17>; 4320def SPIRV_OC_OpTypeVoid : I32EnumAttrCase<"OpTypeVoid", 19>; 4321def SPIRV_OC_OpTypeBool : I32EnumAttrCase<"OpTypeBool", 20>; 4322def SPIRV_OC_OpTypeInt : I32EnumAttrCase<"OpTypeInt", 21>; 4323def SPIRV_OC_OpTypeFloat : I32EnumAttrCase<"OpTypeFloat", 22>; 4324def SPIRV_OC_OpTypeVector : I32EnumAttrCase<"OpTypeVector", 23>; 4325def SPIRV_OC_OpTypeMatrix : I32EnumAttrCase<"OpTypeMatrix", 24>; 4326def SPIRV_OC_OpTypeImage : I32EnumAttrCase<"OpTypeImage", 25>; 4327def SPIRV_OC_OpTypeSampledImage : I32EnumAttrCase<"OpTypeSampledImage", 27>; 4328def SPIRV_OC_OpTypeArray : I32EnumAttrCase<"OpTypeArray", 28>; 4329def SPIRV_OC_OpTypeRuntimeArray : I32EnumAttrCase<"OpTypeRuntimeArray", 29>; 4330def SPIRV_OC_OpTypeStruct : I32EnumAttrCase<"OpTypeStruct", 30>; 4331def SPIRV_OC_OpTypePointer : I32EnumAttrCase<"OpTypePointer", 32>; 4332def SPIRV_OC_OpTypeFunction : I32EnumAttrCase<"OpTypeFunction", 33>; 4333def SPIRV_OC_OpTypeForwardPointer : I32EnumAttrCase<"OpTypeForwardPointer", 39>; 4334def SPIRV_OC_OpConstantTrue : I32EnumAttrCase<"OpConstantTrue", 41>; 4335def SPIRV_OC_OpConstantFalse : I32EnumAttrCase<"OpConstantFalse", 42>; 4336def SPIRV_OC_OpConstant : I32EnumAttrCase<"OpConstant", 43>; 4337def SPIRV_OC_OpConstantComposite : I32EnumAttrCase<"OpConstantComposite", 44>; 4338def SPIRV_OC_OpConstantNull : I32EnumAttrCase<"OpConstantNull", 46>; 4339def SPIRV_OC_OpSpecConstantTrue : I32EnumAttrCase<"OpSpecConstantTrue", 48>; 4340def SPIRV_OC_OpSpecConstantFalse : I32EnumAttrCase<"OpSpecConstantFalse", 49>; 4341def SPIRV_OC_OpSpecConstant : I32EnumAttrCase<"OpSpecConstant", 50>; 4342def SPIRV_OC_OpSpecConstantComposite : I32EnumAttrCase<"OpSpecConstantComposite", 51>; 4343def SPIRV_OC_OpSpecConstantOp : I32EnumAttrCase<"OpSpecConstantOp", 52>; 4344def SPIRV_OC_OpFunction : I32EnumAttrCase<"OpFunction", 54>; 4345def SPIRV_OC_OpFunctionParameter : I32EnumAttrCase<"OpFunctionParameter", 55>; 4346def SPIRV_OC_OpFunctionEnd : I32EnumAttrCase<"OpFunctionEnd", 56>; 4347def SPIRV_OC_OpFunctionCall : I32EnumAttrCase<"OpFunctionCall", 57>; 4348def SPIRV_OC_OpVariable : I32EnumAttrCase<"OpVariable", 59>; 4349def SPIRV_OC_OpLoad : I32EnumAttrCase<"OpLoad", 61>; 4350def SPIRV_OC_OpStore : I32EnumAttrCase<"OpStore", 62>; 4351def SPIRV_OC_OpCopyMemory : I32EnumAttrCase<"OpCopyMemory", 63>; 4352def SPIRV_OC_OpAccessChain : I32EnumAttrCase<"OpAccessChain", 65>; 4353def SPIRV_OC_OpPtrAccessChain : I32EnumAttrCase<"OpPtrAccessChain", 67>; 4354def SPIRV_OC_OpInBoundsPtrAccessChain : I32EnumAttrCase<"OpInBoundsPtrAccessChain", 70>; 4355def SPIRV_OC_OpDecorate : I32EnumAttrCase<"OpDecorate", 71>; 4356def SPIRV_OC_OpMemberDecorate : I32EnumAttrCase<"OpMemberDecorate", 72>; 4357def SPIRV_OC_OpVectorExtractDynamic : I32EnumAttrCase<"OpVectorExtractDynamic", 77>; 4358def SPIRV_OC_OpVectorInsertDynamic : I32EnumAttrCase<"OpVectorInsertDynamic", 78>; 4359def SPIRV_OC_OpVectorShuffle : I32EnumAttrCase<"OpVectorShuffle", 79>; 4360def SPIRV_OC_OpCompositeConstruct : I32EnumAttrCase<"OpCompositeConstruct", 80>; 4361def SPIRV_OC_OpCompositeExtract : I32EnumAttrCase<"OpCompositeExtract", 81>; 4362def SPIRV_OC_OpCompositeInsert : I32EnumAttrCase<"OpCompositeInsert", 82>; 4363def SPIRV_OC_OpTranspose : I32EnumAttrCase<"OpTranspose", 84>; 4364def SPIRV_OC_OpImageDrefGather : I32EnumAttrCase<"OpImageDrefGather", 97>; 4365def SPIRV_OC_OpImage : I32EnumAttrCase<"OpImage", 100>; 4366def SPIRV_OC_OpImageQuerySize : I32EnumAttrCase<"OpImageQuerySize", 104>; 4367def SPIRV_OC_OpConvertFToU : I32EnumAttrCase<"OpConvertFToU", 109>; 4368def SPIRV_OC_OpConvertFToS : I32EnumAttrCase<"OpConvertFToS", 110>; 4369def SPIRV_OC_OpConvertSToF : I32EnumAttrCase<"OpConvertSToF", 111>; 4370def SPIRV_OC_OpConvertUToF : I32EnumAttrCase<"OpConvertUToF", 112>; 4371def SPIRV_OC_OpUConvert : I32EnumAttrCase<"OpUConvert", 113>; 4372def SPIRV_OC_OpSConvert : I32EnumAttrCase<"OpSConvert", 114>; 4373def SPIRV_OC_OpFConvert : I32EnumAttrCase<"OpFConvert", 115>; 4374def SPIRV_OC_OpConvertPtrToU : I32EnumAttrCase<"OpConvertPtrToU", 117>; 4375def SPIRV_OC_OpConvertUToPtr : I32EnumAttrCase<"OpConvertUToPtr", 120>; 4376def SPIRV_OC_OpPtrCastToGeneric : I32EnumAttrCase<"OpPtrCastToGeneric", 121>; 4377def SPIRV_OC_OpGenericCastToPtr : I32EnumAttrCase<"OpGenericCastToPtr", 122>; 4378def SPIRV_OC_OpGenericCastToPtrExplicit : I32EnumAttrCase<"OpGenericCastToPtrExplicit", 123>; 4379def SPIRV_OC_OpBitcast : I32EnumAttrCase<"OpBitcast", 124>; 4380def SPIRV_OC_OpSNegate : I32EnumAttrCase<"OpSNegate", 126>; 4381def SPIRV_OC_OpFNegate : I32EnumAttrCase<"OpFNegate", 127>; 4382def SPIRV_OC_OpIAdd : I32EnumAttrCase<"OpIAdd", 128>; 4383def SPIRV_OC_OpFAdd : I32EnumAttrCase<"OpFAdd", 129>; 4384def SPIRV_OC_OpISub : I32EnumAttrCase<"OpISub", 130>; 4385def SPIRV_OC_OpFSub : I32EnumAttrCase<"OpFSub", 131>; 4386def SPIRV_OC_OpIMul : I32EnumAttrCase<"OpIMul", 132>; 4387def SPIRV_OC_OpFMul : I32EnumAttrCase<"OpFMul", 133>; 4388def SPIRV_OC_OpUDiv : I32EnumAttrCase<"OpUDiv", 134>; 4389def SPIRV_OC_OpSDiv : I32EnumAttrCase<"OpSDiv", 135>; 4390def SPIRV_OC_OpFDiv : I32EnumAttrCase<"OpFDiv", 136>; 4391def SPIRV_OC_OpUMod : I32EnumAttrCase<"OpUMod", 137>; 4392def SPIRV_OC_OpSRem : I32EnumAttrCase<"OpSRem", 138>; 4393def SPIRV_OC_OpSMod : I32EnumAttrCase<"OpSMod", 139>; 4394def SPIRV_OC_OpFRem : I32EnumAttrCase<"OpFRem", 140>; 4395def SPIRV_OC_OpFMod : I32EnumAttrCase<"OpFMod", 141>; 4396def SPIRV_OC_OpVectorTimesScalar : I32EnumAttrCase<"OpVectorTimesScalar", 142>; 4397def SPIRV_OC_OpMatrixTimesScalar : I32EnumAttrCase<"OpMatrixTimesScalar", 143>; 4398def SPIRV_OC_OpVectorTimesMatrix : I32EnumAttrCase<"OpVectorTimesMatrix", 144>; 4399def SPIRV_OC_OpMatrixTimesVector : I32EnumAttrCase<"OpMatrixTimesVector", 145>; 4400def SPIRV_OC_OpMatrixTimesMatrix : I32EnumAttrCase<"OpMatrixTimesMatrix", 146>; 4401def SPIRV_OC_OpDot : I32EnumAttrCase<"OpDot", 148>; 4402def SPIRV_OC_OpIAddCarry : I32EnumAttrCase<"OpIAddCarry", 149>; 4403def SPIRV_OC_OpISubBorrow : I32EnumAttrCase<"OpISubBorrow", 150>; 4404def SPIRV_OC_OpUMulExtended : I32EnumAttrCase<"OpUMulExtended", 151>; 4405def SPIRV_OC_OpSMulExtended : I32EnumAttrCase<"OpSMulExtended", 152>; 4406def SPIRV_OC_OpIsNan : I32EnumAttrCase<"OpIsNan", 156>; 4407def SPIRV_OC_OpIsInf : I32EnumAttrCase<"OpIsInf", 157>; 4408def SPIRV_OC_OpOrdered : I32EnumAttrCase<"OpOrdered", 162>; 4409def SPIRV_OC_OpUnordered : I32EnumAttrCase<"OpUnordered", 163>; 4410def SPIRV_OC_OpLogicalEqual : I32EnumAttrCase<"OpLogicalEqual", 164>; 4411def SPIRV_OC_OpLogicalNotEqual : I32EnumAttrCase<"OpLogicalNotEqual", 165>; 4412def SPIRV_OC_OpLogicalOr : I32EnumAttrCase<"OpLogicalOr", 166>; 4413def SPIRV_OC_OpLogicalAnd : I32EnumAttrCase<"OpLogicalAnd", 167>; 4414def SPIRV_OC_OpLogicalNot : I32EnumAttrCase<"OpLogicalNot", 168>; 4415def SPIRV_OC_OpSelect : I32EnumAttrCase<"OpSelect", 169>; 4416def SPIRV_OC_OpIEqual : I32EnumAttrCase<"OpIEqual", 170>; 4417def SPIRV_OC_OpINotEqual : I32EnumAttrCase<"OpINotEqual", 171>; 4418def SPIRV_OC_OpUGreaterThan : I32EnumAttrCase<"OpUGreaterThan", 172>; 4419def SPIRV_OC_OpSGreaterThan : I32EnumAttrCase<"OpSGreaterThan", 173>; 4420def SPIRV_OC_OpUGreaterThanEqual : I32EnumAttrCase<"OpUGreaterThanEqual", 174>; 4421def SPIRV_OC_OpSGreaterThanEqual : I32EnumAttrCase<"OpSGreaterThanEqual", 175>; 4422def SPIRV_OC_OpULessThan : I32EnumAttrCase<"OpULessThan", 176>; 4423def SPIRV_OC_OpSLessThan : I32EnumAttrCase<"OpSLessThan", 177>; 4424def SPIRV_OC_OpULessThanEqual : I32EnumAttrCase<"OpULessThanEqual", 178>; 4425def SPIRV_OC_OpSLessThanEqual : I32EnumAttrCase<"OpSLessThanEqual", 179>; 4426def SPIRV_OC_OpFOrdEqual : I32EnumAttrCase<"OpFOrdEqual", 180>; 4427def SPIRV_OC_OpFUnordEqual : I32EnumAttrCase<"OpFUnordEqual", 181>; 4428def SPIRV_OC_OpFOrdNotEqual : I32EnumAttrCase<"OpFOrdNotEqual", 182>; 4429def SPIRV_OC_OpFUnordNotEqual : I32EnumAttrCase<"OpFUnordNotEqual", 183>; 4430def SPIRV_OC_OpFOrdLessThan : I32EnumAttrCase<"OpFOrdLessThan", 184>; 4431def SPIRV_OC_OpFUnordLessThan : I32EnumAttrCase<"OpFUnordLessThan", 185>; 4432def SPIRV_OC_OpFOrdGreaterThan : I32EnumAttrCase<"OpFOrdGreaterThan", 186>; 4433def SPIRV_OC_OpFUnordGreaterThan : I32EnumAttrCase<"OpFUnordGreaterThan", 187>; 4434def SPIRV_OC_OpFOrdLessThanEqual : I32EnumAttrCase<"OpFOrdLessThanEqual", 188>; 4435def SPIRV_OC_OpFUnordLessThanEqual : I32EnumAttrCase<"OpFUnordLessThanEqual", 189>; 4436def SPIRV_OC_OpFOrdGreaterThanEqual : I32EnumAttrCase<"OpFOrdGreaterThanEqual", 190>; 4437def SPIRV_OC_OpFUnordGreaterThanEqual : I32EnumAttrCase<"OpFUnordGreaterThanEqual", 191>; 4438def SPIRV_OC_OpShiftRightLogical : I32EnumAttrCase<"OpShiftRightLogical", 194>; 4439def SPIRV_OC_OpShiftRightArithmetic : I32EnumAttrCase<"OpShiftRightArithmetic", 195>; 4440def SPIRV_OC_OpShiftLeftLogical : I32EnumAttrCase<"OpShiftLeftLogical", 196>; 4441def SPIRV_OC_OpBitwiseOr : I32EnumAttrCase<"OpBitwiseOr", 197>; 4442def SPIRV_OC_OpBitwiseXor : I32EnumAttrCase<"OpBitwiseXor", 198>; 4443def SPIRV_OC_OpBitwiseAnd : I32EnumAttrCase<"OpBitwiseAnd", 199>; 4444def SPIRV_OC_OpNot : I32EnumAttrCase<"OpNot", 200>; 4445def SPIRV_OC_OpBitFieldInsert : I32EnumAttrCase<"OpBitFieldInsert", 201>; 4446def SPIRV_OC_OpBitFieldSExtract : I32EnumAttrCase<"OpBitFieldSExtract", 202>; 4447def SPIRV_OC_OpBitFieldUExtract : I32EnumAttrCase<"OpBitFieldUExtract", 203>; 4448def SPIRV_OC_OpBitReverse : I32EnumAttrCase<"OpBitReverse", 204>; 4449def SPIRV_OC_OpBitCount : I32EnumAttrCase<"OpBitCount", 205>; 4450def SPIRV_OC_OpEmitVertex : I32EnumAttrCase<"OpEmitVertex", 218>; 4451def SPIRV_OC_OpEndPrimitive : I32EnumAttrCase<"OpEndPrimitive", 219>; 4452def SPIRV_OC_OpControlBarrier : I32EnumAttrCase<"OpControlBarrier", 224>; 4453def SPIRV_OC_OpMemoryBarrier : I32EnumAttrCase<"OpMemoryBarrier", 225>; 4454def SPIRV_OC_OpAtomicExchange : I32EnumAttrCase<"OpAtomicExchange", 229>; 4455def SPIRV_OC_OpAtomicCompareExchange : I32EnumAttrCase<"OpAtomicCompareExchange", 230>; 4456def SPIRV_OC_OpAtomicCompareExchangeWeak : I32EnumAttrCase<"OpAtomicCompareExchangeWeak", 231>; 4457def SPIRV_OC_OpAtomicIIncrement : I32EnumAttrCase<"OpAtomicIIncrement", 232>; 4458def SPIRV_OC_OpAtomicIDecrement : I32EnumAttrCase<"OpAtomicIDecrement", 233>; 4459def SPIRV_OC_OpAtomicIAdd : I32EnumAttrCase<"OpAtomicIAdd", 234>; 4460def SPIRV_OC_OpAtomicISub : I32EnumAttrCase<"OpAtomicISub", 235>; 4461def SPIRV_OC_OpAtomicSMin : I32EnumAttrCase<"OpAtomicSMin", 236>; 4462def SPIRV_OC_OpAtomicUMin : I32EnumAttrCase<"OpAtomicUMin", 237>; 4463def SPIRV_OC_OpAtomicSMax : I32EnumAttrCase<"OpAtomicSMax", 238>; 4464def SPIRV_OC_OpAtomicUMax : I32EnumAttrCase<"OpAtomicUMax", 239>; 4465def SPIRV_OC_OpAtomicAnd : I32EnumAttrCase<"OpAtomicAnd", 240>; 4466def SPIRV_OC_OpAtomicOr : I32EnumAttrCase<"OpAtomicOr", 241>; 4467def SPIRV_OC_OpAtomicXor : I32EnumAttrCase<"OpAtomicXor", 242>; 4468def SPIRV_OC_OpPhi : I32EnumAttrCase<"OpPhi", 245>; 4469def SPIRV_OC_OpLoopMerge : I32EnumAttrCase<"OpLoopMerge", 246>; 4470def SPIRV_OC_OpSelectionMerge : I32EnumAttrCase<"OpSelectionMerge", 247>; 4471def SPIRV_OC_OpLabel : I32EnumAttrCase<"OpLabel", 248>; 4472def SPIRV_OC_OpBranch : I32EnumAttrCase<"OpBranch", 249>; 4473def SPIRV_OC_OpBranchConditional : I32EnumAttrCase<"OpBranchConditional", 250>; 4474def SPIRV_OC_OpReturn : I32EnumAttrCase<"OpReturn", 253>; 4475def SPIRV_OC_OpReturnValue : I32EnumAttrCase<"OpReturnValue", 254>; 4476def SPIRV_OC_OpUnreachable : I32EnumAttrCase<"OpUnreachable", 255>; 4477def SPIRV_OC_OpGroupBroadcast : I32EnumAttrCase<"OpGroupBroadcast", 263>; 4478def SPIRV_OC_OpGroupIAdd : I32EnumAttrCase<"OpGroupIAdd", 264>; 4479def SPIRV_OC_OpGroupFAdd : I32EnumAttrCase<"OpGroupFAdd", 265>; 4480def SPIRV_OC_OpGroupFMin : I32EnumAttrCase<"OpGroupFMin", 266>; 4481def SPIRV_OC_OpGroupUMin : I32EnumAttrCase<"OpGroupUMin", 267>; 4482def SPIRV_OC_OpGroupSMin : I32EnumAttrCase<"OpGroupSMin", 268>; 4483def SPIRV_OC_OpGroupFMax : I32EnumAttrCase<"OpGroupFMax", 269>; 4484def SPIRV_OC_OpGroupUMax : I32EnumAttrCase<"OpGroupUMax", 270>; 4485def SPIRV_OC_OpGroupSMax : I32EnumAttrCase<"OpGroupSMax", 271>; 4486def SPIRV_OC_OpNoLine : I32EnumAttrCase<"OpNoLine", 317>; 4487def SPIRV_OC_OpModuleProcessed : I32EnumAttrCase<"OpModuleProcessed", 330>; 4488def SPIRV_OC_OpGroupNonUniformElect : I32EnumAttrCase<"OpGroupNonUniformElect", 333>; 4489def SPIRV_OC_OpGroupNonUniformBroadcast : I32EnumAttrCase<"OpGroupNonUniformBroadcast", 337>; 4490def SPIRV_OC_OpGroupNonUniformBallot : I32EnumAttrCase<"OpGroupNonUniformBallot", 339>; 4491def SPIRV_OC_OpGroupNonUniformBallotFindLSB : I32EnumAttrCase<"OpGroupNonUniformBallotFindLSB", 343>; 4492def SPIRV_OC_OpGroupNonUniformBallotFindMSB : I32EnumAttrCase<"OpGroupNonUniformBallotFindMSB", 344>; 4493def SPIRV_OC_OpGroupNonUniformShuffle : I32EnumAttrCase<"OpGroupNonUniformShuffle", 345>; 4494def SPIRV_OC_OpGroupNonUniformShuffleXor : I32EnumAttrCase<"OpGroupNonUniformShuffleXor", 346>; 4495def SPIRV_OC_OpGroupNonUniformShuffleUp : I32EnumAttrCase<"OpGroupNonUniformShuffleUp", 347>; 4496def SPIRV_OC_OpGroupNonUniformShuffleDown : I32EnumAttrCase<"OpGroupNonUniformShuffleDown", 348>; 4497def SPIRV_OC_OpGroupNonUniformIAdd : I32EnumAttrCase<"OpGroupNonUniformIAdd", 349>; 4498def SPIRV_OC_OpGroupNonUniformFAdd : I32EnumAttrCase<"OpGroupNonUniformFAdd", 350>; 4499def SPIRV_OC_OpGroupNonUniformIMul : I32EnumAttrCase<"OpGroupNonUniformIMul", 351>; 4500def SPIRV_OC_OpGroupNonUniformFMul : I32EnumAttrCase<"OpGroupNonUniformFMul", 352>; 4501def SPIRV_OC_OpGroupNonUniformSMin : I32EnumAttrCase<"OpGroupNonUniformSMin", 353>; 4502def SPIRV_OC_OpGroupNonUniformUMin : I32EnumAttrCase<"OpGroupNonUniformUMin", 354>; 4503def SPIRV_OC_OpGroupNonUniformFMin : I32EnumAttrCase<"OpGroupNonUniformFMin", 355>; 4504def SPIRV_OC_OpGroupNonUniformSMax : I32EnumAttrCase<"OpGroupNonUniformSMax", 356>; 4505def SPIRV_OC_OpGroupNonUniformUMax : I32EnumAttrCase<"OpGroupNonUniformUMax", 357>; 4506def SPIRV_OC_OpGroupNonUniformFMax : I32EnumAttrCase<"OpGroupNonUniformFMax", 358>; 4507def SPIRV_OC_OpGroupNonUniformBitwiseAnd : I32EnumAttrCase<"OpGroupNonUniformBitwiseAnd", 359>; 4508def SPIRV_OC_OpGroupNonUniformBitwiseOr : I32EnumAttrCase<"OpGroupNonUniformBitwiseOr", 360>; 4509def SPIRV_OC_OpGroupNonUniformBitwiseXor : I32EnumAttrCase<"OpGroupNonUniformBitwiseXor", 361>; 4510def SPIRV_OC_OpGroupNonUniformLogicalAnd : I32EnumAttrCase<"OpGroupNonUniformLogicalAnd", 362>; 4511def SPIRV_OC_OpGroupNonUniformLogicalOr : I32EnumAttrCase<"OpGroupNonUniformLogicalOr", 363>; 4512def SPIRV_OC_OpGroupNonUniformLogicalXor : I32EnumAttrCase<"OpGroupNonUniformLogicalXor", 364>; 4513def SPIRV_OC_OpSubgroupBallotKHR : I32EnumAttrCase<"OpSubgroupBallotKHR", 4421>; 4514def SPIRV_OC_OpSDot : I32EnumAttrCase<"OpSDot", 4450>; 4515def SPIRV_OC_OpUDot : I32EnumAttrCase<"OpUDot", 4451>; 4516def SPIRV_OC_OpSUDot : I32EnumAttrCase<"OpSUDot", 4452>; 4517def SPIRV_OC_OpSDotAccSat : I32EnumAttrCase<"OpSDotAccSat", 4453>; 4518def SPIRV_OC_OpUDotAccSat : I32EnumAttrCase<"OpUDotAccSat", 4454>; 4519def SPIRV_OC_OpSUDotAccSat : I32EnumAttrCase<"OpSUDotAccSat", 4455>; 4520def SPIRV_OC_OpTypeCooperativeMatrixKHR : I32EnumAttrCase<"OpTypeCooperativeMatrixKHR", 4456>; 4521def SPIRV_OC_OpCooperativeMatrixLoadKHR : I32EnumAttrCase<"OpCooperativeMatrixLoadKHR", 4457>; 4522def SPIRV_OC_OpCooperativeMatrixStoreKHR : I32EnumAttrCase<"OpCooperativeMatrixStoreKHR", 4458>; 4523def SPIRV_OC_OpCooperativeMatrixMulAddKHR : I32EnumAttrCase<"OpCooperativeMatrixMulAddKHR", 4459>; 4524def SPIRV_OC_OpCooperativeMatrixLengthKHR : I32EnumAttrCase<"OpCooperativeMatrixLengthKHR", 4460>; 4525def SPIRV_OC_OpSubgroupBlockReadINTEL : I32EnumAttrCase<"OpSubgroupBlockReadINTEL", 5575>; 4526def SPIRV_OC_OpSubgroupBlockWriteINTEL : I32EnumAttrCase<"OpSubgroupBlockWriteINTEL", 5576>; 4527def SPIRV_OC_OpAssumeTrueKHR : I32EnumAttrCase<"OpAssumeTrueKHR", 5630>; 4528def SPIRV_OC_OpAtomicFAddEXT : I32EnumAttrCase<"OpAtomicFAddEXT", 6035>; 4529def SPIRV_OC_OpConvertFToBF16INTEL : I32EnumAttrCase<"OpConvertFToBF16INTEL", 6116>; 4530def SPIRV_OC_OpConvertBF16ToFINTEL : I32EnumAttrCase<"OpConvertBF16ToFINTEL", 6117>; 4531def SPIRV_OC_OpControlBarrierArriveINTEL : I32EnumAttrCase<"OpControlBarrierArriveINTEL", 6142>; 4532def SPIRV_OC_OpControlBarrierWaitINTEL : I32EnumAttrCase<"OpControlBarrierWaitINTEL", 6143>; 4533def SPIRV_OC_OpGroupIMulKHR : I32EnumAttrCase<"OpGroupIMulKHR", 6401>; 4534def SPIRV_OC_OpGroupFMulKHR : I32EnumAttrCase<"OpGroupFMulKHR", 6402>; 4535 4536def SPIRV_OpcodeAttr : 4537 SPIRV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", "opcode", [ 4538 SPIRV_OC_OpNop, SPIRV_OC_OpUndef, SPIRV_OC_OpSourceContinued, 4539 SPIRV_OC_OpSource, SPIRV_OC_OpSourceExtension, SPIRV_OC_OpName, 4540 SPIRV_OC_OpMemberName, SPIRV_OC_OpString, SPIRV_OC_OpLine, 4541 SPIRV_OC_OpExtension, SPIRV_OC_OpExtInstImport, SPIRV_OC_OpExtInst, 4542 SPIRV_OC_OpMemoryModel, SPIRV_OC_OpEntryPoint, SPIRV_OC_OpExecutionMode, 4543 SPIRV_OC_OpCapability, SPIRV_OC_OpTypeVoid, SPIRV_OC_OpTypeBool, 4544 SPIRV_OC_OpTypeInt, SPIRV_OC_OpTypeFloat, SPIRV_OC_OpTypeVector, 4545 SPIRV_OC_OpTypeMatrix, SPIRV_OC_OpTypeImage, SPIRV_OC_OpTypeSampledImage, 4546 SPIRV_OC_OpTypeArray, SPIRV_OC_OpTypeRuntimeArray, SPIRV_OC_OpTypeStruct, 4547 SPIRV_OC_OpTypePointer, SPIRV_OC_OpTypeFunction, SPIRV_OC_OpTypeForwardPointer, 4548 SPIRV_OC_OpConstantTrue, SPIRV_OC_OpConstantFalse, SPIRV_OC_OpConstant, 4549 SPIRV_OC_OpConstantComposite, SPIRV_OC_OpConstantNull, 4550 SPIRV_OC_OpSpecConstantTrue, SPIRV_OC_OpSpecConstantFalse, 4551 SPIRV_OC_OpSpecConstant, SPIRV_OC_OpSpecConstantComposite, 4552 SPIRV_OC_OpSpecConstantOp, SPIRV_OC_OpFunction, SPIRV_OC_OpFunctionParameter, 4553 SPIRV_OC_OpFunctionEnd, SPIRV_OC_OpFunctionCall, SPIRV_OC_OpVariable, 4554 SPIRV_OC_OpLoad, SPIRV_OC_OpStore, SPIRV_OC_OpCopyMemory, 4555 SPIRV_OC_OpAccessChain, SPIRV_OC_OpPtrAccessChain, 4556 SPIRV_OC_OpInBoundsPtrAccessChain, SPIRV_OC_OpDecorate, 4557 SPIRV_OC_OpMemberDecorate, SPIRV_OC_OpVectorExtractDynamic, 4558 SPIRV_OC_OpVectorInsertDynamic, SPIRV_OC_OpVectorShuffle, 4559 SPIRV_OC_OpCompositeConstruct, SPIRV_OC_OpCompositeExtract, 4560 SPIRV_OC_OpCompositeInsert, SPIRV_OC_OpTranspose, SPIRV_OC_OpImageDrefGather, 4561 SPIRV_OC_OpImage, SPIRV_OC_OpImageQuerySize, SPIRV_OC_OpConvertFToU, 4562 SPIRV_OC_OpConvertFToS, SPIRV_OC_OpConvertSToF, SPIRV_OC_OpConvertUToF, 4563 SPIRV_OC_OpUConvert, SPIRV_OC_OpSConvert, SPIRV_OC_OpFConvert, 4564 SPIRV_OC_OpConvertPtrToU, SPIRV_OC_OpConvertUToPtr, 4565 SPIRV_OC_OpPtrCastToGeneric, SPIRV_OC_OpGenericCastToPtr, 4566 SPIRV_OC_OpGenericCastToPtrExplicit, SPIRV_OC_OpBitcast, SPIRV_OC_OpSNegate, 4567 SPIRV_OC_OpFNegate, SPIRV_OC_OpIAdd, SPIRV_OC_OpFAdd, SPIRV_OC_OpISub, 4568 SPIRV_OC_OpFSub, SPIRV_OC_OpIMul, SPIRV_OC_OpFMul, SPIRV_OC_OpUDiv, 4569 SPIRV_OC_OpSDiv, SPIRV_OC_OpFDiv, SPIRV_OC_OpUMod, SPIRV_OC_OpSRem, 4570 SPIRV_OC_OpSMod, SPIRV_OC_OpFRem, SPIRV_OC_OpFMod, 4571 SPIRV_OC_OpVectorTimesScalar, SPIRV_OC_OpMatrixTimesScalar, 4572 SPIRV_OC_OpVectorTimesMatrix, SPIRV_OC_OpMatrixTimesVector, 4573 SPIRV_OC_OpMatrixTimesMatrix, SPIRV_OC_OpDot, SPIRV_OC_OpIAddCarry, 4574 SPIRV_OC_OpISubBorrow, SPIRV_OC_OpUMulExtended, SPIRV_OC_OpSMulExtended, 4575 SPIRV_OC_OpIsNan, SPIRV_OC_OpIsInf, SPIRV_OC_OpOrdered, SPIRV_OC_OpUnordered, 4576 SPIRV_OC_OpLogicalEqual, SPIRV_OC_OpLogicalNotEqual, SPIRV_OC_OpLogicalOr, 4577 SPIRV_OC_OpLogicalAnd, SPIRV_OC_OpLogicalNot, SPIRV_OC_OpSelect, 4578 SPIRV_OC_OpIEqual, SPIRV_OC_OpINotEqual, SPIRV_OC_OpUGreaterThan, 4579 SPIRV_OC_OpSGreaterThan, SPIRV_OC_OpUGreaterThanEqual, 4580 SPIRV_OC_OpSGreaterThanEqual, SPIRV_OC_OpULessThan, SPIRV_OC_OpSLessThan, 4581 SPIRV_OC_OpULessThanEqual, SPIRV_OC_OpSLessThanEqual, SPIRV_OC_OpFOrdEqual, 4582 SPIRV_OC_OpFUnordEqual, SPIRV_OC_OpFOrdNotEqual, SPIRV_OC_OpFUnordNotEqual, 4583 SPIRV_OC_OpFOrdLessThan, SPIRV_OC_OpFUnordLessThan, SPIRV_OC_OpFOrdGreaterThan, 4584 SPIRV_OC_OpFUnordGreaterThan, SPIRV_OC_OpFOrdLessThanEqual, 4585 SPIRV_OC_OpFUnordLessThanEqual, SPIRV_OC_OpFOrdGreaterThanEqual, 4586 SPIRV_OC_OpFUnordGreaterThanEqual, SPIRV_OC_OpShiftRightLogical, 4587 SPIRV_OC_OpShiftRightArithmetic, SPIRV_OC_OpShiftLeftLogical, 4588 SPIRV_OC_OpBitwiseOr, SPIRV_OC_OpBitwiseXor, SPIRV_OC_OpBitwiseAnd, 4589 SPIRV_OC_OpNot, SPIRV_OC_OpBitFieldInsert, SPIRV_OC_OpBitFieldSExtract, 4590 SPIRV_OC_OpBitFieldUExtract, SPIRV_OC_OpBitReverse, SPIRV_OC_OpBitCount, 4591 SPIRV_OC_OpEmitVertex, SPIRV_OC_OpEndPrimitive, SPIRV_OC_OpControlBarrier, 4592 SPIRV_OC_OpMemoryBarrier, SPIRV_OC_OpAtomicExchange, 4593 SPIRV_OC_OpAtomicCompareExchange, SPIRV_OC_OpAtomicCompareExchangeWeak, 4594 SPIRV_OC_OpAtomicIIncrement, SPIRV_OC_OpAtomicIDecrement, 4595 SPIRV_OC_OpAtomicIAdd, SPIRV_OC_OpAtomicISub, SPIRV_OC_OpAtomicSMin, 4596 SPIRV_OC_OpAtomicUMin, SPIRV_OC_OpAtomicSMax, SPIRV_OC_OpAtomicUMax, 4597 SPIRV_OC_OpAtomicAnd, SPIRV_OC_OpAtomicOr, SPIRV_OC_OpAtomicXor, 4598 SPIRV_OC_OpPhi, SPIRV_OC_OpLoopMerge, SPIRV_OC_OpSelectionMerge, 4599 SPIRV_OC_OpLabel, SPIRV_OC_OpBranch, SPIRV_OC_OpBranchConditional, 4600 SPIRV_OC_OpReturn, SPIRV_OC_OpReturnValue, SPIRV_OC_OpUnreachable, 4601 SPIRV_OC_OpGroupBroadcast, SPIRV_OC_OpGroupIAdd, SPIRV_OC_OpGroupFAdd, 4602 SPIRV_OC_OpGroupFMin, SPIRV_OC_OpGroupUMin, SPIRV_OC_OpGroupSMin, 4603 SPIRV_OC_OpGroupFMax, SPIRV_OC_OpGroupUMax, SPIRV_OC_OpGroupSMax, 4604 SPIRV_OC_OpNoLine, SPIRV_OC_OpModuleProcessed, SPIRV_OC_OpGroupNonUniformElect, 4605 SPIRV_OC_OpGroupNonUniformBroadcast, SPIRV_OC_OpGroupNonUniformBallot, 4606 SPIRV_OC_OpGroupNonUniformBallotFindLSB, 4607 SPIRV_OC_OpGroupNonUniformBallotFindMSB, SPIRV_OC_OpGroupNonUniformShuffle, 4608 SPIRV_OC_OpGroupNonUniformShuffleXor, SPIRV_OC_OpGroupNonUniformShuffleUp, 4609 SPIRV_OC_OpGroupNonUniformShuffleDown, SPIRV_OC_OpGroupNonUniformIAdd, 4610 SPIRV_OC_OpGroupNonUniformFAdd, SPIRV_OC_OpGroupNonUniformIMul, 4611 SPIRV_OC_OpGroupNonUniformFMul, SPIRV_OC_OpGroupNonUniformSMin, 4612 SPIRV_OC_OpGroupNonUniformUMin, SPIRV_OC_OpGroupNonUniformFMin, 4613 SPIRV_OC_OpGroupNonUniformSMax, SPIRV_OC_OpGroupNonUniformUMax, 4614 SPIRV_OC_OpGroupNonUniformFMax, SPIRV_OC_OpGroupNonUniformBitwiseAnd, 4615 SPIRV_OC_OpGroupNonUniformBitwiseOr, SPIRV_OC_OpGroupNonUniformBitwiseXor, 4616 SPIRV_OC_OpGroupNonUniformLogicalAnd, SPIRV_OC_OpGroupNonUniformLogicalOr, 4617 SPIRV_OC_OpGroupNonUniformLogicalXor, SPIRV_OC_OpSubgroupBallotKHR, 4618 SPIRV_OC_OpSDot, SPIRV_OC_OpUDot, SPIRV_OC_OpSUDot, SPIRV_OC_OpSDotAccSat, 4619 SPIRV_OC_OpUDotAccSat, SPIRV_OC_OpSUDotAccSat, 4620 SPIRV_OC_OpTypeCooperativeMatrixKHR, SPIRV_OC_OpCooperativeMatrixLoadKHR, 4621 SPIRV_OC_OpCooperativeMatrixStoreKHR, SPIRV_OC_OpCooperativeMatrixMulAddKHR, 4622 SPIRV_OC_OpCooperativeMatrixLengthKHR, SPIRV_OC_OpSubgroupBlockReadINTEL, 4623 SPIRV_OC_OpSubgroupBlockWriteINTEL, SPIRV_OC_OpAssumeTrueKHR, 4624 SPIRV_OC_OpAtomicFAddEXT, SPIRV_OC_OpConvertFToBF16INTEL, 4625 SPIRV_OC_OpConvertBF16ToFINTEL, SPIRV_OC_OpControlBarrierArriveINTEL, 4626 SPIRV_OC_OpControlBarrierWaitINTEL, SPIRV_OC_OpGroupIMulKHR, 4627 SPIRV_OC_OpGroupFMulKHR 4628 ]>; 4629 4630// End opcode section. Generated from SPIR-V spec; DO NOT MODIFY! 4631 4632//===----------------------------------------------------------------------===// 4633// SPIR-V op definitions 4634//===----------------------------------------------------------------------===// 4635 4636// Base class for all SPIR-V ops. 4637class SPIRV_Op<string mnemonic, list<Trait> traits = []> : 4638 Op<SPIRV_Dialect, mnemonic, !listconcat(traits, [ 4639 // TODO: We don't need all of the following traits for every op; only 4640 // the suitable ones should be added automatically after ODS supports 4641 // dialect-specific contents. 4642 DeclareOpInterfaceMethods<QueryMinVersionInterface>, 4643 DeclareOpInterfaceMethods<QueryMaxVersionInterface>, 4644 DeclareOpInterfaceMethods<QueryExtensionInterface>, 4645 DeclareOpInterfaceMethods<QueryCapabilityInterface> 4646 ])> { 4647 // Availability specification for this op itself. 4648 list<Availability> availability = [ 4649 MinVersion<SPIRV_V_1_0>, 4650 MaxVersion<SPIRV_V_1_6>, 4651 Extension<[]>, 4652 Capability<[]> 4653 ]; 4654 4655 // Controls whether to auto-generate this op's availability specification. 4656 // If set, generates the following methods: 4657 // 4658 // ```c++ 4659 // SmallVector<ArrayRef<Capability>, 1> OpTy::getCapabilities(); 4660 // SmallVector<ArrayRef<Extension>, 1> OpTy::getExtensions(); 4661 // Optional<Version> OpTy::getMinVersion(); 4662 // Optional<Version> OpTy::getMaxVersion(); 4663 // ``` 4664 // 4665 // When not set, manual implementation of these methods is required. 4666 bit autogenAvailability = 1; 4667 4668 // For each SPIR-V op, the following static functions need to be defined 4669 // in SPIRVOps.cpp: 4670 // 4671 // * ParseResult <op-c++-class-name>::parse(OpAsmParser &parser, 4672 // OperationState &result) 4673 // * void <op-c++-class-name>::print(OpAsmPrinter &p) 4674 // * LogicalResult <op-c++-class-name>::verify() 4675 let hasCustomAssemblyFormat = 1; 4676 let hasVerifier = 1; 4677 4678 // Specifies whether this op has a direct corresponding SPIR-V binary 4679 // instruction opcode. The (de)serializer use this field to determine whether 4680 // to auto-generate an entry in the (de)serialization dispatch table for this 4681 // op. 4682 bit hasOpcode = 1; 4683 4684 // Name of the corresponding SPIR-V op. Only valid to use when hasOpcode is 1. 4685 string spirvOpName = "Op" # mnemonic; 4686 4687 // Controls whether to auto-generate this op's (de)serialization method. 4688 // If set, it results in generation of the following methods: 4689 // 4690 // ```c++ 4691 // template<typename OpTy> Serializer::processOp(OpTy op); 4692 // template<typename OpTy> Deserializer::processOp(ArrayRef<uint32_t>); 4693 // ``` 4694 // 4695 // If this field is not set, then manual implementation of a specialization of 4696 // these methods is required. 4697 // 4698 // Note: 4699 // 1) If hasOpcode is set but autogenSerialization is not set, the 4700 // (de)serializer dispatch method still calls the above method for 4701 // (de)serializing this op. 4702 // 2) If hasOpcode is not set, but autogenSerialization is set, the 4703 // above methods for (de)serialization are generated, but there is no 4704 // entry added in the dispatch tables to invoke these methods. The 4705 // dispatch needs to be handled manually. SPIRV_ExtInstOps are an 4706 // example of this. 4707 bit autogenSerialization = 1; 4708} 4709 4710class SPIRV_UnaryOp<string mnemonic, Type resultType, Type operandType, 4711 list<Trait> traits = []> : 4712 SPIRV_Op<mnemonic, traits> { 4713 let arguments = (ins 4714 SPIRV_ScalarOrVectorOf<operandType>:$operand 4715 ); 4716 4717 let results = (outs 4718 SPIRV_ScalarOrVectorOf<resultType>:$result 4719 ); 4720 4721 let assemblyFormat = "$operand `:` type($operand) attr-dict"; 4722 // No additional verification needed in addition to the ODS-generated ones. 4723 let hasVerifier = 0; 4724} 4725 4726class SPIRV_BinaryOp<string mnemonic, Type resultType, Type operandsType, 4727 list<Trait> traits = []> : 4728 SPIRV_Op<mnemonic, traits> { 4729 let arguments = (ins 4730 SPIRV_ScalarOrVectorOf<operandsType>:$operand1, 4731 SPIRV_ScalarOrVectorOf<operandsType>:$operand2 4732 ); 4733 4734 let results = (outs 4735 SPIRV_ScalarOrVectorOf<resultType>:$result 4736 ); 4737 4738 // No additional verification needed in addition to the ODS-generated ones. 4739 let hasVerifier = 0; 4740} 4741 4742class SPIRV_ExtInstOp<string mnemonic, string setPrefix, string setName, 4743 int opcode, list<Trait> traits = []> : 4744 SPIRV_Op<setPrefix # "." # mnemonic, traits> { 4745 4746 // Extended instruction sets have no direct opcode (they share the 4747 // same `OpExtInst` instruction). So the hasOpcode field is set to 4748 // false. So no entry corresponding to these ops are added in the 4749 // dispatch functions for (de)serialization. The methods for 4750 // (de)serialization are still automatically generated (since 4751 // autogenSerialization remains 1). A separate method is generated 4752 // for dispatching extended instruction set ops. 4753 let hasOpcode = 0; 4754 4755 // Opcode within extended instruction set. 4756 int extendedInstOpcode = opcode; 4757 4758 // Name used to import the extended instruction set. 4759 string extendedInstSetName = setName; 4760} 4761 4762// Base classes for SPIR-V vendor ops. These have opcode in the form of 4763// Op<Name><VENDOR>, e.g., OpCooperativeMatrixStoreNV. 4764class SPIRV_VendorOp<string mnemonic, string vendorName, 4765 list<Trait> traits = []> : 4766 SPIRV_Op<vendorName # "." # mnemonic, traits> { 4767 string spirvOpName = "Op" # mnemonic # vendorName; 4768} 4769 4770class SPIRV_ExtVendorOp<string mnemonic, list<Trait> traits = []> : 4771 SPIRV_VendorOp<mnemonic, "EXT", traits> { 4772} 4773 4774class SPIRV_KhrVendorOp<string mnemonic, list<Trait> traits = []> : 4775 SPIRV_VendorOp<mnemonic, "KHR", traits> { 4776} 4777 4778class SPIRV_IntelVendorOp<string mnemonic, list<Trait> traits = []> : 4779 SPIRV_VendorOp<mnemonic, "INTEL", traits> { 4780} 4781 4782class SPIRV_NvVendorOp<string mnemonic, list<Trait> traits = []> : 4783 SPIRV_VendorOp<mnemonic, "NV", traits> { 4784} 4785 4786def SPIRV_FPFMM_None : I32BitEnumAttrCaseNone<"None">; 4787def SPIRV_FPFMM_NotNaN : I32BitEnumAttrCaseBit<"NotNaN", 0>; 4788def SPIRV_FPFMM_NotInf : I32BitEnumAttrCaseBit<"NotInf", 1>; 4789def SPIRV_FPFMM_NSZ : I32BitEnumAttrCaseBit<"NSZ", 2>; 4790def SPIRV_FPFMM_AllowRecip : I32BitEnumAttrCaseBit<"AllowRecip", 3>; 4791def SPIRV_FPFMM_Fast : I32BitEnumAttrCaseBit<"Fast", 4>; 4792def SPIRV_FPFMM_AllowContractFastINTEL : I32BitEnumAttrCaseBit<"AllowContractFastINTEL", 16> { 4793 list<Availability> availability = [ 4794 Capability<[SPIRV_C_FPFastMathModeINTEL]> 4795 ]; 4796} 4797def SPIRV_FPFMM_AllowReassocINTEL : I32BitEnumAttrCaseBit<"AllowReassocINTEL", 17> { 4798 list<Availability> availability = [ 4799 Capability<[SPIRV_C_FPFastMathModeINTEL]> 4800 ]; 4801} 4802 4803def SPIRV_FPFastMathModeAttr : 4804 SPIRV_BitEnumAttr<"FPFastMathMode", "Indicates a floating-point fast math flag", "fastmath_mode", [ 4805 SPIRV_FPFMM_None, SPIRV_FPFMM_NotNaN, SPIRV_FPFMM_NotInf, SPIRV_FPFMM_NSZ, 4806 SPIRV_FPFMM_AllowRecip, SPIRV_FPFMM_Fast, SPIRV_FPFMM_AllowContractFastINTEL, 4807 SPIRV_FPFMM_AllowReassocINTEL 4808 ]>; 4809 4810#endif // MLIR_DIALECT_SPIRV_IR_BASE 4811