1;; DFA scheduling description for Renesas / SuperH SH. 2;; Copyright (C) 2004 Free Software Foundation, Inc. 3 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 2, or (at your option) 9;; any later version. 10 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING. If not, write to 18;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 19;; Boston, MA 02110-1301, USA. 20 21;; Load and store instructions save a cycle if they are aligned on a 22;; four byte boundary. Using a function unit for stores encourages 23;; gcc to separate load and store instructions by one instruction, 24;; which makes it more likely that the linker will be able to word 25;; align them when relaxing. 26 27;; SH-1 scheduling. This is just a conversion of the old scheduling 28;; model, using define_function_unit. 29 30(define_automaton "sh1") 31(define_cpu_unit "sh1memory,sh1int,sh1mpy,sh1fp" "sh1") 32 33;; Loads have a latency of two. 34;; However, call insns can have a delay slot, so that we want one more 35;; insn to be scheduled between the load of the function address and the call. 36;; This is equivalent to a latency of three. 37;; ADJUST_COST can only properly handle reductions of the cost, so we 38;; use a latency of three here. 39;; We only do this for SImode loads of general registers, to make the work 40;; for ADJUST_COST easier. 41(define_insn_reservation "sh1_load_si" 3 42 (and (eq_attr "pipe_model" "sh1") 43 (eq_attr "type" "load_si,pcload_si")) 44 "sh1memory*2") 45 46(define_insn_reservation "sh1_load_store" 2 47 (and (eq_attr "pipe_model" "sh1") 48 (eq_attr "type" "load,pcload,pload,store,pstore")) 49 "sh1memory*2") 50 51(define_insn_reservation "sh1_arith3" 3 52 (and (eq_attr "pipe_model" "sh1") 53 (eq_attr "type" "arith3,arith3b")) 54 "sh1int*3") 55 56(define_insn_reservation "sh1_dyn_shift" 2 57 (and (eq_attr "pipe_model" "sh1") 58 (eq_attr "type" "dyn_shift")) 59 "sh1int*2") 60 61(define_insn_reservation "sh1_int" 1 62 (and (eq_attr "pipe_model" "sh1") 63 (eq_attr "type" "!arith3,arith3b,dyn_shift")) 64 "sh1int") 65 66;; ??? These are approximations. 67(define_insn_reservation "sh1_smpy" 2 68 (and (eq_attr "pipe_model" "sh1") 69 (eq_attr "type" "smpy")) 70 "sh1mpy*2") 71 72(define_insn_reservation "sh1_dmpy" 3 73 (and (eq_attr "pipe_model" "sh1") 74 (eq_attr "type" "dmpy")) 75 "sh1mpy*3") 76 77(define_insn_reservation "sh1_fp" 2 78 (and (eq_attr "pipe_model" "sh1") 79 (eq_attr "type" "fp,fmove")) 80 "sh1fp") 81 82(define_insn_reservation "sh1_fdiv" 13 83 (and (eq_attr "pipe_model" "sh1") 84 (eq_attr "type" "fdiv")) 85 "sh1fp*12") 86 87