1//===------ RISCVProfiles.td - RISC-V Profiles -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Profile Featuyre Lists 11//===----------------------------------------------------------------------===// 12 13// RVI Profile Family 14 15defvar RVI20U32Features = [Feature32Bit, FeatureStdExtI]; 16defvar RVI20U64Features = [Feature64Bit, FeatureStdExtI]; 17 18// RVA Profile Family 19 20defvar RVA20U64BaseFeatures = [Feature64Bit, 21 FeatureStdExtI, 22 FeatureStdExtM, 23 FeatureStdExtA, 24 FeatureStdExtF, 25 FeatureStdExtD, 26 FeatureStdExtC, 27 FeatureStdExtZicntr, 28 FeatureStdExtZiccif, 29 FeatureStdExtZiccrse, 30 FeatureStdExtZiccamoa, 31 FeatureStdExtZicclsm]; 32defvar RVA20U64Features = !listconcat(RVA20U64BaseFeatures, 33 [FeatureStdExtZa128rs]); 34 35defvar RVA20S64BaseFeatures = [FeatureStdExtZifencei, 36 FeatureStdExtSvbare, 37 FeatureStdExtSvade, 38 FeatureStdExtSsccptr, 39 FeatureStdExtSstvecd, 40 FeatureStdExtSstvala]; 41defvar RVA20S64Features = !listconcat(RVA20U64Features, 42 RVA20S64BaseFeatures); 43 44defvar RVA22U64Features = !listconcat(RVA20U64BaseFeatures, 45 [FeatureStdExtZa64rs, 46 FeatureStdExtZihpm, 47 FeatureStdExtZihintpause, 48 FeatureStdExtB, 49 FeatureStdExtZic64b, 50 FeatureStdExtZicbom, 51 FeatureStdExtZicbop, 52 FeatureStdExtZicboz, 53 FeatureStdExtZfhmin, 54 FeatureStdExtZkt]); 55 56defvar RVA22S64BaseFeatures = !listconcat(RVA20S64BaseFeatures, 57 [FeatureStdExtSscounterenw, 58 FeatureStdExtSvpbmt, 59 FeatureStdExtSvinval]); 60defvar RVA22S64Features = !listconcat(RVA22U64Features, 61 RVA22S64BaseFeatures); 62 63defvar RVA23U64Features = !listconcat(RVA22U64Features, 64 [FeatureStdExtV, 65 FeatureStdExtZvfhmin, 66 FeatureStdExtZvbb, 67 FeatureStdExtZvkt, 68 FeatureStdExtZihintntl, 69 FeatureStdExtZicond, 70 FeatureStdExtZimop, 71 FeatureStdExtZcmop, 72 FeatureStdExtZcb, 73 FeatureStdExtZfa, 74 FeatureStdExtZawrs, 75 FeatureStdExtSupm]); 76 77defvar RVA23S64BaseFeatures = !listconcat(RVA22S64BaseFeatures, 78 [FeatureStdExtSvnapot, 79 FeatureStdExtSstc, 80 FeatureStdExtSscofpmf, 81 FeatureStdExtSsnpm, 82 FeatureStdExtSsu64xl, 83 FeatureStdExtSha]); 84defvar RVA23S64Features = !listconcat(RVA23U64Features, 85 RVA23S64BaseFeatures); 86 87// RVB Profile Family 88 89defvar RVB23U64Features = !listconcat(RVA20U64BaseFeatures, 90 [FeatureStdExtZihpm, 91 FeatureStdExtZa64rs, 92 FeatureStdExtZihintpause, 93 FeatureStdExtB, 94 FeatureStdExtZic64b, 95 FeatureStdExtZicbom, 96 FeatureStdExtZicbop, 97 FeatureStdExtZicboz, 98 FeatureStdExtZkt, 99 FeatureStdExtZihintntl, 100 FeatureStdExtZicond, 101 FeatureStdExtZimop, 102 FeatureStdExtZcmop, 103 FeatureStdExtZcb, 104 FeatureStdExtZfa, 105 FeatureStdExtZawrs]); 106 107defvar RVB23S64Features = !listconcat(RVB23U64Features, 108 [FeatureStdExtZifencei, 109 FeatureStdExtSvnapot, 110 FeatureStdExtSvbare, 111 FeatureStdExtSvade, 112 FeatureStdExtSsccptr, 113 FeatureStdExtSstvecd, 114 FeatureStdExtSstvala, 115 FeatureStdExtSscounterenw, 116 FeatureStdExtSvpbmt, 117 FeatureStdExtSvinval, 118 FeatureStdExtSstc, 119 FeatureStdExtSscofpmf, 120 FeatureStdExtSsu64xl]); 121 122// RVM Profile Family 123 124defvar RVM23U32Features = [Feature32Bit, 125 FeatureStdExtI, 126 FeatureStdExtM, 127 FeatureStdExtB, 128 FeatureStdExtZicond, 129 FeatureStdExtZihintpause, 130 FeatureStdExtZihintntl, 131 FeatureStdExtZce, 132 FeatureStdExtZicbop, 133 FeatureStdExtZimop, 134 FeatureStdExtZcmop]; 135 136//===----------------------------------------------------------------------===// 137// Profile Definitions for ISA String 138//===----------------------------------------------------------------------===// 139 140class RISCVProfile<string name, list<SubtargetFeature> features> 141 : SubtargetFeature<name, "Is" # NAME, "true", 142 "RISC-V " # name # " profile", features> { 143 // Indicates if the profile is not yet ratified, so should be treated as 144 // experimental. 145 bit Experimental = false; 146} 147class RISCVExperimentalProfile<string name, list<SubtargetFeature> features> 148 : RISCVProfile<"experimental-"#name, features> { 149 let Experimental = true; 150} 151 152def RVI20U32 : RISCVProfile<"rvi20u32", RVI20U32Features>; 153def RVI20U64 : RISCVProfile<"rvi20u64", RVI20U64Features>; 154def RVA20U64 : RISCVProfile<"rva20u64", RVA20U64Features>; 155def RVA20S64 : RISCVProfile<"rva20s64", RVA20S64Features>; 156def RVA22U64 : RISCVProfile<"rva22u64", RVA22U64Features>; 157def RVA22S64 : RISCVProfile<"rva22s64", RVA22S64Features>; 158def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>; 159def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>; 160def RVB23U64 : RISCVProfile<"rvb23u64", RVB23U64Features>; 161def RVB23S64 : RISCVProfile<"rvb23s64", RVB23S64Features>; 162def RVM23U32 : RISCVExperimentalProfile<"rvm23u32", RVM23U32Features>; 163