1 //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISCV ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines an instruction selector for the RISCV target. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H 15 16 #include "RISCV.h" 17 #include "RISCVTargetMachine.h" 18 #include "llvm/CodeGen/SelectionDAGISel.h" 19 20 // RISCV-specific code to select RISCV machine instructions for 21 // SelectionDAG operations. 22 namespace llvm { 23 class RISCVDAGToDAGISel : public SelectionDAGISel { 24 const RISCVSubtarget *Subtarget = nullptr; 25 26 public: RISCVDAGToDAGISel(RISCVTargetMachine & TargetMachine)27 explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine) 28 : SelectionDAGISel(TargetMachine) {} 29 getPassName()30 StringRef getPassName() const override { 31 return "RISCV DAG->DAG Pattern Instruction Selection"; 32 } 33 runOnMachineFunction(MachineFunction & MF)34 bool runOnMachineFunction(MachineFunction &MF) override { 35 Subtarget = &MF.getSubtarget<RISCVSubtarget>(); 36 return SelectionDAGISel::runOnMachineFunction(MF); 37 } 38 39 void PostprocessISelDAG() override; 40 41 void Select(SDNode *Node) override; 42 43 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 44 std::vector<SDValue> &OutOps) override; 45 46 bool SelectAddrFI(SDValue Addr, SDValue &Base); 47 bool SelectBaseAddr(SDValue Addr, SDValue &Base); 48 49 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt); selectShiftMaskXLen(SDValue N,SDValue & ShAmt)50 bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt) { 51 return selectShiftMask(N, Subtarget->getXLen(), ShAmt); 52 } selectShiftMask32(SDValue N,SDValue & ShAmt)53 bool selectShiftMask32(SDValue N, SDValue &ShAmt) { 54 return selectShiftMask(N, 32, ShAmt); 55 } 56 57 bool selectSExti32(SDValue N, SDValue &Val); 58 bool selectZExti32(SDValue N, SDValue &Val); 59 60 bool MatchSLLIUW(SDNode *N) const; 61 62 bool selectVLOp(SDValue N, SDValue &VL); 63 64 bool selectVSplat(SDValue N, SDValue &SplatVal); 65 bool selectVSplatSimm5(SDValue N, SDValue &SplatVal); 66 bool selectVSplatUimm5(SDValue N, SDValue &SplatVal); 67 bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal); 68 bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal); 69 70 bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm); selectRVVSimm5(SDValue N,SDValue & Imm)71 template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) { 72 return selectRVVSimm5(N, Width, Imm); 73 } 74 75 void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, 76 const SDLoc &DL, unsigned CurOp, 77 bool IsMasked, bool IsStridedOrIndexed, 78 SmallVectorImpl<SDValue> &Operands, 79 MVT *IndexVT = nullptr); 80 81 void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided); 82 void selectVLSEGFF(SDNode *Node, bool IsMasked); 83 void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered); 84 void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided); 85 void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered); 86 87 // Include the pieces autogenerated from the target description. 88 #include "RISCVGenDAGISel.inc" 89 90 private: 91 void doPeepholeLoadStoreADDI(); 92 }; 93 94 namespace RISCV { 95 struct VLSEGPseudo { 96 uint8_t NF; 97 uint8_t Masked; 98 uint8_t Strided; 99 uint8_t FF; 100 uint8_t SEW; 101 uint8_t LMUL; 102 uint16_t Pseudo; 103 }; 104 105 struct VLXSEGPseudo { 106 uint8_t NF; 107 uint8_t Masked; 108 uint8_t Ordered; 109 uint8_t SEW; 110 uint8_t LMUL; 111 uint8_t IndexLMUL; 112 uint16_t Pseudo; 113 }; 114 115 struct VSSEGPseudo { 116 uint8_t NF; 117 uint8_t Masked; 118 uint8_t Strided; 119 uint8_t SEW; 120 uint8_t LMUL; 121 uint16_t Pseudo; 122 }; 123 124 struct VSXSEGPseudo { 125 uint8_t NF; 126 uint8_t Masked; 127 uint8_t Ordered; 128 uint8_t SEW; 129 uint8_t LMUL; 130 uint8_t IndexLMUL; 131 uint16_t Pseudo; 132 }; 133 134 struct VLEPseudo { 135 uint8_t Masked; 136 uint8_t Strided; 137 uint8_t FF; 138 uint8_t SEW; 139 uint8_t LMUL; 140 uint16_t Pseudo; 141 }; 142 143 struct VSEPseudo { 144 uint8_t Masked; 145 uint8_t Strided; 146 uint8_t SEW; 147 uint8_t LMUL; 148 uint16_t Pseudo; 149 }; 150 151 struct VLX_VSXPseudo { 152 uint8_t Masked; 153 uint8_t Ordered; 154 uint8_t SEW; 155 uint8_t LMUL; 156 uint8_t IndexLMUL; 157 uint16_t Pseudo; 158 }; 159 160 #define GET_RISCVVSSEGTable_DECL 161 #define GET_RISCVVLSEGTable_DECL 162 #define GET_RISCVVLXSEGTable_DECL 163 #define GET_RISCVVSXSEGTable_DECL 164 #define GET_RISCVVLETable_DECL 165 #define GET_RISCVVSETable_DECL 166 #define GET_RISCVVLXTable_DECL 167 #define GET_RISCVVSXTable_DECL 168 #include "RISCVGenSearchableTables.inc" 169 } // namespace RISCV 170 171 } // namespace llvm 172 173 #endif 174