xref: /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCInstrPrefix.td (revision 82d56013d7b633d116a93943de88e08335357a7c) 
1//-------------------------- Predicate definitions ---------------------------//
2def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;
3
4// Mask immediates for MMA instructions (2, 4 and 8 bits).
5def Msk2Imm : ImmLeaf<i32, [{ return isUInt<2>(Imm); }]>;
6def Msk4Imm : ImmLeaf<i32, [{ return isUInt<4>(Imm); }]>;
7def Msk8Imm : ImmLeaf<i32, [{ return isUInt<8>(Imm); }]>;
8
9//===----------------------------------------------------------------------===//
10// PowerPC ISA 3.1 specific type constraints.
11//
12
13def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>,
14  SDTCisVec<1>, SDTCisInt<2>, SDTCisInt<3>
15]>;
16def SDT_PPCAccBuild : SDTypeProfile<1, 4, [
17  SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>,
18                       SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32>
19]>;
20def SDT_PPCPairBuild : SDTypeProfile<1, 2, [
21  SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>
22]>;
23def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [
24  SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2>
25]>;
26def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [
27  SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2>
28]>;
29def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [
30  SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1>
31]>;
32def SDT_PPCVecInsertElt : SDTypeProfile<1, 3, [
33  SDTCisVec<0>, SDTCisVec<1>, SDTCisInt<3>
34]>;
35
36//===----------------------------------------------------------------------===//
37// ISA 3.1 specific PPCISD nodes.
38//
39
40def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>;
41def PPCAccBuild : SDNode<"PPCISD::ACC_BUILD", SDT_PPCAccBuild, []>;
42def PPCPairBuild : SDNode<"PPCISD::PAIR_BUILD", SDT_PPCPairBuild, []>;
43def PPCAccExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCAccExtractVsx,
44                       []>;
45def PPCPairExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCPairExtractVsx,
46                        []>;
47def PPCxxmfacc : SDNode<"PPCISD::XXMFACC", SDT_PPCxxmfacc, []>;
48def PPCvecinsertelt : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsertElt, []>;
49
50//===----------------------------------------------------------------------===//
51
52// PC Relative flag (for instructions that use the address of the prefix for
53// address computations).
54class isPCRel { bit PCRel = 1; }
55
56// PowerPC specific type constraints.
57def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [
58  SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
59]>;
60
61// PPC Specific DAG Nodes.
62def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX,
63                       [SDNPHasChain, SDNPMayLoad]>;
64
65// Top-level class for prefixed instructions.
66class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
67         InstrItinClass itin> : Instruction {
68  field bits<64> Inst;
69  field bits<64> SoftFail = 0;
70  bit PCRel = 0; // Default value, set by isPCRel.
71  let Size = 8;
72
73  let Namespace = "PPC";
74  let OutOperandList = OOL;
75  let InOperandList = IOL;
76  let AsmString = asmstr;
77  let Itinerary = itin;
78  let Inst{0-5} = pref;
79  let Inst{32-37} = opcode;
80
81  bits<1> PPC970_First = 0;
82  bits<1> PPC970_Single = 0;
83  bits<1> PPC970_Cracked = 0;
84  bits<3> PPC970_Unit = 0;
85
86  /// These fields correspond to the fields in PPCInstrInfo.h.  Any changes to
87  /// these must be reflected there!  See comments there for what these are.
88  let TSFlags{0}   = PPC970_First;
89  let TSFlags{1}   = PPC970_Single;
90  let TSFlags{2}   = PPC970_Cracked;
91  let TSFlags{5-3} = PPC970_Unit;
92
93  bits<1> Prefixed = 1;  // This is a prefixed instruction.
94  let TSFlags{7}  = Prefixed;
95
96  // For cases where multiple instruction definitions really represent the
97  // same underlying instruction but with one definition for 64-bit arguments
98  // and one for 32-bit arguments, this bit breaks the degeneracy between
99  // the two forms and allows TableGen to generate mapping tables.
100  bit Interpretation64Bit = 0;
101
102  // Fields used for relation models.
103  string BaseName = "";
104}
105
106// VX-Form: [ PO VT R VB RC XO ]
107class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
108                      InstrItinClass itin, list<dag> pattern>
109  : I<4, OOL, IOL, asmstr, itin> {
110  bits<5> VT;
111  bits<5> VB;
112  bit RC = 0;
113
114  let Pattern = pattern;
115
116  let Inst{6-10} = VT;
117  let Inst{11-15} = R;
118  let Inst{16-20} = VB;
119  let Inst{21} = RC;
120  let Inst{22-31} = xo;
121}
122
123// Multiclass definition to account for record and non-record form
124// instructions of VXRForm.
125multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,
126                            string asmbase, string asmstr,
127                            InstrItinClass itin, list<dag> pattern> {
128  let BaseName = asmbase in {
129    def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL,
130                               !strconcat(asmbase, !strconcat(" ", asmstr)),
131                               itin, pattern>, RecFormRel;
132    let Defs = [CR6] in
133    def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL,
134                               !strconcat(asmbase, !strconcat(". ", asmstr)),
135                               itin, []>, isRecordForm, RecFormRel;
136  }
137}
138
139class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
140                                InstrItinClass itin, list<dag> pattern>
141  : PI<1, opcode, OOL, IOL, asmstr, itin> {
142  bits<5> FRS;
143  bits<39> D_RA;
144
145  let Pattern = pattern;
146
147  // The prefix.
148  let Inst{6-7} = 2;
149  let Inst{8-10} = 0;
150  let Inst{11} = PCRel;
151  let Inst{12-13} = 0;
152  let Inst{14-31} = D_RA{33-16}; // d0
153
154  // The instruction.
155  let Inst{38-42} = FRS{4-0};
156  let Inst{43-47} = D_RA{38-34}; // RA
157  let Inst{48-63} = D_RA{15-0}; // d1
158}
159
160class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
161                            InstrItinClass itin, list<dag> pattern>
162  : PI<1, opcode, OOL, IOL, asmstr, itin> {
163  bits<5> RT;
164  bits<5> RA;
165  bits<34> SI;
166
167  let Pattern = pattern;
168
169  // The prefix.
170  let Inst{6-7} = 2;
171  let Inst{8-10} = 0;
172  let Inst{11} = PCRel;
173  let Inst{12-13} = 0;
174  let Inst{14-31} = SI{33-16};
175
176  // The instruction.
177  let Inst{38-42} = RT;
178  let Inst{43-47} = RA;
179  let Inst{48-63} = SI{15-0};
180}
181
182class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
183                         InstrItinClass itin, list<dag> pattern>
184  : PI<1, opcode, OOL, IOL, asmstr, itin> {
185  bits<5> RT;
186  bits<34> SI;
187
188  let Pattern = pattern;
189
190  // The prefix.
191  let Inst{6-7} = 2;
192  let Inst{8-10} = 0;
193  let Inst{11} = 0;
194  let Inst{12-13} = 0;
195  let Inst{14-31} = SI{33-16};
196
197  // The instruction.
198  let Inst{38-42} = RT;
199  let Inst{43-47} = 0;
200  let Inst{48-63} = SI{15-0};
201}
202
203multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
204                                   dag PCRel_IOL, string asmstr,
205                                   InstrItinClass itin> {
206  def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
207                                   !strconcat(asmstr, ", 0"), itin, []>;
208  def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
209                                 !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
210}
211
212class 8LS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
213                            InstrItinClass itin, list<dag> pattern>
214  : PI<1, opcode, OOL, IOL, asmstr, itin> {
215  bits<5> RT;
216  bits<39> D_RA;
217
218  let Pattern = pattern;
219
220  // The prefix.
221  let Inst{6-10} = 0;
222  let Inst{11} = PCRel;
223  let Inst{12-13} = 0;
224  let Inst{14-31} = D_RA{33-16}; // d0
225
226  // The instruction.
227  let Inst{38-42} = RT{4-0};
228  let Inst{43-47} = D_RA{38-34}; // RA
229  let Inst{48-63} = D_RA{15-0}; // d1
230}
231
232// 8LS:D-Form: [ 1 0 0 // R // d0
233//               PO TX T RA d1 ]
234class 8LS_DForm_R_SI34_XT6_RA5<bits<5> opcode, dag OOL, dag IOL, string asmstr,
235                               InstrItinClass itin, list<dag> pattern>
236  : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> {
237  bits<6> XT;
238  bits<39> D_RA;
239
240  let Pattern = pattern;
241
242  // The prefix.
243  let Inst{6-7} = 0;
244  let Inst{8} = 0;
245  let Inst{9-10} = 0; // reserved
246  let Inst{11} = PCRel;
247  let Inst{12-13} = 0; // reserved
248  let Inst{14-31} = D_RA{33-16}; // d0
249
250  // The instruction.
251  let Inst{37} = XT{5};
252  let Inst{38-42} = XT{4-0};
253  let Inst{43-47} = D_RA{38-34}; // RA
254  let Inst{48-63} = D_RA{15-0}; // d1
255}
256
257// X-Form: [PO T IMM VRB XO TX]
258class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
259                         string asmstr, InstrItinClass itin, list<dag> pattern>
260  : I<opcode, OOL, IOL, asmstr, itin> {
261  bits<6> XT;
262  bits<5> VRB;
263  bits<5> IMM;
264
265  let Pattern = pattern;
266  let Inst{6-10} = XT{4-0};
267  let Inst{11-15} = IMM;
268  let Inst{16-20} = VRB;
269  let Inst{21-30} = xo;
270  let Inst{31} = XT{5};
271}
272
273class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo,
274                             dag OOL, dag IOL, string asmstr,
275                             InstrItinClass itin, list<dag> pattern>
276  : PI<1, opcode, OOL, IOL, asmstr, itin> {
277    bits<6> XT;
278    bits<6> XA;
279    bits<6> XB;
280    bits<6> XC;
281    bits<8> IMM;
282
283    let Pattern = pattern;
284
285    // The prefix.
286    let Inst{6-7} = 1;
287    let Inst{8} = 0;
288    let Inst{9-11} = 0;
289    let Inst{12-13} = 0;
290    let Inst{14-23} = 0;
291    let Inst{24-31} = IMM;
292
293    // The instruction.
294    let Inst{38-42} = XT{4-0};
295    let Inst{43-47} = XA{4-0};
296    let Inst{48-52} = XB{4-0};
297    let Inst{53-57} = XC{4-0};
298    let Inst{58-59} = xo;
299    let Inst{60} = XC{5};
300    let Inst{61} = XA{5};
301    let Inst{62} = XB{5};
302    let Inst{63} = XT{5};
303}
304
305class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
306                        InstrItinClass itin, list<dag> pattern>
307  : I<4, OOL, IOL, asmstr, itin> {
308  bits<5> RD;
309  bits<5> VB;
310  bits<3> N;
311
312  let Pattern = pattern;
313
314  let Inst{6-10}  = RD;
315  let Inst{11-12} = 0;
316  let Inst{13-15} = N;
317  let Inst{16-20} = VB;
318  let Inst{21-31} = xo;
319}
320
321
322// VX-Form: [PO VRT RA VRB XO].
323// Destructive (insert) forms are suffixed with _ins.
324class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
325  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, vrrc:$vB),
326             !strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>,
327             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
328
329// VX-Form: [PO VRT RA RB XO].
330// Destructive (insert) forms are suffixed with _ins.
331class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern>
332  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, gprc:$rB),
333             !strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>,
334             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
335
336// VX-Form: [ PO BF // VRA VRB XO ]
337class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
338                      InstrItinClass itin, list<dag> pattern>
339  : I<4, OOL, IOL, asmstr, itin> {
340  bits<3> BF;
341  bits<5> VA;
342  bits<5> VB;
343
344  let Pattern = pattern;
345
346  let Inst{6-8} = BF;
347  let Inst{9-10} = 0;
348  let Inst{11-15} = VA;
349  let Inst{16-20} = VB;
350  let Inst{21-31} = xo;
351}
352
353// VN-Form: [PO VRT VRA VRB PS SD XO]
354// SD is "Shift Direction"
355class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
356                       InstrItinClass itin, list<dag> pattern>
357    : I<4, OOL, IOL, asmstr, itin> {
358  bits<5> VRT;
359  bits<5> VRA;
360  bits<5> VRB;
361  bits<3> SD;
362
363  let Pattern = pattern;
364
365  let Inst{6-10}  = VRT;
366  let Inst{11-15} = VRA;
367  let Inst{16-20} = VRB;
368  let Inst{21-22} = ps;
369  let Inst{23-25} = SD;
370  let Inst{26-31} = xo;
371}
372
373class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL,
374                        string asmstr, InstrItinClass itin, list<dag> pattern>
375  : I<4, OOL, IOL, asmstr, itin> {
376  bits<5> RD;
377  bits<5> VB;
378  bit MP;
379
380  let Pattern = pattern;
381
382  let Inst{6-10}  = RD;
383  let Inst{11-14} = eo;
384  let Inst{15} = MP;
385  let Inst{16-20} = VB;
386  let Inst{21-31} = xo;
387}
388
389// 8RR:D-Form: [ 1 1 0 // // imm0
390//               PO T XO TX imm1 ].
391class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
392                          string asmstr, InstrItinClass itin,
393                          list<dag> pattern>
394  : PI<1, opcode, OOL, IOL, asmstr, itin> {
395  bits<6> XT;
396  bits<32> IMM32;
397
398  let Pattern = pattern;
399
400  // The prefix.
401  let Inst{6-7} = 1;
402  let Inst{8-11} = 0;
403  let Inst{12-13} = 0; // reserved
404  let Inst{14-15} = 0; // reserved
405  let Inst{16-31} = IMM32{31-16};
406
407  // The instruction.
408  let Inst{38-42} = XT{4-0};
409  let Inst{43-46} = xo;
410  let Inst{47} = XT{5};
411  let Inst{48-63} = IMM32{15-0};
412}
413
414// 8RR:D-Form: [ 1 1 0 // // imm0
415//               PO T XO IX TX imm1 ].
416class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
417                             string asmstr, InstrItinClass itin,
418                             list<dag> pattern>
419  : PI<1, opcode, OOL, IOL, asmstr, itin> {
420  bits<6> XT;
421  bit IX;
422  bits<32> IMM32;
423
424  let Pattern = pattern;
425
426  // The prefix.
427  let Inst{6-7} = 1;
428  let Inst{8-11} = 0;
429  let Inst{12-13} = 0; // reserved
430  let Inst{14-15} = 0; // reserved
431  let Inst{16-31} = IMM32{31-16};
432
433  // The instruction.
434  let Inst{38-42} = XT{4-0};
435  let Inst{43-45} = xo;
436  let Inst{46} = IX;
437  let Inst{47} = XT{5};
438  let Inst{48-63} = IMM32{15-0};
439}
440
441class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
442                         string asmstr, InstrItinClass itin, list<dag> pattern>
443  : PI<1, opcode, OOL, IOL, asmstr, itin> {
444  bits<6> XT;
445  bits<6> XA;
446  bits<6> XB;
447  bits<6> XC;
448
449  let Pattern = pattern;
450
451  // The prefix.
452  let Inst{6-7} = 1;
453  let Inst{8-11} = 0;
454  let Inst{12-13} = 0;
455  let Inst{14-31} = 0;
456
457  // The instruction.
458  let Inst{38-42} = XT{4-0};
459  let Inst{43-47} = XA{4-0};
460  let Inst{48-52} = XB{4-0};
461  let Inst{53-57} = XC{4-0};
462  let Inst{58-59} = xo;
463  let Inst{60} = XC{5};
464  let Inst{61} = XA{5};
465  let Inst{62} = XB{5};
466  let Inst{63} = XT{5};
467}
468
469class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
470                              string asmstr, InstrItinClass itin,
471                              list<dag> pattern>
472  : PI<1, opcode, OOL, IOL, asmstr, itin> {
473  bits<6> XT;
474  bits<6> XA;
475  bits<6> XB;
476  bits<6> XC;
477  bits<3> IMM;
478
479  let Pattern = pattern;
480
481  // The prefix.
482  let Inst{6-7} = 1;
483  let Inst{8-11} = 0;
484  let Inst{12-13} = 0;
485  let Inst{14-28} = 0;
486  let Inst{29-31} = IMM;
487
488  // The instruction.
489  let Inst{38-42} = XT{4-0};
490  let Inst{43-47} = XA{4-0};
491  let Inst{48-52} = XB{4-0};
492  let Inst{53-57} = XC{4-0};
493  let Inst{58-59} = xo;
494  let Inst{60} = XC{5};
495  let Inst{61} = XA{5};
496  let Inst{62} = XB{5};
497  let Inst{63} = XT{5};
498}
499
500// [PO BF / XO2 B XO BX /]
501class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL,
502                          dag IOL, string asmstr, InstrItinClass itin,
503                          list<dag> pattern>
504  : I<opcode, OOL, IOL, asmstr, itin> {
505  bits<3> BF;
506  bits<6> XB;
507
508  let Pattern = pattern;
509
510  let Inst{6-8}   = BF;
511  let Inst{9-10}  = 0;
512  let Inst{11-15} = xo2;
513  let Inst{16-20} = XB{4-0};
514  let Inst{21-29} = xo;
515  let Inst{30}    = XB{5};
516  let Inst{31}    = 0;
517}
518
519// X-Form: [ PO RT BI /// XO / ]
520class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
521                    string asmstr, InstrItinClass itin, list<dag> pattern>
522  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
523  let B = 0;
524}
525
526multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
527                                       dag PCRel_IOL, string asmstr,
528                                       InstrItinClass itin> {
529  def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
530                                       !strconcat(asmstr, ", 0"), itin, []>;
531  def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
532                                     !strconcat(asmstr, ", 1"), itin, []>,
533                                     isPCRel;
534}
535
536multiclass 8LS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
537                                   dag PCRel_IOL, string asmstr,
538                                   InstrItinClass itin> {
539  def NAME : 8LS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
540                                   !strconcat(asmstr, ", 0"), itin, []>;
541  def pc : 8LS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
542                                 !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
543}
544
545multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
546                                      dag PCRel_IOL, string asmstr,
547                                      InstrItinClass itin> {
548  def NAME : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, IOL,
549                                      !strconcat(asmstr, ", 0"), itin, []>;
550  def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL,
551                                    !strconcat(asmstr, ", 1"), itin, []>,
552                                    isPCRel;
553}
554
555def PPCRegVSRpRCAsmOperand : AsmOperandClass {
556  let Name = "RegVSRpRC"; let PredicateMethod = "isVSRpEvenRegNumber";
557}
558
559def vsrprc : RegisterOperand<VSRpRC> {
560  let ParserMatchClass = PPCRegVSRpRCAsmOperand;
561}
562
563def PPCRegVSRpEvenRCAsmOperand : AsmOperandClass {
564  let Name = "RegVSRpEvenRC"; let PredicateMethod = "isVSRpEvenRegNumber";
565}
566
567def vsrpevenrc : RegisterOperand<VSRpRC> {
568  let ParserMatchClass = PPCRegVSRpEvenRCAsmOperand;
569  let EncoderMethod = "getVSRpEvenEncoding";
570  let DecoderMethod = "decodeVSRpEvenOperands";
571}
572
573class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
574                           string asmstr, InstrItinClass itin, list<dag> pattern>
575  : I<opcode, OOL, IOL, asmstr, itin> {
576  bits<5> XTp;
577  bits<17> DQ_RA;
578  let Pattern = pattern;
579
580  let Inst{6-9} = XTp{3-0};
581  let Inst{10} = XTp{4};
582  let Inst{11-15} = DQ_RA{16-12};  // Register #
583  let Inst{16-27} = DQ_RA{11-0};   // Displacement.
584  let Inst{28-31} = xo;
585}
586
587class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
588                      string asmstr, InstrItinClass itin, list<dag> pattern>
589  : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp {
590  bits<5> XTp;
591  bits<5> A;
592  bits<5> B;
593
594  let Pattern = pattern;
595  let Inst{6-9} = XTp{3-0};
596  let Inst{10} = XTp{4};
597  let Inst{11-15} = A;
598  let Inst{16-20} = B;
599  let Inst{21-30} = xo;
600  let Inst{31} = 0;
601}
602
603class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
604                                InstrItinClass itin, list<dag> pattern>
605  : PI<1, opcode, OOL, IOL, asmstr, itin> {
606  bits<5> XTp;
607  bits<39> D_RA;
608
609  let Pattern = pattern;
610
611  // The prefix.
612  let Inst{6-10} = 0;
613  let Inst{11} = PCRel;
614  let Inst{12-13} = 0;
615  let Inst{14-31} = D_RA{33-16}; // Imm18
616
617  // The instruction.
618  let Inst{38-41} = XTp{3-0};
619  let Inst{42}    = XTp{4};
620  let Inst{43-47} = D_RA{38-34};   // Register #
621  let Inst{48-63} = D_RA{15-0};    // D
622}
623
624multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> pref, bits<6> opcode, dag OOL,
625                                       dag IOL, dag PCRel_IOL,
626                                       string asmstr, InstrItinClass itin> {
627  def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL,
628                                       !strconcat(asmstr, ", 0"), itin, []>;
629  def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL,
630                                     !strconcat(asmstr, ", 1"), itin, []>,
631                                     isPCRel;
632}
633
634def PPCRegACCRCAsmOperand : AsmOperandClass {
635  let Name = "RegACCRC"; let PredicateMethod = "isACCRegNumber";
636}
637
638def acc : RegisterOperand<ACCRC> {
639  let ParserMatchClass = PPCRegACCRCAsmOperand;
640}
641
642def uacc : RegisterOperand<UACCRC> {
643  let ParserMatchClass = PPCRegACCRCAsmOperand;
644}
645
646// [PO AS XO2 XO]
647class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
648                    string asmstr, InstrItinClass itin, list<dag> pattern>
649  : I<opcode, OOL, IOL, asmstr, itin> {
650  bits<3> AT;
651
652  let Pattern = pattern;
653
654  let Inst{6-8}  = AT;
655  let Inst{9-10}  = 0;
656  let Inst{11-15} = xo2;
657  let Inst{16-20} = 0;
658  let Inst{21-30} = xo;
659  let Inst{31} = 0;
660}
661
662class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
663                           string asmstr, InstrItinClass itin,
664                           list<dag> pattern>
665  : I<opcode, OOL, IOL, asmstr, itin> {
666  bits<3> AT;
667  bits<6> XA;
668  bits<6> XB;
669
670  let Pattern = pattern;
671
672  let Inst{6-8} = AT;
673  let Inst{9-10} = 0;
674  let Inst{11-15} = XA{4-0};
675  let Inst{16-20} = XB{4-0};
676  let Inst{21-28} = xo;
677  let Inst{29}    = XA{5};
678  let Inst{30}    = XB{5};
679  let Inst{31} = 0;
680}
681
682class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
683                               string asmstr, InstrItinClass itin,
684                               list<dag> pattern>
685  : PI<1, opcode, OOL, IOL, asmstr, itin> {
686  bits<3> AT;
687  bits<6> XA;
688  bits<6> XB;
689  bits<4> XMSK;
690  bits<4> YMSK;
691  bits<2> PMSK;
692
693  let Pattern = pattern;
694
695  // The prefix.
696  let Inst{6-7} = 3;
697  let Inst{8-11} = 9;
698  let Inst{12-15} = 0;
699  let Inst{16-17} = PMSK;
700  let Inst{18-23} = 0;
701  let Inst{24-27} = XMSK;
702  let Inst{28-31} = YMSK;
703
704  // The instruction.
705  let Inst{38-40} = AT;
706  let Inst{41-42} = 0;
707  let Inst{43-47} = XA{4-0};
708  let Inst{48-52} = XB{4-0};
709  let Inst{53-60} = xo;
710  let Inst{61} = XA{5};
711  let Inst{62} = XB{5};
712  let Inst{63} = 0;
713}
714
715class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
716                             string asmstr, InstrItinClass itin,
717                             list<dag> pattern>
718  : PI<1, opcode, OOL, IOL, asmstr, itin> {
719  bits<3> AT;
720  bits<6> XA;
721  bits<6> XB;
722  bits<4> XMSK;
723  bits<4> YMSK;
724
725  let Pattern = pattern;
726
727  // The prefix.
728  let Inst{6-7} = 3;
729  let Inst{8-11} = 9;
730  let Inst{12-23} = 0;
731  let Inst{24-27} = XMSK;
732  let Inst{28-31} = YMSK;
733
734  // The instruction.
735  let Inst{38-40} = AT;
736  let Inst{41-42} = 0;
737  let Inst{43-47} = XA{4-0};
738  let Inst{48-52} = XB{4-0};
739  let Inst{53-60} = xo;
740  let Inst{61} = XA{5};
741  let Inst{62} = XB{5};
742  let Inst{63} = 0;
743}
744
745class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
746                              string asmstr, InstrItinClass itin,
747                              list<dag> pattern>
748  : PI<1, opcode, OOL, IOL, asmstr, itin> {
749  bits<3> AT;
750  bits<6> XA;
751  bits<6> XB;
752  bits<4> XMSK;
753  bits<2> YMSK;
754
755  let Pattern = pattern;
756
757  // The prefix.
758  let Inst{6-7} = 3;
759  let Inst{8-11} = 9;
760  let Inst{12-23} = 0;
761  let Inst{24-27} = XMSK;
762  let Inst{28-29} = YMSK;
763  let Inst{30-31} = 0;
764
765  // The instruction.
766  let Inst{38-40} = AT;
767  let Inst{41-42} = 0;
768  let Inst{43-47} = XA{4-0};
769  let Inst{48-52} = XB{4-0};
770  let Inst{53-60} = xo;
771  let Inst{61} = XA{5};
772  let Inst{62} = XB{5};
773  let Inst{63} = 0;
774}
775
776class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
777                               string asmstr, InstrItinClass itin,
778                               list<dag> pattern>
779  : PI<1, opcode, OOL, IOL, asmstr, itin> {
780  bits<3> AT;
781  bits<6> XA;
782  bits<6> XB;
783  bits<4> XMSK;
784  bits<4> YMSK;
785  bits<8> PMSK;
786
787  let Pattern = pattern;
788
789  // The prefix.
790  let Inst{6-7} = 3;
791  let Inst{8-11} = 9;
792  let Inst{12-15} = 0;
793  let Inst{16-23} = PMSK;
794  let Inst{24-27} = XMSK;
795  let Inst{28-31} = YMSK;
796
797  // The instruction.
798  let Inst{38-40} = AT;
799  let Inst{41-42} = 0;
800  let Inst{43-47} = XA{4-0};
801  let Inst{48-52} = XB{4-0};
802  let Inst{53-60} = xo;
803  let Inst{61} = XA{5};
804  let Inst{62} = XB{5};
805  let Inst{63} = 0;
806}
807
808class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
809                              string asmstr, InstrItinClass itin,
810                              list<dag> pattern>
811  : PI<1, opcode, OOL, IOL, asmstr, itin> {
812  bits<3> AT;
813  bits<6> XA;
814  bits<6> XB;
815  bits<4> XMSK;
816  bits<4> YMSK;
817  bits<4> PMSK;
818
819  let Pattern = pattern;
820
821  // The prefix.
822  let Inst{6-7} = 3;
823  let Inst{8-11} = 9;
824  let Inst{12-15} = 0;
825  let Inst{16-19} = PMSK;
826  let Inst{20-23} = 0;
827  let Inst{24-27} = XMSK;
828  let Inst{28-31} = YMSK;
829
830  // The instruction.
831  let Inst{38-40} = AT;
832  let Inst{41-42} = 0;
833  let Inst{43-47} = XA{4-0};
834  let Inst{48-52} = XB{4-0};
835  let Inst{53-60} = xo;
836  let Inst{61} = XA{5};
837  let Inst{62} = XB{5};
838  let Inst{63} = 0;
839}
840
841def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
842def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
843def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
844def MMA : Predicate<"Subtarget->hasMMA()">;
845
846def RCCp {
847  dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);
848  dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);
849}
850
851let Predicates = [PrefixInstrs] in {
852  let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
853    defm PADDI8 :
854      MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
855                              (ins immZero:$RA, s34imm_pcrel:$SI),
856                              "paddi $RT, $RA, $SI", IIC_LdStLFD>;
857    let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
858      def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
859                                    (ins s34imm:$SI),
860                                    "pli $RT, $SI", IIC_IntSimple, []>;
861    }
862  }
863  defm PADDI :
864    MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),
865                            (ins immZero:$RA, s34imm_pcrel:$SI),
866                            "paddi $RT, $RA, $SI", IIC_LdStLFD>;
867  let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
868    def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
869                                 (ins s34imm:$SI),
870                                 "pli $RT, $SI", IIC_IntSimple, []>;
871  }
872
873  let mayLoad = 1, mayStore = 0 in {
874    defm PLXV :
875      8LS_DForm_R_SI34_XT6_RA5_p<25, (outs vsrc:$XT), (ins memri34:$D_RA),
876                                 (ins memri34_pcrel:$D_RA), "plxv $XT, $D_RA",
877                                 IIC_LdStLFD>;
878    defm PLFS :
879      MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA),
880                                  (ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA",
881                                  IIC_LdStLFD>;
882    defm PLFD :
883      MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA),
884                                  (ins  memri34_pcrel:$D_RA), "plfd $FRT, $D_RA",
885                                  IIC_LdStLFD>;
886    defm PLXSSP :
887      8LS_DForm_R_SI34_RTA5_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA),
888                              (ins memri34_pcrel:$D_RA), "plxssp $VRT, $D_RA",
889                              IIC_LdStLFD>;
890    defm PLXSD :
891      8LS_DForm_R_SI34_RTA5_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA),
892                              (ins memri34_pcrel:$D_RA), "plxsd $VRT, $D_RA",
893                              IIC_LdStLFD>;
894    let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
895      defm PLBZ8 :
896        MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA),
897                                    (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
898                                    IIC_LdStLFD>;
899      defm PLHZ8 :
900        MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA),
901                                    (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
902                                    IIC_LdStLFD>;
903      defm PLHA8 :
904        MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA),
905                                    (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
906                                    IIC_LdStLFD>;
907      defm PLWA8 :
908        8LS_DForm_R_SI34_RTA5_p<41, (outs g8rc:$RT), (ins memri34:$D_RA),
909                                (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
910                                IIC_LdStLFD>;
911      defm PLWZ8 :
912        MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA),
913                                    (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
914                                    IIC_LdStLFD>;
915    }
916    defm PLBZ :
917      MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA),
918                                  (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
919                                  IIC_LdStLFD>;
920    defm PLHZ :
921      MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA),
922                                  (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
923                                  IIC_LdStLFD>;
924    defm PLHA :
925      MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA),
926                                  (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
927                                  IIC_LdStLFD>;
928    defm PLWZ :
929      MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA),
930                                  (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
931                                  IIC_LdStLFD>;
932    defm PLWA :
933      8LS_DForm_R_SI34_RTA5_p<41, (outs gprc:$RT), (ins memri34:$D_RA),
934                              (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
935                              IIC_LdStLFD>;
936    defm PLD :
937      8LS_DForm_R_SI34_RTA5_p<57, (outs g8rc:$RT), (ins memri34:$D_RA),
938                              (ins memri34_pcrel:$D_RA), "pld $RT, $D_RA",
939                              IIC_LdStLFD>;
940  }
941
942  let mayStore = 1, mayLoad = 0 in {
943    defm PSTXV :
944      8LS_DForm_R_SI34_XT6_RA5_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA),
945                                 (ins vsrc:$XS, memri34_pcrel:$D_RA),
946                                 "pstxv $XS, $D_RA", IIC_LdStLFD>;
947    defm PSTFS :
948      MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA),
949                                  (ins f4rc:$FRS, memri34_pcrel:$D_RA),
950                                  "pstfs $FRS, $D_RA", IIC_LdStLFD>;
951    defm PSTFD :
952      MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA),
953                                  (ins f8rc:$FRS, memri34_pcrel:$D_RA),
954                                  "pstfd $FRS, $D_RA", IIC_LdStLFD>;
955    defm PSTXSSP :
956      8LS_DForm_R_SI34_RTA5_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA),
957                              (ins vfrc:$VRS, memri34_pcrel:$D_RA),
958                              "pstxssp $VRS, $D_RA", IIC_LdStLFD>;
959    defm PSTXSD :
960      8LS_DForm_R_SI34_RTA5_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA),
961                              (ins vfrc:$VRS, memri34_pcrel:$D_RA),
962                              "pstxsd $VRS, $D_RA", IIC_LdStLFD>;
963    let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
964      defm PSTB8 :
965        MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA),
966                                    (ins g8rc:$RS, memri34_pcrel:$D_RA),
967                                    "pstb $RS, $D_RA", IIC_LdStLFD>;
968      defm PSTH8 :
969        MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA),
970                                    (ins g8rc:$RS, memri34_pcrel:$D_RA),
971                                    "psth $RS, $D_RA", IIC_LdStLFD>;
972      defm PSTW8 :
973        MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA),
974                                    (ins g8rc:$RS, memri34_pcrel:$D_RA),
975                                    "pstw $RS, $D_RA", IIC_LdStLFD>;
976    }
977    defm PSTB :
978      MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA),
979                                  (ins gprc:$RS, memri34_pcrel:$D_RA),
980                                  "pstb $RS, $D_RA", IIC_LdStLFD>;
981    defm PSTH :
982      MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA),
983                                  (ins gprc:$RS, memri34_pcrel:$D_RA),
984                                  "psth $RS, $D_RA", IIC_LdStLFD>;
985    defm PSTW :
986      MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA),
987                                  (ins gprc:$RS, memri34_pcrel:$D_RA),
988                                  "pstw $RS, $D_RA", IIC_LdStLFD>;
989    defm PSTD :
990      8LS_DForm_R_SI34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
991                              (ins g8rc:$RS, memri34_pcrel:$D_RA),
992                              "pstd $RS, $D_RA", IIC_LdStLFD>;
993  }
994}
995
996// Multiclass definitions for MMA accumulator instructions.
997// ----------------------------------------------------------------------------
998
999// Defines 2 unmasked instructions where the xo field for acc/non-acc version
1000// is even/odd.
1001multiclass ACC_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
1002                       string asmstr> {
1003  let Predicates = [MMA] in {
1004  def NAME :
1005    XX3Form_AT3_XAB6<opcode, !or(xo, 0x01), (outs acc:$AT), IOL,
1006                     !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
1007    RegConstraint<"@earlyclobber $AT">;
1008  def PP :
1009    XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), !con((ins acc:$ATi), IOL),
1010                     !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
1011    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1012  }
1013}
1014
1015// Defines 4 instructions, masked/unmasked with masks 8, 4, 4 bits.
1016// The XO field for acc/non-acc version is even/odd.
1017multiclass ACC_UM_M844_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
1018                            string asmstr> {
1019  defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
1020  let Predicates = [MMA, PrefixInstrs] in {
1021  def PM#NAME :
1022    MMIRR_XX3Form_XY4P8_XAB6<
1023      opcode, !or(xo, 0x01), (outs acc:$AT),
1024      !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK)),
1025      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
1026      IIC_VecFP, []>,
1027    RegConstraint<"@earlyclobber $AT">;
1028  def PM#NAME#PP :
1029    MMIRR_XX3Form_XY4P8_XAB6<
1030      opcode, xo, (outs acc:$AT),
1031      !con((ins acc:$ATi),
1032           !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK))),
1033      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
1034      IIC_VecFP, []>,
1035    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1036  }
1037}
1038
1039// Defines 4 instructions, masked/unmasked with masks 4, 4, 4 bits.
1040// The XO field for acc/non-acc version is even/odd.
1041multiclass ACC_UM_M444_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
1042                            string asmstr> {
1043  defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
1044  let Predicates = [MMA, PrefixInstrs] in {
1045  def PM#NAME :
1046    MMIRR_XX3Form_XYP4_XAB6<
1047      opcode, !or(xo, 0x01), (outs acc:$AT),
1048      !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)),
1049      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
1050      IIC_VecFP, []>,
1051    RegConstraint<"@earlyclobber $AT">;
1052  def PM#NAME#PP :
1053    MMIRR_XX3Form_XYP4_XAB6<
1054      opcode, xo, (outs acc:$AT),
1055      !con((ins acc:$ATi),
1056           !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),
1057      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
1058      IIC_VecFP, []>,
1059    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1060  }
1061}
1062
1063// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits.
1064// The XO field for acc/non-acc version is even/odd.
1065multiclass ACC_UM_M244_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
1066                            string asmstr> {
1067  defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
1068  let Predicates = [MMA, PrefixInstrs] in {
1069  def PM#NAME :
1070    MMIRR_XX3Form_XY4P2_XAB6<
1071      opcode, !or(xo, 0x01), (outs acc:$AT),
1072      !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
1073      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
1074      IIC_VecFP, []>,
1075    RegConstraint<"@earlyclobber $AT">;
1076  def PM#NAME#PP :
1077    MMIRR_XX3Form_XY4P2_XAB6<
1078      opcode, xo, (outs acc:$AT),
1079      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
1080      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
1081      IIC_VecFP, []>,
1082    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1083  }
1084}
1085
1086// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits.
1087// Upper nibble of XO field for acc/non-acc version is 0x4/0x6.
1088multiclass ACC_UM_M244_XO46<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
1089                            string asmstr> {
1090  let Predicates = [MMA] in {
1091  def NAME :
1092    XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), IOL,
1093                     !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
1094    RegConstraint<"@earlyclobber $AT">;
1095  def PP :
1096    XX3Form_AT3_XAB6<
1097      opcode, !or(xo, 0x20), (outs acc:$AT), !con((ins acc:$ATi), IOL),
1098      !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
1099    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1100  }
1101  let Predicates = [MMA, PrefixInstrs] in {
1102  def PM#NAME :
1103    MMIRR_XX3Form_XY4P2_XAB6<
1104      opcode, xo, (outs acc:$AT),
1105      !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
1106      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
1107      IIC_VecFP, []>,
1108    RegConstraint<"@earlyclobber $AT">;
1109  def PM#NAME#PP :
1110    MMIRR_XX3Form_XY4P2_XAB6<
1111      opcode, !or(xo, 0x20), (outs acc:$AT),
1112      !con((ins acc:$ATi),
1113           !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
1114      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
1115      IIC_VecFP, []>,
1116    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1117  }
1118}
1119
1120// Defines 10 instructions, operand negating, unmasked, masked with 2, 4, 4
1121// bits. Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
1122multiclass ACC_NEG_UM_M244_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
1123                                  string asmbase, string asmstr> {
1124  defm NAME : ACC_UM_M244_XOEO<opcode, xo, IOL, asmbase, asmstr>;
1125  let Predicates = [MMA] in {
1126  def PN : XX3Form_AT3_XAB6<
1127             opcode, !or(xo, 0x80), (outs acc:$AT), !con((ins acc:$ATi), IOL),
1128             !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
1129           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1130  def NP : XX3Form_AT3_XAB6<
1131             opcode, !or(xo, 0x40), (outs acc:$AT), !con((ins acc:$ATi), IOL),
1132             !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
1133           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1134  def NN : XX3Form_AT3_XAB6<
1135             opcode, !or(xo, 0xC0), (outs acc:$AT), !con((ins acc:$ATi), IOL),
1136             !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
1137           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1138  }
1139  let Predicates = [MMA, PrefixInstrs] in {
1140  def PM#NAME#PN :
1141    MMIRR_XX3Form_XY4P2_XAB6<
1142      opcode, !or(xo, 0x80), (outs acc:$AT),
1143      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
1144      !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),
1145      IIC_VecFP, []>,
1146    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1147  def PM#NAME#NP :
1148    MMIRR_XX3Form_XY4P2_XAB6<
1149      opcode, !or(xo, 0x40), (outs acc:$AT),
1150      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
1151      !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),
1152      IIC_VecFP, []>,
1153    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1154  def PM#NAME#NN :
1155    MMIRR_XX3Form_XY4P2_XAB6<
1156      opcode, !or(xo, 0xC0), (outs acc:$AT),
1157      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
1158      !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),
1159      IIC_VecFP, []>,
1160    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1161  }
1162}
1163
1164// Defines 5 instructions, unmasked, operand negating.
1165// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
1166multiclass ACC_NEG_UM_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
1167                             string asmbase, string asmstr> {
1168  defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
1169  let Predicates = [MMA] in {
1170  def PN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs acc:$AT),
1171                            !con((ins acc:$ATi), IOL),
1172                            !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
1173           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1174  def NP : XX3Form_AT3_XAB6<opcode, !or(xo, 0x40), (outs acc:$AT),
1175                            !con((ins acc:$ATi), IOL),
1176                            !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
1177           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1178  def NN : XX3Form_AT3_XAB6<opcode, !or(xo, 0xC0), (outs acc:$AT),
1179                            !con((ins acc:$ATi), IOL),
1180                            !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
1181           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1182  }
1183}
1184
1185// Defines 10 instructions, operand negating, unmasked, masked with 4, 4 bits.
1186// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
1187multiclass ACC_NEG_UM_M44_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
1188                                 string asmbase, string asmstr> {
1189  defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>;
1190  let Predicates = [MMA, PrefixInstrs] in {
1191  def PM#NAME :
1192    MMIRR_XX3Form_XY4_XAB6<
1193      opcode, !or(xo, 0x01), (outs acc:$AT),
1194      !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK)),
1195      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),
1196      IIC_VecFP, []>,
1197    RegConstraint<"@earlyclobber $AT">;
1198  def PM#NAME#PP :
1199    MMIRR_XX3Form_XY4_XAB6<
1200      opcode, xo, (outs acc:$AT),
1201      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
1202      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
1203      IIC_VecFP, []>,
1204    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1205  def PM#NAME#PN :
1206    MMIRR_XX3Form_XY4_XAB6<
1207      opcode, !or(xo, 0x80), (outs acc:$AT),
1208      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
1209      !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
1210      IIC_VecFP, []>,
1211    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1212  def PM#NAME#NP :
1213    MMIRR_XX3Form_XY4_XAB6<
1214      opcode, !or(xo, 0x40), (outs acc:$AT),
1215      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
1216      !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
1217      IIC_VecFP, []>,
1218    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1219  def PM#NAME#NN :
1220    MMIRR_XX3Form_XY4_XAB6<
1221      opcode, !or(xo, 0xC0), (outs acc:$AT),
1222      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
1223      !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
1224      IIC_VecFP, []>,
1225    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1226  }
1227}
1228
1229// Defines 10 instructions, operand negating, unmasked, masked with 4, 2 bits.
1230// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
1231multiclass ACC_NEG_UM_M42_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
1232                                 string asmbase, string asmstr> {
1233  defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>;
1234  let Predicates = [MMA, PrefixInstrs] in {
1235  def PM#NAME :
1236    MMIRR_XX3Form_X4Y2_XAB6<
1237      opcode, !or(xo, 0x01), (outs acc:$AT),
1238      !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK)),
1239      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),
1240      IIC_VecFP, []>,
1241    RegConstraint<"@earlyclobber $AT">;
1242  def PM#NAME#PP :
1243    MMIRR_XX3Form_X4Y2_XAB6<
1244      opcode, xo, (outs acc:$AT),
1245      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
1246      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
1247      IIC_VecFP, []>,
1248    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1249  def PM#NAME#PN :
1250    MMIRR_XX3Form_X4Y2_XAB6<
1251      opcode, !or(xo, 0x80), (outs acc:$AT),
1252      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
1253      !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
1254      IIC_VecFP, []>,
1255    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1256  def PM#NAME#NP :
1257    MMIRR_XX3Form_X4Y2_XAB6<
1258      opcode, !or(xo, 0x40), (outs acc:$AT),
1259      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
1260      !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
1261      IIC_VecFP, []>,
1262    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1263  def PM#NAME#NN :
1264    MMIRR_XX3Form_X4Y2_XAB6<
1265      opcode, !or(xo, 0xC0), (outs acc:$AT),
1266      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
1267      !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
1268      IIC_VecFP, []>,
1269    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1270  }
1271}
1272
1273// End of class definitions.
1274//-----------------------------------------------------------------------------
1275
1276let Predicates = [MMA] in {
1277  def XXMFACC :
1278    XForm_AT3<31, 0, 177, (outs acc:$ASo), (ins acc:$AS), "xxmfacc $AS",
1279              IIC_VecGeneral,
1280              [(set v512i1:$ASo, (int_ppc_mma_xxmfacc v512i1:$AS))]>,
1281              RegConstraint<"$ASo = $AS">, NoEncode<"$ASo">;
1282  def XXMTACC :
1283    XForm_AT3<31, 1, 177, (outs acc:$AT), (ins acc:$ATi), "xxmtacc $AT",
1284              IIC_VecGeneral,
1285              [(set v512i1:$AT, (int_ppc_mma_xxmtacc v512i1:$ATi))]>,
1286              RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1287  def KILL_PAIR : PPCPostRAExpPseudo<(outs vsrprc:$XTp), (ins vsrprc:$XSp),
1288                                      "#KILL_PAIR", []>,
1289                                      RegConstraint<"$XTp = $XSp">;
1290  def BUILD_UACC : PPCPostRAExpPseudo<(outs acc:$AT), (ins uacc:$AS),
1291                                      "#BUILD_UACC $AT, $AS", []>;
1292  // We define XXSETACCZ as rematerializable to undo CSE of that intrinsic in
1293  // the backend. We avoid CSE here because it generates a copy of the acc
1294  // register and this copy is more expensive than calling the intrinsic again.
1295  let isAsCheapAsAMove = 1, isReMaterializable = 1 in {
1296    def XXSETACCZ :
1297      XForm_AT3<31, 3, 177, (outs acc:$AT), (ins), "xxsetaccz $AT", IIC_VecGeneral,
1298                [(set v512i1:$AT, (int_ppc_mma_xxsetaccz))]>;
1299  }
1300  def XVI8GER4SPP :
1301    XX3Form_AT3_XAB6<59, 99, (outs acc:$AT), (ins acc:$ATi, vsrc:$XA, vsrc:$XB),
1302                     "xvi8ger4spp $AT, $XA, $XB", IIC_VecGeneral, []>,
1303    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1304  let mayStore = 1 in {
1305    def SPILL_ACC: PPCEmitTimePseudo<(outs), (ins acc:$AT, memrix16:$dst),
1306                                     "#SPILL_ACC", []>;
1307    def SPILL_UACC: PPCEmitTimePseudo<(outs), (ins uacc:$AT, memrix16:$dst),
1308                                     "#SPILL_UACC", []>;
1309  }
1310  let mayLoad = 1, hasSideEffects = 0 in {
1311    def RESTORE_ACC: PPCEmitTimePseudo<(outs acc:$AT), (ins memrix16:$src),
1312                                       "#RESTORE_ACC", []>;
1313    def RESTORE_UACC: PPCEmitTimePseudo<(outs uacc:$AT), (ins memrix16:$src),
1314                                       "#RESTORE_UACC", []>;
1315  }
1316}
1317
1318let Predicates = [MMA, PrefixInstrs] in {
1319  def PMXVI8GER4SPP :
1320    MMIRR_XX3Form_XYP4_XAB6<59, 99, (outs acc:$AT),
1321                            (ins acc:$ATi, vsrc:$XA,vsrc:$XB, u4imm:$XMSK,
1322                             u4imm:$YMSK, u4imm:$PMSK),
1323                            "pmxvi8ger4spp $AT, $XA, $XB, $XMSK, $YMSK, $PMSK",
1324                            IIC_VecGeneral, []>,
1325    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1326}
1327
1328// MMA accumulating/non-accumulating instructions.
1329//------------------------------------------------------------------------------
1330
1331// XVBF16GER2, XVBF16GER2PP, XVBF16GER2PN, XVBF16GER2NP, XVBF16GER2NN
1332// PMXVBF16GER2, PMXVBF16GER2PP, PMXVBF16GER2PN, PMXVBF16GER2NP, PMXVBF16GER2NN
1333defm XVBF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 50, (ins vsrc:$XA, vsrc:$XB),
1334                                         "xvbf16ger2", "$AT, $XA, $XB">;
1335
1336// XVI4GER8, XVI4GER8PP, PMXVI4GER8,  PMXVI4GER8PP
1337defm XVI4GER8 : ACC_UM_M844_XOEO<59, 34, (ins vsrc:$XA, vsrc:$XB),
1338                                 "xvi4ger8", "$AT, $XA, $XB">;
1339
1340// XVI8GER4, XVI8GER4PP, PMXVI8GER4, PMXVI8GER4PP
1341defm XVI8GER4 : ACC_UM_M444_XOEO<59, 2, (ins vsrc:$XA, vsrc:$XB),
1342                                 "xvi8ger4", "$AT, $XA, $XB">;
1343
1344// XVI16GER2, XVI16GER2PP, PMXVI16GER2, PMXVI16GER2PP
1345defm XVI16GER2 : ACC_UM_M244_XO46<59, 75, (ins vsrc:$XA, vsrc:$XB),
1346                                  "xvi16ger2", "$AT, $XA, $XB">;
1347
1348// XVI16GER2S, XVI16GER2SPP, PMXVI16GER2S, PMXVI16GER2SPP
1349defm XVI16GER2S : ACC_UM_M244_XOEO<59, 42, (ins vsrc:$XA, vsrc:$XB),
1350                                   "xvi16ger2s", "$AT, $XA, $XB">;
1351
1352// XVF16GER2, XVF16GER2PP, XVF16GER2PN, XVF16GER2NP, XVF16GER2NN
1353// PMXVF16GER2, PMXVF16GER2PP, PMXVF16GER2PN, PMXVF16GER2NP, PMXVF16GER2NN
1354defm XVF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 18, (ins vsrc:$XA, vsrc:$XB),
1355                                        "xvf16ger2", "$AT, $XA, $XB">;
1356
1357// XVF32GER, XVF32GERPP, XVF32GERPN, XVF32GERNP, XVF32GERPP
1358// PMXVF32GER, PMXVF32GERPP, PMXVF32GERPN, PMXVF32GERNP, PMXVF32GERPP
1359defm XVF32GER : ACC_NEG_UM_M44_XOM84C<59, 26, (ins vsrc:$XA, vsrc:$XB),
1360                                      "xvf32ger", "$AT, $XA, $XB">;
1361
1362// XVF64GER, XVF64GERPP, XVF64GERPN, XVF64GERNP, XVF64GERNN
1363// PMXVF64GER, PMXVF64GERPP, PMXVF64GERPN, PMXVF64GERNP, PMXVF64GERNN
1364defm XVF64GER : ACC_NEG_UM_M42_XOM84C<59, 58, (ins vsrpevenrc:$XA, vsrc:$XB),
1365                                      "xvf64ger", "$AT, $XA, $XB">;
1366//------------------------------------------------------------------------------
1367
1368// MMA Intrinsics
1369let Predicates = [MMA] in {
1370  def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)),
1371            (XVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC)>;
1372  def : Pat<(v512i1 (int_ppc_mma_xvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1373            (XVI4GER8PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1374
1375  def : Pat<(v512i1 (int_ppc_mma_xvi8ger4 v16i8:$XA, v16i8:$XB)),
1376            (XVI8GER4 RCCp.AToVSRC, RCCp.BToVSRC)>;
1377  def : Pat<(v512i1 (int_ppc_mma_xvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1378            (XVI8GER4PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1379
1380  def : Pat<(v512i1 (int_ppc_mma_xvi16ger2s v16i8:$XA, v16i8:$XB)),
1381            (XVI16GER2S RCCp.AToVSRC, RCCp.BToVSRC)>;
1382  def : Pat<(v512i1 (int_ppc_mma_xvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1383            (XVI16GER2SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1384
1385  def : Pat<(v512i1 (int_ppc_mma_xvf16ger2 v16i8:$XA, v16i8:$XB)),
1386            (XVF16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>;
1387  def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1388            (XVF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1389  def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1390            (XVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1391  def : Pat<(v512i1 (int_ppc_mma_xvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1392            (XVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1393  def : Pat<(v512i1 (int_ppc_mma_xvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1394            (XVF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1395
1396  def : Pat<(v512i1 (int_ppc_mma_xvf32ger v16i8:$XA, v16i8:$XB)),
1397            (XVF32GER RCCp.AToVSRC, RCCp.BToVSRC)>;
1398  def : Pat<(v512i1 (int_ppc_mma_xvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1399            (XVF32GERPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1400  def : Pat<(v512i1 (int_ppc_mma_xvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1401            (XVF32GERPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1402  def : Pat<(v512i1 (int_ppc_mma_xvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1403            (XVF32GERNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1404  def : Pat<(v512i1 (int_ppc_mma_xvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1405            (XVF32GERNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1406  def : Pat<(v512i1 (int_ppc_mma_xvf64ger v256i1:$XA, v16i8:$XB)),
1407            (XVF64GER $XA, RCCp.BToVSRC)>;
1408  def : Pat<(v512i1 (int_ppc_mma_xvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
1409            (XVF64GERPP $ATi, $XA, RCCp.BToVSRC)>;
1410  def : Pat<(v512i1 (int_ppc_mma_xvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
1411            (XVF64GERPN $ATi, $XA, RCCp.BToVSRC)>;
1412  def : Pat<(v512i1 (int_ppc_mma_xvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
1413            (XVF64GERNP $ATi, $XA, RCCp.BToVSRC)>;
1414  def : Pat<(v512i1 (int_ppc_mma_xvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
1415            (XVF64GERNN $ATi, $XA, RCCp.BToVSRC)>;
1416
1417  def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2 v16i8:$XA, v16i8:$XB)),
1418            (XVBF16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>;
1419  def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1420            (XVBF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1421  def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1422            (XVBF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1423  def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1424            (XVBF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1425  def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1426            (XVBF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1427  def : Pat<(v512i1 (int_ppc_mma_xvi16ger2 v16i8:$XA, v16i8:$XB)),
1428            (XVI16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>;
1429  def : Pat<(v512i1 (int_ppc_mma_xvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1430            (XVI16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1431  def : Pat<(v512i1 (int_ppc_mma_xvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1432            (XVI8GER4SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1433}
1434
1435// MMA Intrinsics
1436let Predicates = [MMA, PrefixInstrs] in {
1437  def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1438                                            Msk4Imm:$YMSK, Msk8Imm:$PMSK)),
1439            (PMXVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1440                        Msk4Imm:$YMSK, Msk8Imm:$PMSK)>;
1441  def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1442                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1443                                              Msk8Imm:$PMSK)),
1444            (PMXVI4GER8PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1445                          Msk4Imm:$YMSK, Msk8Imm:$PMSK)>;
1446
1447  def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1448                                            Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
1449            (PMXVI8GER4 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1450                        Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
1451  def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1452                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1453                                              Msk4Imm:$PMSK)),
1454            (PMXVI8GER4PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1455                          Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
1456
1457  def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2s v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1458                                              Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
1459            (PMXVI16GER2S RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1460                          Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1461  def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1462                                                Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1463                                                Msk2Imm:$PMSK)),
1464            (PMXVI16GER2SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1465                            Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1466  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1467                                             Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
1468            (PMXVF16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1469                         Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1470  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1471                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1472                                               Msk2Imm:$PMSK)),
1473            (PMXVF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1474                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1475  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1476                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1477                                               Msk2Imm:$PMSK)),
1478            (PMXVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1479                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1480  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1481                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1482                                               Msk2Imm:$PMSK)),
1483            (PMXVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1484                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1485  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1486                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1487                                               Msk2Imm:$PMSK)),
1488            (PMXVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1489                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1490  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1491                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1492                                               Msk2Imm:$PMSK)),
1493            (PMXVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1494                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1495  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1496                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1497                                               Msk2Imm:$PMSK)),
1498            (PMXVF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1499                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1500
1501  def : Pat<(v512i1 (int_ppc_mma_pmxvf32ger v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1502                                            Msk4Imm:$YMSK)),
1503            (PMXVF32GER RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1504                        Msk4Imm:$YMSK)>;
1505  def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1506                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
1507            (PMXVF32GERPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1508                          Msk4Imm:$YMSK)>;
1509  def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1510                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
1511            (PMXVF32GERPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1512                          Msk4Imm:$YMSK)>;
1513  def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1514                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
1515            (PMXVF32GERNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1516                          Msk4Imm:$YMSK)>;
1517  def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1518                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
1519            (PMXVF32GERNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1520                          Msk4Imm:$YMSK)>;
1521
1522  def : Pat<(v512i1 (int_ppc_mma_pmxvf64ger v256i1:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1523                                            Msk2Imm:$YMSK)),
1524            (PMXVF64GER $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, Msk2Imm:$YMSK)>;
1525  def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB,
1526                                              Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
1527            (PMXVF64GERPP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
1528                          Msk2Imm:$YMSK)>;
1529  def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB,
1530                                              Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
1531            (PMXVF64GERPN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
1532                          Msk2Imm:$YMSK)>;
1533  def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB,
1534                                              Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
1535            (PMXVF64GERNP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
1536                          Msk2Imm:$YMSK)>;
1537  def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB,
1538                                              Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
1539            (PMXVF64GERNN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
1540                          Msk2Imm:$YMSK)>;
1541
1542  def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1543                                              Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
1544            (PMXVBF16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1545                          Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1546  def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1547                                                Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1548                                                Msk2Imm:$PMSK)),
1549            (PMXVBF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1550                            Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1551  def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1552                                                Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1553                                                Msk2Imm:$PMSK)),
1554            (PMXVBF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1555                            Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1556  def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1557                                                Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1558                                                Msk2Imm:$PMSK)),
1559            (PMXVBF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1560                            Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1561  def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1562                                                Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1563                                                Msk2Imm:$PMSK)),
1564            (PMXVBF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1565                            Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1566  def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1567                                             Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
1568            (PMXVI16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1569                         Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1570  def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1571                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1572                                               Msk2Imm:$PMSK)),
1573            (PMXVI8GER4SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1574                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1575  def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1576                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1577                                               Msk2Imm:$PMSK)),
1578            (PMXVI16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1579                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1580}
1581
1582def Concats {
1583  dag VecsToVecPair0 =
1584    (v256i1 (INSERT_SUBREG
1585      (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1),
1586      $vs1, sub_vsx0));
1587  dag VecsToVecPair1 =
1588    (v256i1 (INSERT_SUBREG
1589      (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),
1590      $vs3, sub_vsx0));
1591  dag VecsToVecQuad =
1592    (BUILD_UACC (INSERT_SUBREG
1593                  (INSERT_SUBREG (v512i1 (IMPLICIT_DEF)),
1594                                 (KILL_PAIR VecsToVecPair0), sub_pair0),
1595                  (KILL_PAIR VecsToVecPair1), sub_pair1));
1596}
1597
1598def Extracts {
1599  dag Pair0 = (v256i1 (EXTRACT_SUBREG $v, sub_pair0));
1600  dag Pair1 = (v256i1 (EXTRACT_SUBREG $v, sub_pair1));
1601  dag Vec0 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx0));
1602  dag Vec1 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx1));
1603  dag Vec2 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx0));
1604  dag Vec3 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx1));
1605}
1606
1607let Predicates = [MMA] in {
1608  def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1609            (XXMTACC Concats.VecsToVecQuad)>;
1610  def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
1611                                              v16i8:$vs3, v16i8:$vs2)),
1612            (XXMTACC Concats.VecsToVecQuad)>;
1613  def : Pat<(v512i1 (PPCxxmfacc v512i1:$AS)), (XXMFACC acc:$AS)>;
1614  def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 0)),
1615            Extracts.Vec0>;
1616  def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 1)),
1617            Extracts.Vec1>;
1618  def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 2)),
1619            Extracts.Vec2>;
1620  def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 3)),
1621            Extracts.Vec3>;
1622}
1623
1624let Predicates = [PairedVectorMemops] in {
1625  def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)),
1626            Concats.VecsToVecPair0>;
1627  def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)),
1628            Concats.VecsToVecPair0>;
1629  def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)),
1630            (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>;
1631  def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)),
1632            (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>;
1633}
1634
1635let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in {
1636  def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp),
1637                                  (ins memrix16:$DQ_RA), "lxvp $XTp, $DQ_RA",
1638                                  IIC_LdStLFD, []>;
1639  def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins memrr:$src),
1640                              "lxvpx $XTp, $src", IIC_LdStLFD,
1641                              []>;
1642}
1643
1644let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
1645  def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp,
1646                                   memrix16:$DQ_RA), "stxvp $XTp, $DQ_RA",
1647                                   IIC_LdStLFD, []>;
1648  def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, memrr:$dst),
1649                               "stxvpx $XTp, $dst", IIC_LdStLFD,
1650                               []>;
1651}
1652
1653let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
1654  defm PLXVP :
1655    8LS_DForm_R_XTp5_SI34_MEM_p<1, 58, (outs vsrprc:$XTp), (ins memri34:$D_RA),
1656                                (ins memri34_pcrel:$D_RA), "plxvp $XTp, $D_RA",
1657                                IIC_LdStLFD>;
1658}
1659
1660let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in {
1661  defm PSTXVP :
1662    8LS_DForm_R_XTp5_SI34_MEM_p<1, 62, (outs), (ins vsrprc:$XTp, memri34:$D_RA),
1663                                (ins vsrprc:$XTp, memri34_pcrel:$D_RA),
1664                                "pstxvp $XTp, $D_RA", IIC_LdStLFD>;
1665}
1666
1667let Predicates = [PairedVectorMemops] in {
1668  // Intrinsics for Paired Vector Loads.
1669  def : Pat<(v256i1 (int_ppc_vsx_lxvp iaddrX16:$src)), (LXVP memrix16:$src)>;
1670  def : Pat<(v256i1 (int_ppc_vsx_lxvp xaddrX16:$src)), (LXVPX xaddrX16:$src)>;
1671  let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1672    def : Pat<(v256i1 (int_ppc_vsx_lxvp iaddrX34:$src)), (PLXVP memri34:$src)>;
1673  }
1674  // Intrinsics for Paired Vector Stores.
1675  def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, iaddrX16:$dst),
1676            (STXVP $XSp, memrix16:$dst)>;
1677  def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, xaddrX16:$dst),
1678            (STXVPX $XSp, xaddrX16:$dst)>;
1679  let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1680    def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, iaddrX34:$dst),
1681              (PSTXVP $XSp, memri34:$dst)>;
1682  }
1683}
1684
1685// TODO: We have an added complexity of 500 here. This is only a temporary
1686// solution to have tablegen consider these patterns first. The way we do
1687// addressing for PowerPC is complex depending on available D form, X form, or
1688// aligned D form loads/stores like DS and DQ forms. The prefixed
1689// instructions in this file also add additional PC Relative loads/stores
1690// and D form loads/stores with 34 bit immediates. It is very difficult to force
1691// instruction selection to consistently pick these first without the current
1692// added complexity. Once pc-relative implementation is complete, a set of
1693// follow-up patches will address this refactoring and the AddedComplexity will
1694// be removed.
1695let Predicates = [PCRelativeMemops], AddedComplexity = 500 in {
1696  // Load i32
1697  def : Pat<(i32 (zextloadi1  (PPCmatpcreladdr pcreladdr:$ga))),
1698            (PLBZpc $ga, 0)>;
1699  def : Pat<(i32 (extloadi1  (PPCmatpcreladdr pcreladdr:$ga))),
1700            (PLBZpc $ga, 0)>;
1701  def : Pat<(i32 (zextloadi8  (PPCmatpcreladdr pcreladdr:$ga))),
1702            (PLBZpc $ga, 0)>;
1703  def : Pat<(i32 (extloadi8   (PPCmatpcreladdr pcreladdr:$ga))),
1704            (PLBZpc $ga, 0)>;
1705  def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
1706            (PLHApc $ga, 0)>;
1707  def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
1708            (PLHZpc $ga, 0)>;
1709  def : Pat<(i32 (extloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
1710            (PLHZpc $ga, 0)>;
1711  def : Pat<(i32 (load (PPCmatpcreladdr pcreladdr:$ga))), (PLWZpc $ga, 0)>;
1712
1713  // Store i32
1714  def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
1715            (PSTBpc $RS, $ga, 0)>;
1716  def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
1717            (PSTHpc $RS, $ga, 0)>;
1718  def : Pat<(store i32:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
1719            (PSTWpc $RS, $ga, 0)>;
1720
1721  // Load i64
1722  def : Pat<(i64 (zextloadi1  (PPCmatpcreladdr pcreladdr:$ga))),
1723            (PLBZ8pc $ga, 0)>;
1724  def : Pat<(i64 (extloadi1  (PPCmatpcreladdr pcreladdr:$ga))),
1725            (PLBZ8pc $ga, 0)>;
1726  def : Pat<(i64 (zextloadi8  (PPCmatpcreladdr pcreladdr:$ga))),
1727            (PLBZ8pc $ga, 0)>;
1728  def : Pat<(i64 (extloadi8   (PPCmatpcreladdr pcreladdr:$ga))),
1729            (PLBZ8pc $ga, 0)>;
1730  def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
1731            (PLHA8pc $ga, 0)>;
1732  def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
1733            (PLHZ8pc $ga, 0)>;
1734  def : Pat<(i64 (extloadi16 (PPCmatpcreladdr pcreladdr:$ga))),
1735            (PLHZ8pc $ga, 0)>;
1736  def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr pcreladdr:$ga))),
1737            (PLWZ8pc $ga, 0)>;
1738  def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr pcreladdr:$ga))),
1739            (PLWA8pc $ga, 0)>;
1740  def : Pat<(i64 (extloadi32 (PPCmatpcreladdr pcreladdr:$ga))),
1741            (PLWZ8pc $ga, 0)>;
1742  def : Pat<(i64 (load (PPCmatpcreladdr pcreladdr:$ga))), (PLDpc $ga, 0)>;
1743
1744  // Store i64
1745  def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
1746            (PSTB8pc $RS, $ga, 0)>;
1747  def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
1748            (PSTH8pc $RS, $ga, 0)>;
1749  def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
1750            (PSTW8pc $RS, $ga, 0)>;
1751  def : Pat<(store i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)),
1752            (PSTDpc $RS, $ga, 0)>;
1753
1754  // Load f32
1755  def : Pat<(f32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLFSpc $addr, 0)>;
1756
1757  // Store f32
1758  def : Pat<(store f32:$FRS, (PPCmatpcreladdr pcreladdr:$ga)),
1759            (PSTFSpc $FRS, $ga, 0)>;
1760
1761  // Load f64
1762  def : Pat<(f64 (extloadf32 (PPCmatpcreladdr pcreladdr:$addr))),
1763            (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>;
1764  def : Pat<(f64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLFDpc $addr, 0)>;
1765
1766  // Store f64
1767  def : Pat<(store f64:$FRS, (PPCmatpcreladdr pcreladdr:$ga)),
1768            (PSTFDpc $FRS, $ga, 0)>;
1769
1770  // Load f128
1771  def : Pat<(f128 (load (PPCmatpcreladdr pcreladdr:$addr))),
1772            (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>;
1773
1774  // Store f128
1775  def : Pat<(store f128:$XS, (PPCmatpcreladdr pcreladdr:$ga)),
1776            (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>;
1777
1778  // Load v4i32
1779  def : Pat<(v4i32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
1780
1781  // Store v4i32
1782  def : Pat<(store v4i32:$XS, (PPCmatpcreladdr pcreladdr:$ga)),
1783            (PSTXVpc $XS, $ga, 0)>;
1784
1785  // Load v2i64
1786  def : Pat<(v2i64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
1787
1788  // Store v2i64
1789  def : Pat<(store v2i64:$XS, (PPCmatpcreladdr pcreladdr:$ga)),
1790            (PSTXVpc $XS, $ga, 0)>;
1791
1792  // Load v4f32
1793  def : Pat<(v4f32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
1794
1795  // Store v4f32
1796  def : Pat<(store v4f32:$XS, (PPCmatpcreladdr pcreladdr:$ga)),
1797            (PSTXVpc $XS, $ga, 0)>;
1798
1799  // Load v2f64
1800  def : Pat<(v2f64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
1801
1802  // Store v2f64
1803  def : Pat<(store v2f64:$XS, (PPCmatpcreladdr pcreladdr:$ga)),
1804            (PSTXVpc $XS, $ga, 0)>;
1805
1806  // Atomic Load
1807  def : Pat<(atomic_load_8 (PPCmatpcreladdr pcreladdr:$ga)),
1808            (PLBZpc $ga, 0)>;
1809  def : Pat<(atomic_load_16 (PPCmatpcreladdr pcreladdr:$ga)),
1810            (PLHZpc $ga, 0)>;
1811  def : Pat<(atomic_load_32 (PPCmatpcreladdr pcreladdr:$ga)),
1812            (PLWZpc $ga, 0)>;
1813  def : Pat<(atomic_load_64 (PPCmatpcreladdr pcreladdr:$ga)),
1814            (PLDpc $ga, 0)>;
1815
1816  // Atomic Store
1817  def : Pat<(atomic_store_8 (PPCmatpcreladdr pcreladdr:$ga), i32:$RS),
1818            (PSTBpc $RS, $ga, 0)>;
1819  def : Pat<(atomic_store_16 (PPCmatpcreladdr pcreladdr:$ga), i32:$RS),
1820            (PSTHpc $RS, $ga, 0)>;
1821  def : Pat<(atomic_store_32 (PPCmatpcreladdr pcreladdr:$ga), i32:$RS),
1822            (PSTWpc $RS, $ga, 0)>;
1823  def : Pat<(atomic_store_8 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS),
1824            (PSTB8pc $RS, $ga, 0)>;
1825  def : Pat<(atomic_store_16 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS),
1826            (PSTH8pc $RS, $ga, 0)>;
1827  def : Pat<(atomic_store_32 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS),
1828            (PSTW8pc $RS, $ga, 0)>;
1829  def : Pat<(atomic_store_64 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS),
1830            (PSTDpc $RS, $ga, 0)>;
1831
1832  // Special Cases For PPCstore_scal_int_from_vsr
1833  def : Pat<(PPCstore_scal_int_from_vsr
1834              (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)),
1835              (PPCmatpcreladdr pcreladdr:$dst), 8),
1836            (PSTXSDpc (XSCVDPSXDS f64:$src), $dst, 0)>;
1837  def : Pat<(PPCstore_scal_int_from_vsr
1838              (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)),
1839              (PPCmatpcreladdr pcreladdr:$dst), 8),
1840            (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), $dst, 0)>;
1841
1842  def : Pat<(PPCstore_scal_int_from_vsr
1843              (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)),
1844              (PPCmatpcreladdr pcreladdr:$dst), 8),
1845            (PSTXSDpc (XSCVDPUXDS f64:$src), $dst, 0)>;
1846  def : Pat<(PPCstore_scal_int_from_vsr
1847              (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)),
1848              (PPCmatpcreladdr pcreladdr:$dst), 8),
1849            (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>;
1850
1851  // If the PPCmatpcreladdr node is not caught by any other pattern it should be
1852  // caught here and turned into a paddi instruction to materialize the address.
1853  def : Pat<(PPCmatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
1854  // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize
1855  // tls global address with paddi instruction.
1856  def : Pat<(PPCtlsdynamatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
1857  // PPCtlslocalexecmataddr node is used for TLS local exec models to
1858  // materialize tls global address with paddi instruction.
1859  def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)),
1860            (PADDI8 $in, $addr)>;
1861}
1862
1863let Predicates = [PrefixInstrs] in {
1864  def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
1865                                     (ins i32imm:$IMM32),
1866                                     "xxspltiw $XT, $IMM32", IIC_VecGeneral,
1867                                     []>;
1868  def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
1869                                      (ins i32imm:$IMM32),
1870                                      "xxspltidp $XT, $IMM32", IIC_VecGeneral,
1871                                      [(set v2f64:$XT,
1872                                            (PPCxxspltidp i32:$IMM32))]>;
1873  def XXPERMX :
1874    8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1875                            vsrc:$XC, u3imm:$UIM),
1876                            "xxpermx $XT, $XA, $XB, $XC, $UIM",
1877                            IIC_VecPerm, []>;
1878  def XXBLENDVB :
1879    8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1880                       vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",
1881                       IIC_VecGeneral, []>;
1882  def XXBLENDVH :
1883    8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1884                       vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",
1885                       IIC_VecGeneral, []>;
1886  def XXBLENDVW :
1887    8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1888                       vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",
1889                       IIC_VecGeneral, []>;
1890  def XXBLENDVD :
1891    8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1892                       vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC",
1893                       IIC_VecGeneral, []>;
1894}
1895
1896// XXSPLI32DX needs extra flags to make sure the compiler does not attempt
1897// to spill part of the instruction when the values are similar.
1898let isReMaterializable = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in {
1899  def XXSPLTI32DX :
1900      8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),
1901                             (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32),
1902                             "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral,
1903                             [(set v2i64:$XT,
1904                                   (PPCxxsplti32dx v2i64:$XTi, i32:$IX,
1905                                                   i32:$IMM32))]>,
1906                             RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
1907}
1908
1909let Predicates = [IsISA3_1] in {
1910  def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI),
1911                            "setbc $RT, $BI", IIC_IntCompare, []>;
1912  def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI),
1913                             "setbcr $RT, $BI", IIC_IntCompare, []>;
1914  def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI),
1915                             "setnbc $RT, $BI", IIC_IntCompare, []>;
1916  def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI),
1917                              "setnbcr $RT, $BI", IIC_IntCompare, []>;
1918
1919  let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1920    def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI),
1921                               "setbc $RT, $BI", IIC_IntCompare, []>;
1922    def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI),
1923                                "setbcr $RT, $BI", IIC_IntCompare, []>;
1924    def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI),
1925                                "setnbc $RT, $BI", IIC_IntCompare, []>;
1926    def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI),
1927                                 "setnbcr $RT, $BI", IIC_IntCompare, []>;
1928  }
1929
1930  def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
1931                                (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
1932                                "vsldbi $VRT, $VRA, $VRB, $SH",
1933                                IIC_VecGeneral,
1934                                [(set v16i8:$VRT,
1935                                      (int_ppc_altivec_vsldbi v16i8:$VRA,
1936                                                              v16i8:$VRB,
1937                                                              i32:$SH))]>;
1938  def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
1939                                (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
1940                                "vsrdbi $VRT, $VRA, $VRB, $SH",
1941                                IIC_VecGeneral,
1942                                [(set v16i8:$VRT,
1943                                      (int_ppc_altivec_vsrdbi v16i8:$VRA,
1944                                                              v16i8:$VRB,
1945                                                              i32:$SH))]>;
1946  defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB),
1947                                 "vstribr", "$vT, $vB", IIC_VecGeneral,
1948				 [(set v16i8:$vT,
1949                                       (int_ppc_altivec_vstribr v16i8:$vB))]>;
1950  defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$vT), (ins vrrc:$vB),
1951                                 "vstribl", "$vT, $vB", IIC_VecGeneral,
1952                                 [(set v16i8:$vT,
1953                                       (int_ppc_altivec_vstribl v16i8:$vB))]>;
1954  defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$vT), (ins vrrc:$vB),
1955                                 "vstrihr", "$vT, $vB", IIC_VecGeneral,
1956                                 [(set v8i16:$vT,
1957                                       (int_ppc_altivec_vstrihr v8i16:$vB))]>;
1958  defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$vT), (ins vrrc:$vB),
1959                                 "vstrihl", "$vT, $vB", IIC_VecGeneral,
1960                                 [(set v8i16:$vT,
1961                                       (int_ppc_altivec_vstrihl v8i16:$vB))]>;
1962  def VINSW :
1963    VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB),
1964             "vinsw $vD, $rB, $UIM", IIC_VecGeneral,
1965             [(set v4i32:$vD,
1966                   (int_ppc_altivec_vinsw v4i32:$vDi, i32:$rB, timm:$UIM))]>,
1967             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1968  def VINSD :
1969    VXForm_1<463, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB),
1970             "vinsd $vD, $rB, $UIM", IIC_VecGeneral,
1971             [(set v2i64:$vD,
1972                   (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB, timm:$UIM))]>,
1973             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1974  def VINSBVLX :
1975    VXForm_VTB5_RA5_ins<15, "vinsbvlx",
1976                        [(set v16i8:$vD,
1977                              (int_ppc_altivec_vinsbvlx v16i8:$vDi, i32:$rA,
1978                                                        v16i8:$vB))]>;
1979  def VINSBVRX :
1980    VXForm_VTB5_RA5_ins<271, "vinsbvrx",
1981                        [(set v16i8:$vD,
1982                              (int_ppc_altivec_vinsbvrx v16i8:$vDi, i32:$rA,
1983                                                        v16i8:$vB))]>;
1984  def VINSHVLX :
1985    VXForm_VTB5_RA5_ins<79, "vinshvlx",
1986                        [(set v8i16:$vD,
1987                              (int_ppc_altivec_vinshvlx v8i16:$vDi, i32:$rA,
1988                                                        v8i16:$vB))]>;
1989  def VINSHVRX :
1990    VXForm_VTB5_RA5_ins<335, "vinshvrx",
1991                        [(set v8i16:$vD,
1992                              (int_ppc_altivec_vinshvrx v8i16:$vDi, i32:$rA,
1993                                                        v8i16:$vB))]>;
1994  def VINSWVLX :
1995    VXForm_VTB5_RA5_ins<143, "vinswvlx",
1996                        [(set v4i32:$vD,
1997                              (int_ppc_altivec_vinswvlx v4i32:$vDi, i32:$rA,
1998                                                        v4i32:$vB))]>;
1999  def VINSWVRX :
2000    VXForm_VTB5_RA5_ins<399, "vinswvrx",
2001                        [(set v4i32:$vD,
2002                              (int_ppc_altivec_vinswvrx v4i32:$vDi, i32:$rA,
2003                                                        v4i32:$vB))]>;
2004  def VINSBLX :
2005    VXForm_VRT5_RAB5_ins<527, "vinsblx",
2006                         [(set v16i8:$vD,
2007                               (int_ppc_altivec_vinsblx v16i8:$vDi, i32:$rA,
2008                                                        i32:$rB))]>;
2009  def VINSBRX :
2010    VXForm_VRT5_RAB5_ins<783, "vinsbrx",
2011                         [(set v16i8:$vD,
2012                               (int_ppc_altivec_vinsbrx v16i8:$vDi, i32:$rA,
2013                                                        i32:$rB))]>;
2014  def VINSHLX :
2015    VXForm_VRT5_RAB5_ins<591, "vinshlx",
2016                         [(set v8i16:$vD,
2017                               (int_ppc_altivec_vinshlx v8i16:$vDi, i32:$rA,
2018                                                        i32:$rB))]>;
2019  def VINSHRX :
2020    VXForm_VRT5_RAB5_ins<847, "vinshrx",
2021                         [(set v8i16:$vD,
2022                               (int_ppc_altivec_vinshrx v8i16:$vDi, i32:$rA,
2023                                                        i32:$rB))]>;
2024  def VINSWLX :
2025    VXForm_VRT5_RAB5_ins<655, "vinswlx",
2026                         [(set v4i32:$vD,
2027                               (int_ppc_altivec_vinswlx v4i32:$vDi, i32:$rA,
2028                                                        i32:$rB))]>;
2029  def VINSWRX :
2030    VXForm_VRT5_RAB5_ins<911, "vinswrx",
2031                         [(set v4i32:$vD,
2032                               (int_ppc_altivec_vinswrx v4i32:$vDi, i32:$rA,
2033                                                        i32:$rB))]>;
2034  def VINSDLX :
2035    VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
2036             "vinsdlx $vD, $rA, $rB", IIC_VecGeneral,
2037              [(set v2i64:$vD,
2038                    (int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>,
2039              RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
2040  def VINSDRX :
2041    VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
2042             "vinsdrx $vD, $rA, $rB", IIC_VecGeneral,
2043              [(set v2i64:$vD,
2044                    (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>,
2045              RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
2046  def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB),
2047                                      "vextractbm $rD, $vB", IIC_VecGeneral,
2048                                      [(set i32:$rD,
2049                                      (int_ppc_altivec_vextractbm v16i8:$vB))]>;
2050  def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB),
2051                                      "vextracthm $rD, $vB", IIC_VecGeneral,
2052                                      [(set i32:$rD,
2053                                      (int_ppc_altivec_vextracthm v8i16:$vB))]>;
2054  def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB),
2055                                      "vextractwm $rD, $vB", IIC_VecGeneral,
2056                                      [(set i32:$rD,
2057                                      (int_ppc_altivec_vextractwm v4i32:$vB))]>;
2058  def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB),
2059                                      "vextractdm $rD, $vB", IIC_VecGeneral,
2060                                      [(set i32:$rD,
2061                                      (int_ppc_altivec_vextractdm v2i64:$vB))]>;
2062  def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB),
2063                                      "vextractqm $rD, $vB", IIC_VecGeneral,
2064                                      [(set i32:$rD,
2065                                      (int_ppc_altivec_vextractqm v1i128:$vB))]>;
2066  def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB),
2067                                     "vexpandbm $vD, $vB", IIC_VecGeneral,
2068                                     [(set v16i8:$vD, (int_ppc_altivec_vexpandbm
2069                                           v16i8:$vB))]>;
2070  def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB),
2071                                     "vexpandhm $vD, $vB", IIC_VecGeneral,
2072                                     [(set v8i16:$vD, (int_ppc_altivec_vexpandhm
2073                                           v8i16:$vB))]>;
2074  def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB),
2075                                     "vexpandwm $vD, $vB", IIC_VecGeneral,
2076                                     [(set v4i32:$vD, (int_ppc_altivec_vexpandwm
2077                                           v4i32:$vB))]>;
2078  def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB),
2079                                     "vexpanddm $vD, $vB", IIC_VecGeneral,
2080                                     [(set v2i64:$vD, (int_ppc_altivec_vexpanddm
2081                                           v2i64:$vB))]>;
2082  def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB),
2083                                     "vexpandqm $vD, $vB", IIC_VecGeneral,
2084                                     [(set v1i128:$vD, (int_ppc_altivec_vexpandqm
2085                                           v1i128:$vB))]>;
2086  def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB),
2087                                   "mtvsrbm $vD, $rB", IIC_VecGeneral,
2088                                   [(set v16i8:$vD,
2089                                         (int_ppc_altivec_mtvsrbm i64:$rB))]>;
2090  def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$vD), (ins g8rc:$rB),
2091                                   "mtvsrhm $vD, $rB", IIC_VecGeneral,
2092                                   [(set v8i16:$vD,
2093                                         (int_ppc_altivec_mtvsrhm i64:$rB))]>;
2094  def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$vD), (ins g8rc:$rB),
2095                                   "mtvsrwm $vD, $rB", IIC_VecGeneral,
2096                                   [(set v4i32:$vD,
2097                                         (int_ppc_altivec_mtvsrwm i64:$rB))]>;
2098  def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$vD), (ins g8rc:$rB),
2099                                   "mtvsrdm $vD, $rB", IIC_VecGeneral,
2100                                   [(set v2i64:$vD,
2101                                         (int_ppc_altivec_mtvsrdm i64:$rB))]>;
2102  def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$vD), (ins g8rc:$rB),
2103                                   "mtvsrqm $vD, $rB", IIC_VecGeneral,
2104                                   [(set v1i128:$vD,
2105                                         (int_ppc_altivec_mtvsrqm i64:$rB))]>;
2106  def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u16imm64:$D),
2107                        "mtvsrbmi $vD, $D", IIC_VecGeneral,
2108                        [(set v16i8:$vD,
2109                              (int_ppc_altivec_mtvsrbm imm:$D))]>;
2110  def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD),
2111                                  (ins vrrc:$vB, u1imm:$MP),
2112                                  "vcntmbb $rD, $vB, $MP", IIC_VecGeneral,
2113                                  [(set i64:$rD, (int_ppc_altivec_vcntmbb
2114                                        v16i8:$vB, timm:$MP))]>;
2115  def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$rD),
2116                                  (ins vrrc:$vB, u1imm:$MP),
2117                                  "vcntmbh $rD, $vB, $MP", IIC_VecGeneral,
2118                                  [(set i64:$rD, (int_ppc_altivec_vcntmbh
2119                                        v8i16:$vB, timm:$MP))]>;
2120  def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$rD),
2121                                  (ins vrrc:$vB, u1imm:$MP),
2122                                  "vcntmbw $rD, $vB, $MP", IIC_VecGeneral,
2123                                  [(set i64:$rD, (int_ppc_altivec_vcntmbw
2124                                        v4i32:$vB, timm:$MP))]>;
2125  def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$rD),
2126                                  (ins vrrc:$vB, u1imm:$MP),
2127                                  "vcntmbd $rD, $vB, $MP", IIC_VecGeneral,
2128                                  [(set i64:$rD, (int_ppc_altivec_vcntmbd
2129                                        v2i64:$vB, timm:$MP))]>;
2130  def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$vD),
2131                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2132                             "vextdubvlx $vD, $vA, $vB, $rC",
2133                             IIC_VecGeneral,
2134                             [(set v2i64:$vD,
2135                                   (int_ppc_altivec_vextdubvlx v16i8:$vA,
2136                                                               v16i8:$vB,
2137                                                               i32:$rC))]>;
2138  def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$vD),
2139                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2140                             "vextdubvrx $vD, $vA, $vB, $rC",
2141                             IIC_VecGeneral,
2142                             [(set v2i64:$vD,
2143                                   (int_ppc_altivec_vextdubvrx v16i8:$vA,
2144                                                               v16i8:$vB,
2145                                                               i32:$rC))]>;
2146  def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$vD),
2147                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2148                             "vextduhvlx $vD, $vA, $vB, $rC",
2149                             IIC_VecGeneral,
2150                             [(set v2i64:$vD,
2151                                   (int_ppc_altivec_vextduhvlx v8i16:$vA,
2152                                                               v8i16:$vB,
2153                                                               i32:$rC))]>;
2154  def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$vD),
2155                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2156                             "vextduhvrx $vD, $vA, $vB, $rC",
2157                             IIC_VecGeneral,
2158                             [(set v2i64:$vD,
2159                                   (int_ppc_altivec_vextduhvrx v8i16:$vA,
2160                                                               v8i16:$vB,
2161                                                               i32:$rC))]>;
2162  def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$vD),
2163                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2164                             "vextduwvlx $vD, $vA, $vB, $rC",
2165                             IIC_VecGeneral,
2166                             [(set v2i64:$vD,
2167                                   (int_ppc_altivec_vextduwvlx v4i32:$vA,
2168                                                               v4i32:$vB,
2169                                                               i32:$rC))]>;
2170  def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$vD),
2171                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2172                             "vextduwvrx $vD, $vA, $vB, $rC",
2173                             IIC_VecGeneral,
2174                             [(set v2i64:$vD,
2175                                   (int_ppc_altivec_vextduwvrx v4i32:$vA,
2176                                                               v4i32:$vB,
2177                                                               i32:$rC))]>;
2178  def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$vD),
2179                            (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2180                            "vextddvlx $vD, $vA, $vB, $rC",
2181                            IIC_VecGeneral,
2182                            [(set v2i64:$vD,
2183                                  (int_ppc_altivec_vextddvlx v2i64:$vA,
2184                                                             v2i64:$vB,
2185                                                             i32:$rC))]>;
2186  def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$vD),
2187                            (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2188                            "vextddvrx $vD, $vA, $vB, $rC",
2189                            IIC_VecGeneral,
2190                            [(set v2i64:$vD,
2191                                  (int_ppc_altivec_vextddvrx v2i64:$vA,
2192                                                             v2i64:$vB,
2193                                                             i32:$rC))]>;
2194   def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2195                         "vpdepd $vD, $vA, $vB", IIC_VecGeneral,
2196                         [(set v2i64:$vD,
2197                         (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>;
2198   def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2199                         "vpextd $vD, $vA, $vB", IIC_VecGeneral,
2200                         [(set v2i64:$vD,
2201                         (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>;
2202   def PDEPD : XForm_6<31, 156, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
2203                       "pdepd $rA, $rS, $rB", IIC_IntGeneral,
2204                       [(set i64:$rA, (int_ppc_pdepd i64:$rS, i64:$rB))]>;
2205   def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
2206                       "pextd $rA, $rS, $rB", IIC_IntGeneral,
2207                       [(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>;
2208   def VCFUGED : VXForm_1<1357, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2209                          "vcfuged $vD, $vA, $vB", IIC_VecGeneral,
2210                          [(set v2i64:$vD,
2211                          (int_ppc_altivec_vcfuged v2i64:$vA, v2i64:$vB))]>;
2212   def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$rD), (ins vrrc:$vB, u3imm:$N),
2213                                "vgnb $rD, $vB, $N", IIC_VecGeneral,
2214                                [(set i64:$rD,
2215                                (int_ppc_altivec_vgnb v1i128:$vB, timm:$N))]>;
2216   def CFUGED : XForm_6<31, 220, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
2217                        "cfuged $rA, $rS, $rB", IIC_IntGeneral,
2218                        [(set i64:$rA, (int_ppc_cfuged i64:$rS, i64:$rB))]>;
2219   def XXEVAL :
2220     8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
2221                            vsrc:$XC, u8imm:$IMM),
2222                            "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral,
2223                            [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA,
2224                                  v2i64:$XB, v2i64:$XC, timm:$IMM))]>;
2225   def VCLZDM : VXForm_1<1924, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2226                         "vclzdm $vD, $vA, $vB", IIC_VecGeneral,
2227                         [(set v2i64:$vD,
2228                         (int_ppc_altivec_vclzdm v2i64:$vA, v2i64:$vB))]>;
2229   def VCTZDM : VXForm_1<1988, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2230                         "vctzdm $vD, $vA, $vB", IIC_VecGeneral,
2231                         [(set v2i64:$vD,
2232                         (int_ppc_altivec_vctzdm v2i64:$vA, v2i64:$vB))]>;
2233   def CNTLZDM : XForm_6<31, 59, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
2234                         "cntlzdm $rA, $rS, $rB", IIC_IntGeneral,
2235                         [(set i64:$rA,
2236                         (int_ppc_cntlzdm i64:$rS, i64:$rB))]>;
2237   def CNTTZDM : XForm_6<31, 571, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
2238                         "cnttzdm $rA, $rS, $rB", IIC_IntGeneral,
2239                         [(set i64:$rA,
2240                         (int_ppc_cnttzdm i64:$rS, i64:$rB))]>;
2241   def XXGENPCVBM :
2242     XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
2243                        "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
2244   def XXGENPCVHM :
2245     XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
2246                        "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
2247   def XXGENPCVWM :
2248     XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
2249                        "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
2250   def XXGENPCVDM :
2251     XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
2252                        "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
2253   def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
2254                         "vclrlb $vD, $vA, $rB", IIC_VecGeneral,
2255                         [(set v16i8:$vD,
2256                               (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>;
2257   def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
2258                         "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
2259                         [(set v16i8:$vD,
2260                               (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
2261  def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2262                        "vmulld $vD, $vA, $vB", IIC_VecGeneral,
2263                        [(set v2i64:$vD, (mul v2i64:$vA, v2i64:$vB))]>;
2264  def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2265                         "vmulhsw $vD, $vA, $vB", IIC_VecGeneral,
2266                         [(set v4i32:$vD, (mulhs v4i32:$vA, v4i32:$vB))]>;
2267  def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2268                         "vmulhuw $vD, $vA, $vB", IIC_VecGeneral,
2269                         [(set v4i32:$vD, (mulhu v4i32:$vA, v4i32:$vB))]>;
2270  def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2271                         "vmulhsd $vD, $vA, $vB", IIC_VecGeneral,
2272                         [(set v2i64:$vD, (mulhs v2i64:$vA, v2i64:$vB))]>;
2273  def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2274                         "vmulhud $vD, $vA, $vB", IIC_VecGeneral,
2275                         [(set v2i64:$vD, (mulhu v2i64:$vA, v2i64:$vB))]>;
2276  def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2277                        "vmodsw $vD, $vA, $vB", IIC_VecGeneral,
2278                        [(set v4i32:$vD, (srem v4i32:$vA, v4i32:$vB))]>;
2279  def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2280                        "vmoduw $vD, $vA, $vB", IIC_VecGeneral,
2281                        [(set v4i32:$vD, (urem v4i32:$vA, v4i32:$vB))]>;
2282  def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2283                        "vmodsd $vD, $vA, $vB", IIC_VecGeneral,
2284                        [(set v2i64:$vD, (srem v2i64:$vA, v2i64:$vB))]>;
2285  def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2286                        "vmodud $vD, $vA, $vB", IIC_VecGeneral,
2287                        [(set v2i64:$vD, (urem v2i64:$vA, v2i64:$vB))]>;
2288  def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2289                        "vdivsw $vD, $vA, $vB", IIC_VecGeneral,
2290                        [(set v4i32:$vD, (sdiv v4i32:$vA, v4i32:$vB))]>;
2291  def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2292                        "vdivuw $vD, $vA, $vB", IIC_VecGeneral,
2293                        [(set v4i32:$vD, (udiv v4i32:$vA, v4i32:$vB))]>;
2294  def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2295                        "vdivsd $vD, $vA, $vB", IIC_VecGeneral,
2296                        [(set v2i64:$vD, (sdiv v2i64:$vA, v2i64:$vB))]>;
2297  def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2298                        "vdivud $vD, $vA, $vB", IIC_VecGeneral,
2299                        [(set v2i64:$vD, (udiv v2i64:$vA, v2i64:$vB))]>;
2300  def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2301                         "vdivesw $vD, $vA, $vB", IIC_VecGeneral,
2302                         [(set v4i32:$vD, (int_ppc_altivec_vdivesw v4i32:$vA,
2303                               v4i32:$vB))]>;
2304  def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2305                         "vdiveuw $vD, $vA, $vB", IIC_VecGeneral,
2306                         [(set v4i32:$vD, (int_ppc_altivec_vdiveuw v4i32:$vA,
2307                               v4i32:$vB))]>;
2308  def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2309                         "vdivesd $vD, $vA, $vB", IIC_VecGeneral,
2310                         [(set v2i64:$vD, (int_ppc_altivec_vdivesd v2i64:$vA,
2311                               v2i64:$vB))]>;
2312  def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2313                         "vdiveud $vD, $vA, $vB", IIC_VecGeneral,
2314                         [(set v2i64:$vD, (int_ppc_altivec_vdiveud v2i64:$vA,
2315                               v2i64:$vB))]>;
2316  def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
2317                                    "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
2318
2319  // The XFormMemOp flag for the following 8 instructions is set on
2320  // the instruction format.
2321  let mayLoad = 1, mayStore = 0 in {
2322    def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>;
2323    def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>;
2324    def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>;
2325    def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>;
2326  }
2327
2328  let mayLoad = 0, mayStore = 1 in {
2329    def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>;
2330    def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>;
2331    def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>;
2332    def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>;
2333  }
2334
2335  def VMULESD : VXForm_1<968, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2336                         "vmulesd $vD, $vA, $vB", IIC_VecGeneral,
2337                         [(set v1i128:$vD, (int_ppc_altivec_vmulesd v2i64:$vA,
2338                               v2i64:$vB))]>;
2339  def VMULEUD : VXForm_1<712, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2340                         "vmuleud $vD, $vA, $vB", IIC_VecGeneral,
2341                         [(set v1i128:$vD, (int_ppc_altivec_vmuleud v2i64:$vA,
2342                               v2i64:$vB))]>;
2343  def VMULOSD : VXForm_1<456, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2344                         "vmulosd $vD, $vA, $vB", IIC_VecGeneral,
2345                         [(set v1i128:$vD, (int_ppc_altivec_vmulosd v2i64:$vA,
2346                               v2i64:$vB))]>;
2347  def VMULOUD : VXForm_1<200, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2348                         "vmuloud $vD, $vA, $vB", IIC_VecGeneral,
2349                         [(set v1i128:$vD, (int_ppc_altivec_vmuloud v2i64:$vA,
2350                               v2i64:$vB))]>;
2351  def VMSUMCUD : VAForm_1a<23, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
2352                           "vmsumcud $vD, $vA, $vB, $vC", IIC_VecGeneral,
2353                           [(set v1i128:$vD, (int_ppc_altivec_vmsumcud
2354                                 v2i64:$vA, v2i64:$vB, v1i128:$vC))]>;
2355  def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2356                        "vdivsq $vD, $vA, $vB", IIC_VecGeneral,
2357                        [(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>;
2358  def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2359                        "vdivuq $vD, $vA, $vB", IIC_VecGeneral,
2360                        [(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>;
2361  def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2362                         "vdivesq $vD, $vA, $vB", IIC_VecGeneral,
2363                         [(set v1i128:$vD, (int_ppc_altivec_vdivesq v1i128:$vA,
2364			       v1i128:$vB))]>;
2365  def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2366                         "vdiveuq $vD, $vA, $vB", IIC_VecGeneral,
2367                         [(set v1i128:$vD, (int_ppc_altivec_vdiveuq v1i128:$vA,
2368			       v1i128:$vB))]>;
2369  def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>;
2370  def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>;
2371  def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>;
2372  def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $vD, $vA, $vB" , v1i128>;
2373  def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>;
2374  def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>;
2375  def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2376                        "vmodsq $vD, $vA, $vB", IIC_VecGeneral,
2377                        [(set v1i128:$vD, (srem v1i128:$vA, v1i128:$vB))]>;
2378  def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2379                        "vmoduq $vD, $vA, $vB", IIC_VecGeneral,
2380                        [(set v1i128:$vD, (urem v1i128:$vA, v1i128:$vB))]>;
2381  def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$vD), (ins vrrc:$vB),
2382                               "vextsd2q $vD, $vB", IIC_VecGeneral,
2383                               [(set v1i128:$vD, (int_ppc_altivec_vextsd2q v2i64:$vB))]>;
2384  def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
2385                               "vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>;
2386  def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
2387                               "vcmpsq $BF, $vA, $vB", IIC_VecGeneral, []>;
2388  def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm",
2389                               [(set v1i128:$vD,
2390                                   (int_ppc_altivec_vrlqnm v1i128:$vA,
2391                                                           v1i128:$vB))]>;
2392  def VRLQMI : VXForm_1<69, (outs vrrc:$vD),
2393                        (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
2394                        "vrlqmi $vD, $vA, $vB", IIC_VecFP,
2395                        [(set v1i128:$vD,
2396                          (int_ppc_altivec_vrlqmi v1i128:$vA, v1i128:$vB,
2397                                                  v1i128:$vDi))]>,
2398                        RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
2399  def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;
2400  def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
2401  def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
2402  def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
2403  def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
2404  def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
2405  def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
2406  def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
2407}
2408
2409let Predicates = [IsISA3_1, HasVSX] in {
2410  def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>;
2411  def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;
2412}
2413
2414// Multiclass defining patterns for Set Boolean Extension Reverse Instructions.
2415// This is analogous to the CRNotPat multiclass but specifically for Power10
2416// and newer subtargets since the extended forms use Set Boolean instructions.
2417// The first two anonymous patterns defined are actually a duplicate of those
2418// in CRNotPat, but it is preferable to define both multiclasses as complete
2419// ones rather than pulling that small common section out.
2420multiclass P10ReverseSetBool<dag pattern, dag result> {
2421  def : Pat<pattern, (crnot result)>;
2422  def : Pat<(not pattern), result>;
2423
2424  def : Pat<(i32 (zext pattern)),
2425            (SETBCR result)>;
2426  def : Pat<(i64 (zext pattern)),
2427            (SETBCR8 result)>;
2428
2429  def : Pat<(i32 (sext pattern)),
2430            (SETNBCR result)>;
2431  def : Pat<(i64 (sext pattern)),
2432            (SETNBCR8 result)>;
2433
2434  def : Pat<(i32 (anyext pattern)),
2435            (SETBCR result)>;
2436  def : Pat<(i64 (anyext pattern)),
2437            (SETBCR8 result)>;
2438}
2439
2440multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy,
2441                               ImmLeaf SExtTy, I Cmpi, I Cmpli,
2442                               I Cmp, I Cmpl> {
2443  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
2444                           (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>;
2445  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
2446                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>;
2447  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
2448                           (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>;
2449  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
2450                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>;
2451  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
2452                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>;
2453
2454  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)),
2455                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>;
2456  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)),
2457                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>;
2458  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
2459                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>;
2460  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)),
2461                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>;
2462  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)),
2463                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>;
2464  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)),
2465                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>;
2466}
2467
2468multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, I FCmp> {
2469  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
2470                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
2471  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
2472                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
2473  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
2474                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
2475  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
2476                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
2477  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
2478                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
2479  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
2480                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
2481  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
2482                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;
2483}
2484
2485let Predicates = [IsISA3_1] in {
2486  def : Pat<(i32 (zext i1:$in)),
2487            (SETBC $in)>;
2488  def : Pat<(i64 (zext i1:$in)),
2489            (SETBC8 $in)>;
2490  def : Pat<(i32 (sext i1:$in)),
2491            (SETNBC $in)>;
2492  def : Pat<(i64 (sext i1:$in)),
2493            (SETNBC8 $in)>;
2494  def : Pat<(i32 (anyext i1:$in)),
2495            (SETBC $in)>;
2496  def : Pat<(i64 (anyext i1:$in)),
2497            (SETBC8 $in)>;
2498
2499  // Instantiation of the set boolean reverse patterns for 32-bit integers.
2500  defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16,
2501                             CMPWI, CMPLWI, CMPW, CMPLW>;
2502  defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2503                           (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2504                                           (LO16 imm:$imm)), sub_eq)>;
2505
2506  // Instantiation of the set boolean reverse patterns for 64-bit integers.
2507  defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16,
2508                             CMPDI, CMPLDI, CMPD, CMPLD>;
2509  defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2510                           (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2511                                           (LO16 imm:$imm)), sub_eq)>;
2512}
2513
2514// Instantiation of the set boolean reverse patterns for f32, f64, f128.
2515let Predicates = [IsISA3_1, HasFPU] in {
2516  defm : FSetP10RevSetBool<setcc, f32, FCMPUS>;
2517  defm : FSetP10RevSetBool<setcc, f64, FCMPUD>;
2518  defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>;
2519}
2520
2521//---------------------------- Anonymous Patterns ----------------------------//
2522let Predicates = [IsISA3_1] in {
2523  // Exploit the vector multiply high instructions using intrinsics.
2524  def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)),
2525            (v4i32 (VMULHSW $vA, $vB))>;
2526  def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)),
2527            (v4i32 (VMULHUW $vA, $vB))>;
2528  def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)),
2529            (v2i64 (VMULHSD $vA, $vB))>;
2530  def : Pat<(v2i64 (int_ppc_altivec_vmulhud v2i64:$vA, v2i64:$vB)),
2531            (v2i64 (VMULHUD $vA, $vB))>;
2532  def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),
2533            (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>;
2534  def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)),
2535            (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>;
2536  def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)),
2537            (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
2538  def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
2539            (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
2540  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)),
2541            (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
2542  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
2543            (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
2544
2545  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)),
2546             (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>;
2547  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)),
2548             (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>;
2549  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 32)),
2550             (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>;
2551  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 64)),
2552             (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>;
2553
2554  def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)),
2555            (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>;
2556
2557  def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)),
2558             (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>;
2559}
2560
2561let Predicates = [IsISA3_1, HasVSX] in {
2562  def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)),
2563            (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>;
2564  def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)),
2565            (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>;
2566}
2567
2568let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in {
2569  // Store element 0 of a VSX register to memory
2570  def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), ForceXForm:$dst),
2571            (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), ForceXForm:$dst)>;
2572  def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), ForceXForm:$dst),
2573            (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), ForceXForm:$dst)>;
2574  def : Pat<(store (i32 (extractelt v4i32:$src, 0)), ForceXForm:$dst),
2575            (STXVRWX $src, ForceXForm:$dst)>;
2576  def : Pat<(store (f32 (extractelt v4f32:$src, 0)), ForceXForm:$dst),
2577            (STXVRWX $src, ForceXForm:$dst)>;
2578  def : Pat<(store (i64 (extractelt v2i64:$src, 0)), ForceXForm:$dst),
2579            (STXVRDX $src, ForceXForm:$dst)>;
2580  def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst),
2581            (STXVRDX $src, ForceXForm:$dst)>;
2582  // Load element 0 of a VSX register to memory
2583  def : Pat<(v8i16 (scalar_to_vector (i32 (extloadi16 ForceXForm:$src)))),
2584            (v8i16 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VSRC))>;
2585  def : Pat<(v16i8 (scalar_to_vector (i32 (extloadi8 ForceXForm:$src)))),
2586            (v16i8 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VSRC))>;
2587 }
2588
2589// FIXME: The swap is overkill when the shift amount is a constant.
2590// We should just fix the constant in the DAG.
2591let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
2592  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
2593            (v1i128 (VSLQ v1i128:$VRA,
2594                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2595                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2596  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
2597            (v1i128 (VSLQ v1i128:$VRA,
2598                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2599                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2600  def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
2601            (v1i128 (VSRQ v1i128:$VRA,
2602                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2603                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2604  def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
2605            (v1i128 (VSRQ v1i128:$VRA,
2606                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2607                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2608  def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
2609            (v1i128 (VSRAQ v1i128:$VRA,
2610                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2611                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2612  def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
2613            (v1i128 (VSRAQ v1i128:$VRA,
2614                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2615                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2616}
2617
2618class xxevalPattern <dag pattern, bits<8> imm> :
2619  Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
2620
2621let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
2622 def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
2623                                i32immNonAllOneNonZero:$A,
2624                                i32immNonAllOneNonZero:$A,
2625                                i32immNonAllOneNonZero:$A)),
2626           (v4i32 (XXSPLTIW imm:$A))>;
2627 def : Pat<(f32 nzFPImmAsi32:$A),
2628           (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
2629                             VSFRC)>;
2630 def : Pat<(f64 nzFPImmAsi32:$A),
2631           (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
2632                             VSFRC)>;
2633
2634// To replace constant pool with XXSPLTI32DX for scalars.
2635def : Pat<(f32 nzFPImmAsi64:$A),
2636          (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX(IMPLICIT_DEF), 0,
2637                                        (getFPAs64BitIntHi $A)),
2638                                        1, (getFPAs64BitIntLo $A)),
2639                            VSSRC)>;
2640
2641def : Pat<(f64 nzFPImmAsi64:$A),
2642          (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX (IMPLICIT_DEF), 0,
2643                                        (getFPAs64BitIntHi $A)),
2644                                        1, (getFPAs64BitIntLo $A)),
2645                            VSFRC)>;
2646
2647  // Anonymous patterns for XXEVAL
2648  // AND
2649  // and(A, B, C)
2650  def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;
2651  // and(A, xor(B, C))
2652  def : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>;
2653  // and(A, or(B, C))
2654  def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>;
2655  // and(A, nor(B, C))
2656  def : xxevalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>;
2657  // and(A, eqv(B, C))
2658  def : xxevalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>;
2659  // and(A, nand(B, C))
2660  def : xxevalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>;
2661
2662  // NAND
2663  // nand(A, B, C)
2664  def : xxevalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))),
2665                       !sub(255, 1)>;
2666  // nand(A, xor(B, C))
2667  def : xxevalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))),
2668                       !sub(255, 6)>;
2669  // nand(A, or(B, C))
2670  def : xxevalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))),
2671                       !sub(255, 7)>;
2672  // nand(A, nor(B, C))
2673  def : xxevalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)),
2674                       !sub(255, 8)>;
2675  // nand(A, eqv(B, C))
2676  def : xxevalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)),
2677                       !sub(255, 9)>;
2678  // nand(A, nand(B, C))
2679  def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)),
2680                       !sub(255, 14)>;
2681}
2682
2683let Predicates = [PrefixInstrs] in {
2684  def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>;
2685  def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>;
2686  def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)),
2687            (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC),
2688                                       (COPY_TO_REGCLASS $B, VSRC),
2689                                       (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>;
2690  def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)),
2691            (COPY_TO_REGCLASS
2692                   (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC),
2693                              (COPY_TO_REGCLASS $B, VSRC),
2694                              (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;
2695  def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)),
2696            (COPY_TO_REGCLASS
2697                   (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC),
2698                              (COPY_TO_REGCLASS $B, VSRC),
2699                              (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;
2700  def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C),
2701            (XXBLENDVW $A, $B, $C)>;
2702  def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C),
2703            (XXBLENDVD $A, $B, $C)>;
2704}
2705
2706def InsertEltShift {
2707  dag Sub32Left0 = (EXTRACT_SUBREG $rB, sub_32);
2708  dag Sub32Left1 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 1, 0, 30);
2709  dag Sub32Left2 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 2, 0, 29);
2710  dag Left3 = (RLWINM8 $rB, 3, 0, 28);
2711}
2712
2713let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in {
2714  // Indexed vector insert element
2715  def : Pat<(v16i8 (PPCvecinsertelt v16i8:$vDi, i32:$rA, i64:$rB)),
2716            (VINSBRX $vDi, InsertEltShift.Sub32Left0, $rA)>;
2717  def : Pat<(v8i16 (PPCvecinsertelt v8i16:$vDi, i32:$rA, i64:$rB)),
2718            (VINSHRX $vDi, InsertEltShift.Sub32Left1, $rA)>;
2719  def : Pat<(v4i32 (PPCvecinsertelt v4i32:$vDi, i32:$rA, i64:$rB)),
2720            (VINSWRX $vDi, InsertEltShift.Sub32Left2, $rA)>;
2721  def : Pat<(v2i64 (PPCvecinsertelt v2i64:$vDi, i64:$rA, i64:$rB)),
2722            (VINSDRX $vDi, InsertEltShift.Left3, $rA)>;
2723
2724  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi,  f32:$A, i64:$rB)),
2725            (VINSWRX $vDi, InsertEltShift.Sub32Left2, Bitcast.FltToInt)>;
2726  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddr:$rA)), i64:$rB)),
2727            (VINSWRX $vDi, InsertEltShift.Sub32Left2, (LWZ memri:$rA))>;
2728  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)), i64:$rB)),
2729            (VINSWRX $vDi, InsertEltShift.Sub32Left2, (PLWZ memri34:$rA))>;
2730  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load xaddr:$rA)), i64:$rB)),
2731            (VINSWRX $vDi, InsertEltShift.Sub32Left2, (LWZX memrr:$rA))>;
2732
2733  def : Pat<(v2f64 (PPCvecinsertelt v2f64:$vDi,  f64:$A, i64:$rB)),
2734            (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
2735  def : Pat<(v2f64 (PPCvecinsertelt v2f64:$vDi, (f64 (load iaddrX4:$rA)), i64:$rB)),
2736            (VINSDRX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;
2737  def : Pat<(v2f64 (PPCvecinsertelt v2f64:$vDi, (f64 (load iaddrX34:$rA)), i64:$rB)),
2738            (VINSDRX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;
2739  def : Pat<(v2f64 (PPCvecinsertelt v2f64:$vDi, (f64 (load xaddrX4:$rA)), i64:$rB)),
2740            (VINSDRX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;
2741
2742  // Immediate vector insert element
2743  foreach i = [0, 1, 2, 3] in {
2744    def : Pat<(v4i32 (PPCvecinsertelt v4i32:$vDi, i32:$rA, (i64 i))),
2745              (VINSW $vDi, !mul(!sub(3, i), 4), $rA)>;
2746    def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddr:$rA)), (i64 i))),
2747              (VINSW $vDi, !mul(!sub(3, i), 4), (LWZ memri:$rA))>;
2748    def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)), (i64 i))),
2749              (VINSW $vDi, !mul(!sub(3, i), 4), (PLWZ memri34:$rA))>;
2750    def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load xaddr:$rA)), (i64 i))),
2751              (VINSW $vDi, !mul(!sub(3, i), 4), (LWZX memrr:$rA))>;
2752  }
2753  foreach i = [0, 1] in
2754    def : Pat<(v2i64 (PPCvecinsertelt v2i64:$vDi, i64:$rA, (i64 i))),
2755              (VINSD $vDi, !mul(!sub(1, i), 8), $rA)>;
2756}
2757
2758let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in {
2759  // Indexed vector insert element
2760  def : Pat<(v16i8 (PPCvecinsertelt v16i8:$vDi, i32:$rA, i32:$rB)),
2761            (VINSBLX $vDi, $rB, $rA)>;
2762  def : Pat<(v8i16 (PPCvecinsertelt v8i16:$vDi, i32:$rA, i32:$rB)),
2763            (VINSHLX $vDi, $rB, $rA)>;
2764  def : Pat<(v4i32 (PPCvecinsertelt v4i32:$vDi, i32:$rA, i32:$rB)),
2765            (VINSWLX $vDi, $rB, $rA)>;
2766
2767  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi,  f32:$A, i32:$rB)),
2768            (VINSWLX $vDi, $rB, Bitcast.FltToInt)>;
2769  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddr:$rA)),
2770                                    i32:$rB)),
2771            (VINSWLX $vDi, $rB, (LWZ memri:$rA))>;
2772  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)),
2773                                    i32:$rB)),
2774            (VINSWLX $vDi, $rB, (PLWZ memri34:$rA))>;
2775  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load xaddr:$rA)),
2776                                    i32:$rB)),
2777            (VINSWLX $vDi, $rB, (LWZX memrr:$rA))>;
2778
2779  // Immediate vector insert element
2780  foreach i = [0, 1, 2, 3] in {
2781    def : Pat<(v4i32 (PPCvecinsertelt v4i32:$vDi, i32:$rA, (i32 i))),
2782              (VINSW $vDi, !mul(i, 4), $rA)>;
2783    def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddr:$rA)),
2784                                     (i32 i))),
2785              (VINSW $vDi, !mul(i, 4), (LWZ memri:$rA))>;
2786    def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)),
2787                                     (i32 i))),
2788              (VINSW $vDi, !mul(i, 4), (PLWZ memri34:$rA))>;
2789    def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load xaddr:$rA)),
2790                                     (i32 i))),
2791              (VINSW $vDi, !mul(i, 4), (LWZX memrr:$rA))>;
2792  }
2793}
2794
2795let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in {
2796  // Indexed vector insert element
2797  def : Pat<(v16i8 (PPCvecinsertelt v16i8:$vDi, i32:$rA, i64:$rB)),
2798            (VINSBLX $vDi, InsertEltShift.Sub32Left0, $rA)>;
2799  def : Pat<(v8i16 (PPCvecinsertelt v8i16:$vDi, i32:$rA, i64:$rB)),
2800            (VINSHLX $vDi, InsertEltShift.Sub32Left1, $rA)>;
2801  def : Pat<(v4i32 (PPCvecinsertelt v4i32:$vDi, i32:$rA, i64:$rB)),
2802            (VINSWLX $vDi, InsertEltShift.Sub32Left2, $rA)>;
2803  def : Pat<(v2i64 (PPCvecinsertelt v2i64:$vDi, i64:$rA, i64:$rB)),
2804            (VINSDLX $vDi, InsertEltShift.Left3, $rA)>;
2805
2806  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi,  f32:$A, i64:$rB)),
2807            (VINSWLX $vDi, InsertEltShift.Sub32Left2, Bitcast.FltToInt)>;
2808  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddr:$rA)), i64:$rB)),
2809            (VINSWLX $vDi, InsertEltShift.Sub32Left2, (LWZ memri:$rA))>;
2810  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)), i64:$rB)),
2811            (VINSWLX $vDi, InsertEltShift.Sub32Left2, (PLWZ memri34:$rA))>;
2812  def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load xaddr:$rA)), i64:$rB)),
2813            (VINSWLX $vDi, InsertEltShift.Sub32Left2, (LWZX memrr:$rA))>;
2814
2815  def : Pat<(v2f64 (PPCvecinsertelt v2f64:$vDi,  f64:$A, i64:$rB)),
2816            (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
2817  def : Pat<(v2f64 (PPCvecinsertelt v2f64:$vDi, (f64 (load iaddrX4:$rA)), i64:$rB)),
2818            (VINSDLX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;
2819  def : Pat<(v2f64 (PPCvecinsertelt v2f64:$vDi, (f64 (load iaddrX34:$rA)), i64:$rB)),
2820            (VINSDLX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;
2821  def : Pat<(v2f64 (PPCvecinsertelt v2f64:$vDi, (f64 (load xaddrX4:$rA)), i64:$rB)),
2822            (VINSDLX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;
2823
2824  // Immediate vector insert element
2825  foreach i = [0, 1, 2, 3] in {
2826    def : Pat<(v4i32 (PPCvecinsertelt v4i32:$vDi, i32:$rA, (i64 i))),
2827              (VINSW $vDi, !mul(i, 4), $rA)>;
2828    def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddr:$rA)), (i64 i))),
2829              (VINSW $vDi, !mul(i, 4), (LWZ memri:$rA))>;
2830    def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)), (i64 i))),
2831              (VINSW $vDi, !mul(i, 4), (PLWZ memri34:$rA))>;
2832    def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load xaddr:$rA)), (i64 i))),
2833              (VINSW $vDi, !mul(i, 4), (LWZX memrr:$rA))>;
2834  }
2835  foreach i = [0, 1] in
2836    def : Pat<(v2i64 (PPCvecinsertelt v2i64:$vDi, i64:$rA, (i64 i))),
2837              (VINSD $vDi, !mul(i, 8), $rA)>;
2838}
2839