xref: /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (revision 82d56013d7b633d116a93943de88e08335357a7c) 
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MCTargetDesc/PPCMCExpr.h"
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "PPCTargetStreamer.h"
12 #include "TargetInfo/PowerPCTargetInfo.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCParser/MCAsmLexer.h"
20 #include "llvm/MC/MCParser/MCAsmParser.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbolELF.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 
30 using namespace llvm;
31 
32 DEFINE_PPC_REGCLASSES;
33 
34 // Evaluate an expression containing condition register
35 // or condition register field symbols.  Returns positive
36 // value on success, or -1 on error.
37 static int64_t
EvaluateCRExpr(const MCExpr * E)38 EvaluateCRExpr(const MCExpr *E) {
39   switch (E->getKind()) {
40   case MCExpr::Target:
41     return -1;
42 
43   case MCExpr::Constant: {
44     int64_t Res = cast<MCConstantExpr>(E)->getValue();
45     return Res < 0 ? -1 : Res;
46   }
47 
48   case MCExpr::SymbolRef: {
49     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
50     StringRef Name = SRE->getSymbol().getName();
51 
52     if (Name == "lt") return 0;
53     if (Name == "gt") return 1;
54     if (Name == "eq") return 2;
55     if (Name == "so") return 3;
56     if (Name == "un") return 3;
57 
58     if (Name == "cr0") return 0;
59     if (Name == "cr1") return 1;
60     if (Name == "cr2") return 2;
61     if (Name == "cr3") return 3;
62     if (Name == "cr4") return 4;
63     if (Name == "cr5") return 5;
64     if (Name == "cr6") return 6;
65     if (Name == "cr7") return 7;
66 
67     return -1;
68   }
69 
70   case MCExpr::Unary:
71     return -1;
72 
73   case MCExpr::Binary: {
74     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
75     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
76     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
77     int64_t Res;
78 
79     if (LHSVal < 0 || RHSVal < 0)
80       return -1;
81 
82     switch (BE->getOpcode()) {
83     default: return -1;
84     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
85     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
86     }
87 
88     return Res < 0 ? -1 : Res;
89   }
90   }
91 
92   llvm_unreachable("Invalid expression kind!");
93 }
94 
95 namespace {
96 
97 struct PPCOperand;
98 
99 class PPCAsmParser : public MCTargetAsmParser {
100   bool IsPPC64;
101 
Warning(SMLoc L,const Twine & Msg)102   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
103 
isPPC64() const104   bool isPPC64() const { return IsPPC64; }
105 
106   bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal);
107 
108   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
109   OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
110                                         SMLoc &EndLoc) override;
111 
112   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
113                                         PPCMCExpr::VariantKind &Variant);
114   const MCExpr *FixupVariantKind(const MCExpr *E);
115   bool ParseExpression(const MCExpr *&EVal);
116 
117   bool ParseOperand(OperandVector &Operands);
118 
119   bool ParseDirectiveWord(unsigned Size, AsmToken ID);
120   bool ParseDirectiveTC(unsigned Size, AsmToken ID);
121   bool ParseDirectiveMachine(SMLoc L);
122   bool ParseDirectiveAbiVersion(SMLoc L);
123   bool ParseDirectiveLocalEntry(SMLoc L);
124 
125   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
126                                OperandVector &Operands, MCStreamer &Out,
127                                uint64_t &ErrorInfo,
128                                bool MatchingInlineAsm) override;
129 
130   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
131 
132   /// @name Auto-generated Match Functions
133   /// {
134 
135 #define GET_ASSEMBLER_HEADER
136 #include "PPCGenAsmMatcher.inc"
137 
138   /// }
139 
140 
141 public:
PPCAsmParser(const MCSubtargetInfo & STI,MCAsmParser &,const MCInstrInfo & MII,const MCTargetOptions & Options)142   PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
143                const MCInstrInfo &MII, const MCTargetOptions &Options)
144     : MCTargetAsmParser(Options, STI, MII) {
145     // Check for 64-bit vs. 32-bit pointer mode.
146     const Triple &TheTriple = STI.getTargetTriple();
147     IsPPC64 = TheTriple.isPPC64();
148     // Initialize the set of available features.
149     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
150   }
151 
152   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
153                         SMLoc NameLoc, OperandVector &Operands) override;
154 
155   bool ParseDirective(AsmToken DirectiveID) override;
156 
157   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
158                                       unsigned Kind) override;
159 
160   const MCExpr *applyModifierToExpr(const MCExpr *E,
161                                     MCSymbolRefExpr::VariantKind,
162                                     MCContext &Ctx) override;
163 };
164 
165 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
166 /// instruction.
167 struct PPCOperand : public MCParsedAsmOperand {
168   enum KindTy {
169     Token,
170     Immediate,
171     ContextImmediate,
172     Expression,
173     TLSRegister
174   } Kind;
175 
176   SMLoc StartLoc, EndLoc;
177   bool IsPPC64;
178 
179   struct TokOp {
180     const char *Data;
181     unsigned Length;
182   };
183 
184   struct ImmOp {
185     int64_t Val;
186   };
187 
188   struct ExprOp {
189     const MCExpr *Val;
190     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
191   };
192 
193   struct TLSRegOp {
194     const MCSymbolRefExpr *Sym;
195   };
196 
197   union {
198     struct TokOp Tok;
199     struct ImmOp Imm;
200     struct ExprOp Expr;
201     struct TLSRegOp TLSReg;
202   };
203 
PPCOperand__anoncdd30e2e0111::PPCOperand204   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
205 public:
PPCOperand__anoncdd30e2e0111::PPCOperand206   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
207     Kind = o.Kind;
208     StartLoc = o.StartLoc;
209     EndLoc = o.EndLoc;
210     IsPPC64 = o.IsPPC64;
211     switch (Kind) {
212     case Token:
213       Tok = o.Tok;
214       break;
215     case Immediate:
216     case ContextImmediate:
217       Imm = o.Imm;
218       break;
219     case Expression:
220       Expr = o.Expr;
221       break;
222     case TLSRegister:
223       TLSReg = o.TLSReg;
224       break;
225     }
226   }
227 
228   // Disable use of sized deallocation due to overallocation of PPCOperand
229   // objects in CreateTokenWithStringCopy.
operator delete__anoncdd30e2e0111::PPCOperand230   void operator delete(void *p) { ::operator delete(p); }
231 
232   /// getStartLoc - Get the location of the first token of this operand.
getStartLoc__anoncdd30e2e0111::PPCOperand233   SMLoc getStartLoc() const override { return StartLoc; }
234 
235   /// getEndLoc - Get the location of the last token of this operand.
getEndLoc__anoncdd30e2e0111::PPCOperand236   SMLoc getEndLoc() const override { return EndLoc; }
237 
238   /// getLocRange - Get the range between the first and last token of this
239   /// operand.
getLocRange__anoncdd30e2e0111::PPCOperand240   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
241 
242   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
isPPC64__anoncdd30e2e0111::PPCOperand243   bool isPPC64() const { return IsPPC64; }
244 
getImm__anoncdd30e2e0111::PPCOperand245   int64_t getImm() const {
246     assert(Kind == Immediate && "Invalid access!");
247     return Imm.Val;
248   }
getImmS16Context__anoncdd30e2e0111::PPCOperand249   int64_t getImmS16Context() const {
250     assert((Kind == Immediate || Kind == ContextImmediate) &&
251            "Invalid access!");
252     if (Kind == Immediate)
253       return Imm.Val;
254     return static_cast<int16_t>(Imm.Val);
255   }
getImmU16Context__anoncdd30e2e0111::PPCOperand256   int64_t getImmU16Context() const {
257     assert((Kind == Immediate || Kind == ContextImmediate) &&
258            "Invalid access!");
259     return Imm.Val;
260   }
261 
getExpr__anoncdd30e2e0111::PPCOperand262   const MCExpr *getExpr() const {
263     assert(Kind == Expression && "Invalid access!");
264     return Expr.Val;
265   }
266 
getExprCRVal__anoncdd30e2e0111::PPCOperand267   int64_t getExprCRVal() const {
268     assert(Kind == Expression && "Invalid access!");
269     return Expr.CRVal;
270   }
271 
getTLSReg__anoncdd30e2e0111::PPCOperand272   const MCExpr *getTLSReg() const {
273     assert(Kind == TLSRegister && "Invalid access!");
274     return TLSReg.Sym;
275   }
276 
getReg__anoncdd30e2e0111::PPCOperand277   unsigned getReg() const override {
278     assert(isRegNumber() && "Invalid access!");
279     return (unsigned) Imm.Val;
280   }
281 
getVSReg__anoncdd30e2e0111::PPCOperand282   unsigned getVSReg() const {
283     assert(isVSRegNumber() && "Invalid access!");
284     return (unsigned) Imm.Val;
285   }
286 
getACCReg__anoncdd30e2e0111::PPCOperand287   unsigned getACCReg() const {
288     assert(isACCRegNumber() && "Invalid access!");
289     return (unsigned) Imm.Val;
290   }
291 
getVSRpEvenReg__anoncdd30e2e0111::PPCOperand292   unsigned getVSRpEvenReg() const {
293     assert(isVSRpEvenRegNumber() && "Invalid access!");
294     return (unsigned) Imm.Val >> 1;
295   }
296 
getCCReg__anoncdd30e2e0111::PPCOperand297   unsigned getCCReg() const {
298     assert(isCCRegNumber() && "Invalid access!");
299     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
300   }
301 
getCRBit__anoncdd30e2e0111::PPCOperand302   unsigned getCRBit() const {
303     assert(isCRBitNumber() && "Invalid access!");
304     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
305   }
306 
getCRBitMask__anoncdd30e2e0111::PPCOperand307   unsigned getCRBitMask() const {
308     assert(isCRBitMask() && "Invalid access!");
309     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
310   }
311 
isToken__anoncdd30e2e0111::PPCOperand312   bool isToken() const override { return Kind == Token; }
isImm__anoncdd30e2e0111::PPCOperand313   bool isImm() const override {
314     return Kind == Immediate || Kind == Expression;
315   }
isU1Imm__anoncdd30e2e0111::PPCOperand316   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
isU2Imm__anoncdd30e2e0111::PPCOperand317   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
isU3Imm__anoncdd30e2e0111::PPCOperand318   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
isU4Imm__anoncdd30e2e0111::PPCOperand319   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
isU5Imm__anoncdd30e2e0111::PPCOperand320   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
isS5Imm__anoncdd30e2e0111::PPCOperand321   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
isU6Imm__anoncdd30e2e0111::PPCOperand322   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
isU6ImmX2__anoncdd30e2e0111::PPCOperand323   bool isU6ImmX2() const { return Kind == Immediate &&
324                                   isUInt<6>(getImm()) &&
325                                   (getImm() & 1) == 0; }
isU7Imm__anoncdd30e2e0111::PPCOperand326   bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
isU7ImmX4__anoncdd30e2e0111::PPCOperand327   bool isU7ImmX4() const { return Kind == Immediate &&
328                                   isUInt<7>(getImm()) &&
329                                   (getImm() & 3) == 0; }
isU8Imm__anoncdd30e2e0111::PPCOperand330   bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
isU8ImmX8__anoncdd30e2e0111::PPCOperand331   bool isU8ImmX8() const { return Kind == Immediate &&
332                                   isUInt<8>(getImm()) &&
333                                   (getImm() & 7) == 0; }
334 
isU10Imm__anoncdd30e2e0111::PPCOperand335   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
isU12Imm__anoncdd30e2e0111::PPCOperand336   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
isU16Imm__anoncdd30e2e0111::PPCOperand337   bool isU16Imm() const {
338     switch (Kind) {
339       case Expression:
340         return true;
341       case Immediate:
342       case ContextImmediate:
343         return isUInt<16>(getImmU16Context());
344       default:
345         return false;
346     }
347   }
isS16Imm__anoncdd30e2e0111::PPCOperand348   bool isS16Imm() const {
349     switch (Kind) {
350       case Expression:
351         return true;
352       case Immediate:
353       case ContextImmediate:
354         return isInt<16>(getImmS16Context());
355       default:
356         return false;
357     }
358   }
isS16ImmX4__anoncdd30e2e0111::PPCOperand359   bool isS16ImmX4() const { return Kind == Expression ||
360                                    (Kind == Immediate && isInt<16>(getImm()) &&
361                                     (getImm() & 3) == 0); }
362 
isHashImmX8__anoncdd30e2e0111::PPCOperand363   bool isHashImmX8() const {
364     // The Hash Imm form is used for instructions that check or store a hash.
365     // These instructions have a small immediate range that spans between
366     // -8 and -512.
367     return (Kind == Immediate && getImm() <= -8 && getImm() >= -512 &&
368             (getImm() & 7) == 0);
369   }
370 
isS16ImmX16__anoncdd30e2e0111::PPCOperand371   bool isS16ImmX16() const { return Kind == Expression ||
372                                     (Kind == Immediate && isInt<16>(getImm()) &&
373                                      (getImm() & 15) == 0); }
isS34ImmX16__anoncdd30e2e0111::PPCOperand374   bool isS34ImmX16() const {
375     return Kind == Expression ||
376            (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0);
377   }
isS34Imm__anoncdd30e2e0111::PPCOperand378   bool isS34Imm() const {
379     // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
380     // ContextImmediate is needed.
381     return Kind == Expression || (Kind == Immediate && isInt<34>(getImm()));
382   }
383 
isS17Imm__anoncdd30e2e0111::PPCOperand384   bool isS17Imm() const {
385     switch (Kind) {
386       case Expression:
387         return true;
388       case Immediate:
389       case ContextImmediate:
390         return isInt<17>(getImmS16Context());
391       default:
392         return false;
393     }
394   }
isTLSReg__anoncdd30e2e0111::PPCOperand395   bool isTLSReg() const { return Kind == TLSRegister; }
isDirectBr__anoncdd30e2e0111::PPCOperand396   bool isDirectBr() const {
397     if (Kind == Expression)
398       return true;
399     if (Kind != Immediate)
400       return false;
401     // Operand must be 64-bit aligned, signed 27-bit immediate.
402     if ((getImm() & 3) != 0)
403       return false;
404     if (isInt<26>(getImm()))
405       return true;
406     if (!IsPPC64) {
407       // In 32-bit mode, large 32-bit quantities wrap around.
408       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
409         return true;
410     }
411     return false;
412   }
isCondBr__anoncdd30e2e0111::PPCOperand413   bool isCondBr() const { return Kind == Expression ||
414                                  (Kind == Immediate && isInt<16>(getImm()) &&
415                                   (getImm() & 3) == 0); }
isImmZero__anoncdd30e2e0111::PPCOperand416   bool isImmZero() const { return Kind == Immediate && getImm() == 0; }
isRegNumber__anoncdd30e2e0111::PPCOperand417   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
isACCRegNumber__anoncdd30e2e0111::PPCOperand418   bool isACCRegNumber() const {
419     return Kind == Immediate && isUInt<3>(getImm());
420   }
isVSRpEvenRegNumber__anoncdd30e2e0111::PPCOperand421   bool isVSRpEvenRegNumber() const {
422     return Kind == Immediate && isUInt<6>(getImm()) && ((getImm() & 1) == 0);
423   }
isVSRegNumber__anoncdd30e2e0111::PPCOperand424   bool isVSRegNumber() const {
425     return Kind == Immediate && isUInt<6>(getImm());
426   }
isCCRegNumber__anoncdd30e2e0111::PPCOperand427   bool isCCRegNumber() const { return (Kind == Expression
428                                        && isUInt<3>(getExprCRVal())) ||
429                                       (Kind == Immediate
430                                        && isUInt<3>(getImm())); }
isCRBitNumber__anoncdd30e2e0111::PPCOperand431   bool isCRBitNumber() const { return (Kind == Expression
432                                        && isUInt<5>(getExprCRVal())) ||
433                                       (Kind == Immediate
434                                        && isUInt<5>(getImm())); }
isCRBitMask__anoncdd30e2e0111::PPCOperand435   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
436                                     isPowerOf2_32(getImm()); }
isATBitsAsHint__anoncdd30e2e0111::PPCOperand437   bool isATBitsAsHint() const { return false; }
isMem__anoncdd30e2e0111::PPCOperand438   bool isMem() const override { return false; }
isReg__anoncdd30e2e0111::PPCOperand439   bool isReg() const override { return false; }
440 
addRegOperands__anoncdd30e2e0111::PPCOperand441   void addRegOperands(MCInst &Inst, unsigned N) const {
442     llvm_unreachable("addRegOperands");
443   }
444 
addRegGPRCOperands__anoncdd30e2e0111::PPCOperand445   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
446     assert(N == 1 && "Invalid number of operands!");
447     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
448   }
449 
addRegGPRCNoR0Operands__anoncdd30e2e0111::PPCOperand450   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
451     assert(N == 1 && "Invalid number of operands!");
452     Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
453   }
454 
addRegG8RCOperands__anoncdd30e2e0111::PPCOperand455   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
456     assert(N == 1 && "Invalid number of operands!");
457     Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
458   }
459 
addRegG8RCNoX0Operands__anoncdd30e2e0111::PPCOperand460   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
461     assert(N == 1 && "Invalid number of operands!");
462     Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
463   }
464 
addRegGxRCOperands__anoncdd30e2e0111::PPCOperand465   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
466     if (isPPC64())
467       addRegG8RCOperands(Inst, N);
468     else
469       addRegGPRCOperands(Inst, N);
470   }
471 
addRegGxRCNoR0Operands__anoncdd30e2e0111::PPCOperand472   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
473     if (isPPC64())
474       addRegG8RCNoX0Operands(Inst, N);
475     else
476       addRegGPRCNoR0Operands(Inst, N);
477   }
478 
addRegF4RCOperands__anoncdd30e2e0111::PPCOperand479   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
480     assert(N == 1 && "Invalid number of operands!");
481     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
482   }
483 
addRegF8RCOperands__anoncdd30e2e0111::PPCOperand484   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
485     assert(N == 1 && "Invalid number of operands!");
486     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
487   }
488 
addRegVFRCOperands__anoncdd30e2e0111::PPCOperand489   void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
490     assert(N == 1 && "Invalid number of operands!");
491     Inst.addOperand(MCOperand::createReg(VFRegs[getReg()]));
492   }
493 
addRegVRRCOperands__anoncdd30e2e0111::PPCOperand494   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
495     assert(N == 1 && "Invalid number of operands!");
496     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
497   }
498 
addRegVSRCOperands__anoncdd30e2e0111::PPCOperand499   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
500     assert(N == 1 && "Invalid number of operands!");
501     Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
502   }
503 
addRegVSFRCOperands__anoncdd30e2e0111::PPCOperand504   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
505     assert(N == 1 && "Invalid number of operands!");
506     Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
507   }
508 
addRegVSSRCOperands__anoncdd30e2e0111::PPCOperand509   void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
510     assert(N == 1 && "Invalid number of operands!");
511     Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
512   }
513 
addRegSPE4RCOperands__anoncdd30e2e0111::PPCOperand514   void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const {
515     assert(N == 1 && "Invalid number of operands!");
516     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
517   }
518 
addRegSPERCOperands__anoncdd30e2e0111::PPCOperand519   void addRegSPERCOperands(MCInst &Inst, unsigned N) const {
520     assert(N == 1 && "Invalid number of operands!");
521     Inst.addOperand(MCOperand::createReg(SPERegs[getReg()]));
522   }
523 
addRegACCRCOperands__anoncdd30e2e0111::PPCOperand524   void addRegACCRCOperands(MCInst &Inst, unsigned N) const {
525     assert(N == 1 && "Invalid number of operands!");
526     Inst.addOperand(MCOperand::createReg(ACCRegs[getACCReg()]));
527   }
528 
addRegVSRpRCOperands__anoncdd30e2e0111::PPCOperand529   void addRegVSRpRCOperands(MCInst &Inst, unsigned N) const {
530     assert(N == 1 && "Invalid number of operands!");
531     Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()]));
532   }
533 
addRegVSRpEvenRCOperands__anoncdd30e2e0111::PPCOperand534   void addRegVSRpEvenRCOperands(MCInst &Inst, unsigned N) const {
535     assert(N == 1 && "Invalid number of operands!");
536     Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()]));
537   }
538 
addRegCRBITRCOperands__anoncdd30e2e0111::PPCOperand539   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
540     assert(N == 1 && "Invalid number of operands!");
541     Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
542   }
543 
addRegCRRCOperands__anoncdd30e2e0111::PPCOperand544   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
545     assert(N == 1 && "Invalid number of operands!");
546     Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
547   }
548 
addCRBitMaskOperands__anoncdd30e2e0111::PPCOperand549   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
550     assert(N == 1 && "Invalid number of operands!");
551     Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
552   }
553 
addImmOperands__anoncdd30e2e0111::PPCOperand554   void addImmOperands(MCInst &Inst, unsigned N) const {
555     assert(N == 1 && "Invalid number of operands!");
556     if (Kind == Immediate)
557       Inst.addOperand(MCOperand::createImm(getImm()));
558     else
559       Inst.addOperand(MCOperand::createExpr(getExpr()));
560   }
561 
addS16ImmOperands__anoncdd30e2e0111::PPCOperand562   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
563     assert(N == 1 && "Invalid number of operands!");
564     switch (Kind) {
565       case Immediate:
566         Inst.addOperand(MCOperand::createImm(getImm()));
567         break;
568       case ContextImmediate:
569         Inst.addOperand(MCOperand::createImm(getImmS16Context()));
570         break;
571       default:
572         Inst.addOperand(MCOperand::createExpr(getExpr()));
573         break;
574     }
575   }
576 
addU16ImmOperands__anoncdd30e2e0111::PPCOperand577   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
578     assert(N == 1 && "Invalid number of operands!");
579     switch (Kind) {
580       case Immediate:
581         Inst.addOperand(MCOperand::createImm(getImm()));
582         break;
583       case ContextImmediate:
584         Inst.addOperand(MCOperand::createImm(getImmU16Context()));
585         break;
586       default:
587         Inst.addOperand(MCOperand::createExpr(getExpr()));
588         break;
589     }
590   }
591 
addBranchTargetOperands__anoncdd30e2e0111::PPCOperand592   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
593     assert(N == 1 && "Invalid number of operands!");
594     if (Kind == Immediate)
595       Inst.addOperand(MCOperand::createImm(getImm() / 4));
596     else
597       Inst.addOperand(MCOperand::createExpr(getExpr()));
598   }
599 
addTLSRegOperands__anoncdd30e2e0111::PPCOperand600   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
601     assert(N == 1 && "Invalid number of operands!");
602     Inst.addOperand(MCOperand::createExpr(getTLSReg()));
603   }
604 
getToken__anoncdd30e2e0111::PPCOperand605   StringRef getToken() const {
606     assert(Kind == Token && "Invalid access!");
607     return StringRef(Tok.Data, Tok.Length);
608   }
609 
610   void print(raw_ostream &OS) const override;
611 
CreateToken__anoncdd30e2e0111::PPCOperand612   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
613                                                  bool IsPPC64) {
614     auto Op = std::make_unique<PPCOperand>(Token);
615     Op->Tok.Data = Str.data();
616     Op->Tok.Length = Str.size();
617     Op->StartLoc = S;
618     Op->EndLoc = S;
619     Op->IsPPC64 = IsPPC64;
620     return Op;
621   }
622 
623   static std::unique_ptr<PPCOperand>
CreateTokenWithStringCopy__anoncdd30e2e0111::PPCOperand624   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
625     // Allocate extra memory for the string and copy it.
626     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
627     // deleter which will destroy them by simply using "delete", not correctly
628     // calling operator delete on this extra memory after calling the dtor
629     // explicitly.
630     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
631     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
632     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
633     Op->Tok.Length = Str.size();
634     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
635     Op->StartLoc = S;
636     Op->EndLoc = S;
637     Op->IsPPC64 = IsPPC64;
638     return Op;
639   }
640 
CreateImm__anoncdd30e2e0111::PPCOperand641   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
642                                                bool IsPPC64) {
643     auto Op = std::make_unique<PPCOperand>(Immediate);
644     Op->Imm.Val = Val;
645     Op->StartLoc = S;
646     Op->EndLoc = E;
647     Op->IsPPC64 = IsPPC64;
648     return Op;
649   }
650 
CreateExpr__anoncdd30e2e0111::PPCOperand651   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
652                                                 SMLoc E, bool IsPPC64) {
653     auto Op = std::make_unique<PPCOperand>(Expression);
654     Op->Expr.Val = Val;
655     Op->Expr.CRVal = EvaluateCRExpr(Val);
656     Op->StartLoc = S;
657     Op->EndLoc = E;
658     Op->IsPPC64 = IsPPC64;
659     return Op;
660   }
661 
662   static std::unique_ptr<PPCOperand>
CreateTLSReg__anoncdd30e2e0111::PPCOperand663   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
664     auto Op = std::make_unique<PPCOperand>(TLSRegister);
665     Op->TLSReg.Sym = Sym;
666     Op->StartLoc = S;
667     Op->EndLoc = E;
668     Op->IsPPC64 = IsPPC64;
669     return Op;
670   }
671 
672   static std::unique_ptr<PPCOperand>
CreateContextImm__anoncdd30e2e0111::PPCOperand673   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
674     auto Op = std::make_unique<PPCOperand>(ContextImmediate);
675     Op->Imm.Val = Val;
676     Op->StartLoc = S;
677     Op->EndLoc = E;
678     Op->IsPPC64 = IsPPC64;
679     return Op;
680   }
681 
682   static std::unique_ptr<PPCOperand>
CreateFromMCExpr__anoncdd30e2e0111::PPCOperand683   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
684     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
685       return CreateImm(CE->getValue(), S, E, IsPPC64);
686 
687     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
688       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS ||
689           SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL)
690         return CreateTLSReg(SRE, S, E, IsPPC64);
691 
692     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
693       int64_t Res;
694       if (TE->evaluateAsConstant(Res))
695         return CreateContextImm(Res, S, E, IsPPC64);
696     }
697 
698     return CreateExpr(Val, S, E, IsPPC64);
699   }
700 };
701 
702 } // end anonymous namespace.
703 
print(raw_ostream & OS) const704 void PPCOperand::print(raw_ostream &OS) const {
705   switch (Kind) {
706   case Token:
707     OS << "'" << getToken() << "'";
708     break;
709   case Immediate:
710   case ContextImmediate:
711     OS << getImm();
712     break;
713   case Expression:
714     OS << *getExpr();
715     break;
716   case TLSRegister:
717     OS << *getTLSReg();
718     break;
719   }
720 }
721 
722 static void
addNegOperand(MCInst & Inst,MCOperand & Op,MCContext & Ctx)723 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
724   if (Op.isImm()) {
725     Inst.addOperand(MCOperand::createImm(-Op.getImm()));
726     return;
727   }
728   const MCExpr *Expr = Op.getExpr();
729   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
730     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
731       Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
732       return;
733     }
734   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
735     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
736       const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
737                                                  BinExpr->getLHS(), Ctx);
738       Inst.addOperand(MCOperand::createExpr(NE));
739       return;
740     }
741   }
742   Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
743 }
744 
ProcessInstruction(MCInst & Inst,const OperandVector & Operands)745 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
746                                       const OperandVector &Operands) {
747   int Opcode = Inst.getOpcode();
748   switch (Opcode) {
749   case PPC::DCBTx:
750   case PPC::DCBTT:
751   case PPC::DCBTSTx:
752   case PPC::DCBTSTT: {
753     MCInst TmpInst;
754     TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
755                       PPC::DCBT : PPC::DCBTST);
756     TmpInst.addOperand(MCOperand::createImm(
757       (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
758     TmpInst.addOperand(Inst.getOperand(0));
759     TmpInst.addOperand(Inst.getOperand(1));
760     Inst = TmpInst;
761     break;
762   }
763   case PPC::DCBTCT:
764   case PPC::DCBTDS: {
765     MCInst TmpInst;
766     TmpInst.setOpcode(PPC::DCBT);
767     TmpInst.addOperand(Inst.getOperand(2));
768     TmpInst.addOperand(Inst.getOperand(0));
769     TmpInst.addOperand(Inst.getOperand(1));
770     Inst = TmpInst;
771     break;
772   }
773   case PPC::DCBTSTCT:
774   case PPC::DCBTSTDS: {
775     MCInst TmpInst;
776     TmpInst.setOpcode(PPC::DCBTST);
777     TmpInst.addOperand(Inst.getOperand(2));
778     TmpInst.addOperand(Inst.getOperand(0));
779     TmpInst.addOperand(Inst.getOperand(1));
780     Inst = TmpInst;
781     break;
782   }
783   case PPC::DCBFx:
784   case PPC::DCBFL:
785   case PPC::DCBFLP:
786   case PPC::DCBFPS:
787   case PPC::DCBSTPS: {
788     int L = 0;
789     if (Opcode == PPC::DCBFL)
790       L = 1;
791     else if (Opcode == PPC::DCBFLP)
792       L = 3;
793     else if (Opcode == PPC::DCBFPS)
794       L = 4;
795     else if (Opcode == PPC::DCBSTPS)
796       L = 6;
797 
798     MCInst TmpInst;
799     TmpInst.setOpcode(PPC::DCBF);
800     TmpInst.addOperand(MCOperand::createImm(L));
801     TmpInst.addOperand(Inst.getOperand(0));
802     TmpInst.addOperand(Inst.getOperand(1));
803     Inst = TmpInst;
804     break;
805   }
806   case PPC::LAx: {
807     MCInst TmpInst;
808     TmpInst.setOpcode(PPC::LA);
809     TmpInst.addOperand(Inst.getOperand(0));
810     TmpInst.addOperand(Inst.getOperand(2));
811     TmpInst.addOperand(Inst.getOperand(1));
812     Inst = TmpInst;
813     break;
814   }
815   case PPC::SUBI: {
816     MCInst TmpInst;
817     TmpInst.setOpcode(PPC::ADDI);
818     TmpInst.addOperand(Inst.getOperand(0));
819     TmpInst.addOperand(Inst.getOperand(1));
820     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
821     Inst = TmpInst;
822     break;
823   }
824   case PPC::SUBIS: {
825     MCInst TmpInst;
826     TmpInst.setOpcode(PPC::ADDIS);
827     TmpInst.addOperand(Inst.getOperand(0));
828     TmpInst.addOperand(Inst.getOperand(1));
829     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
830     Inst = TmpInst;
831     break;
832   }
833   case PPC::SUBIC: {
834     MCInst TmpInst;
835     TmpInst.setOpcode(PPC::ADDIC);
836     TmpInst.addOperand(Inst.getOperand(0));
837     TmpInst.addOperand(Inst.getOperand(1));
838     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
839     Inst = TmpInst;
840     break;
841   }
842   case PPC::SUBIC_rec: {
843     MCInst TmpInst;
844     TmpInst.setOpcode(PPC::ADDIC_rec);
845     TmpInst.addOperand(Inst.getOperand(0));
846     TmpInst.addOperand(Inst.getOperand(1));
847     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
848     Inst = TmpInst;
849     break;
850   }
851   case PPC::EXTLWI:
852   case PPC::EXTLWI_rec: {
853     MCInst TmpInst;
854     int64_t N = Inst.getOperand(2).getImm();
855     int64_t B = Inst.getOperand(3).getImm();
856     TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec);
857     TmpInst.addOperand(Inst.getOperand(0));
858     TmpInst.addOperand(Inst.getOperand(1));
859     TmpInst.addOperand(MCOperand::createImm(B));
860     TmpInst.addOperand(MCOperand::createImm(0));
861     TmpInst.addOperand(MCOperand::createImm(N - 1));
862     Inst = TmpInst;
863     break;
864   }
865   case PPC::EXTRWI:
866   case PPC::EXTRWI_rec: {
867     MCInst TmpInst;
868     int64_t N = Inst.getOperand(2).getImm();
869     int64_t B = Inst.getOperand(3).getImm();
870     TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
871     TmpInst.addOperand(Inst.getOperand(0));
872     TmpInst.addOperand(Inst.getOperand(1));
873     TmpInst.addOperand(MCOperand::createImm(B + N));
874     TmpInst.addOperand(MCOperand::createImm(32 - N));
875     TmpInst.addOperand(MCOperand::createImm(31));
876     Inst = TmpInst;
877     break;
878   }
879   case PPC::INSLWI:
880   case PPC::INSLWI_rec: {
881     MCInst TmpInst;
882     int64_t N = Inst.getOperand(2).getImm();
883     int64_t B = Inst.getOperand(3).getImm();
884     TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
885     TmpInst.addOperand(Inst.getOperand(0));
886     TmpInst.addOperand(Inst.getOperand(0));
887     TmpInst.addOperand(Inst.getOperand(1));
888     TmpInst.addOperand(MCOperand::createImm(32 - B));
889     TmpInst.addOperand(MCOperand::createImm(B));
890     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
891     Inst = TmpInst;
892     break;
893   }
894   case PPC::INSRWI:
895   case PPC::INSRWI_rec: {
896     MCInst TmpInst;
897     int64_t N = Inst.getOperand(2).getImm();
898     int64_t B = Inst.getOperand(3).getImm();
899     TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
900     TmpInst.addOperand(Inst.getOperand(0));
901     TmpInst.addOperand(Inst.getOperand(0));
902     TmpInst.addOperand(Inst.getOperand(1));
903     TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
904     TmpInst.addOperand(MCOperand::createImm(B));
905     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
906     Inst = TmpInst;
907     break;
908   }
909   case PPC::ROTRWI:
910   case PPC::ROTRWI_rec: {
911     MCInst TmpInst;
912     int64_t N = Inst.getOperand(2).getImm();
913     TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
914     TmpInst.addOperand(Inst.getOperand(0));
915     TmpInst.addOperand(Inst.getOperand(1));
916     TmpInst.addOperand(MCOperand::createImm(32 - N));
917     TmpInst.addOperand(MCOperand::createImm(0));
918     TmpInst.addOperand(MCOperand::createImm(31));
919     Inst = TmpInst;
920     break;
921   }
922   case PPC::SLWI:
923   case PPC::SLWI_rec: {
924     MCInst TmpInst;
925     int64_t N = Inst.getOperand(2).getImm();
926     TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec);
927     TmpInst.addOperand(Inst.getOperand(0));
928     TmpInst.addOperand(Inst.getOperand(1));
929     TmpInst.addOperand(MCOperand::createImm(N));
930     TmpInst.addOperand(MCOperand::createImm(0));
931     TmpInst.addOperand(MCOperand::createImm(31 - N));
932     Inst = TmpInst;
933     break;
934   }
935   case PPC::SRWI:
936   case PPC::SRWI_rec: {
937     MCInst TmpInst;
938     int64_t N = Inst.getOperand(2).getImm();
939     TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec);
940     TmpInst.addOperand(Inst.getOperand(0));
941     TmpInst.addOperand(Inst.getOperand(1));
942     TmpInst.addOperand(MCOperand::createImm(32 - N));
943     TmpInst.addOperand(MCOperand::createImm(N));
944     TmpInst.addOperand(MCOperand::createImm(31));
945     Inst = TmpInst;
946     break;
947   }
948   case PPC::CLRRWI:
949   case PPC::CLRRWI_rec: {
950     MCInst TmpInst;
951     int64_t N = Inst.getOperand(2).getImm();
952     TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec);
953     TmpInst.addOperand(Inst.getOperand(0));
954     TmpInst.addOperand(Inst.getOperand(1));
955     TmpInst.addOperand(MCOperand::createImm(0));
956     TmpInst.addOperand(MCOperand::createImm(0));
957     TmpInst.addOperand(MCOperand::createImm(31 - N));
958     Inst = TmpInst;
959     break;
960   }
961   case PPC::CLRLSLWI:
962   case PPC::CLRLSLWI_rec: {
963     MCInst TmpInst;
964     int64_t B = Inst.getOperand(2).getImm();
965     int64_t N = Inst.getOperand(3).getImm();
966     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec);
967     TmpInst.addOperand(Inst.getOperand(0));
968     TmpInst.addOperand(Inst.getOperand(1));
969     TmpInst.addOperand(MCOperand::createImm(N));
970     TmpInst.addOperand(MCOperand::createImm(B - N));
971     TmpInst.addOperand(MCOperand::createImm(31 - N));
972     Inst = TmpInst;
973     break;
974   }
975   case PPC::EXTLDI:
976   case PPC::EXTLDI_rec: {
977     MCInst TmpInst;
978     int64_t N = Inst.getOperand(2).getImm();
979     int64_t B = Inst.getOperand(3).getImm();
980     TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec);
981     TmpInst.addOperand(Inst.getOperand(0));
982     TmpInst.addOperand(Inst.getOperand(1));
983     TmpInst.addOperand(MCOperand::createImm(B));
984     TmpInst.addOperand(MCOperand::createImm(N - 1));
985     Inst = TmpInst;
986     break;
987   }
988   case PPC::EXTRDI:
989   case PPC::EXTRDI_rec: {
990     MCInst TmpInst;
991     int64_t N = Inst.getOperand(2).getImm();
992     int64_t B = Inst.getOperand(3).getImm();
993     TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
994     TmpInst.addOperand(Inst.getOperand(0));
995     TmpInst.addOperand(Inst.getOperand(1));
996     TmpInst.addOperand(MCOperand::createImm(B + N));
997     TmpInst.addOperand(MCOperand::createImm(64 - N));
998     Inst = TmpInst;
999     break;
1000   }
1001   case PPC::INSRDI:
1002   case PPC::INSRDI_rec: {
1003     MCInst TmpInst;
1004     int64_t N = Inst.getOperand(2).getImm();
1005     int64_t B = Inst.getOperand(3).getImm();
1006     TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec);
1007     TmpInst.addOperand(Inst.getOperand(0));
1008     TmpInst.addOperand(Inst.getOperand(0));
1009     TmpInst.addOperand(Inst.getOperand(1));
1010     TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1011     TmpInst.addOperand(MCOperand::createImm(B));
1012     Inst = TmpInst;
1013     break;
1014   }
1015   case PPC::ROTRDI:
1016   case PPC::ROTRDI_rec: {
1017     MCInst TmpInst;
1018     int64_t N = Inst.getOperand(2).getImm();
1019     TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1020     TmpInst.addOperand(Inst.getOperand(0));
1021     TmpInst.addOperand(Inst.getOperand(1));
1022     TmpInst.addOperand(MCOperand::createImm(64 - N));
1023     TmpInst.addOperand(MCOperand::createImm(0));
1024     Inst = TmpInst;
1025     break;
1026   }
1027   case PPC::SLDI:
1028   case PPC::SLDI_rec: {
1029     MCInst TmpInst;
1030     int64_t N = Inst.getOperand(2).getImm();
1031     TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec);
1032     TmpInst.addOperand(Inst.getOperand(0));
1033     TmpInst.addOperand(Inst.getOperand(1));
1034     TmpInst.addOperand(MCOperand::createImm(N));
1035     TmpInst.addOperand(MCOperand::createImm(63 - N));
1036     Inst = TmpInst;
1037     break;
1038   }
1039   case PPC::SUBPCIS: {
1040     MCInst TmpInst;
1041     int64_t N = Inst.getOperand(1).getImm();
1042     TmpInst.setOpcode(PPC::ADDPCIS);
1043     TmpInst.addOperand(Inst.getOperand(0));
1044     TmpInst.addOperand(MCOperand::createImm(-N));
1045     Inst = TmpInst;
1046     break;
1047   }
1048   case PPC::SRDI:
1049   case PPC::SRDI_rec: {
1050     MCInst TmpInst;
1051     int64_t N = Inst.getOperand(2).getImm();
1052     TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1053     TmpInst.addOperand(Inst.getOperand(0));
1054     TmpInst.addOperand(Inst.getOperand(1));
1055     TmpInst.addOperand(MCOperand::createImm(64 - N));
1056     TmpInst.addOperand(MCOperand::createImm(N));
1057     Inst = TmpInst;
1058     break;
1059   }
1060   case PPC::CLRRDI:
1061   case PPC::CLRRDI_rec: {
1062     MCInst TmpInst;
1063     int64_t N = Inst.getOperand(2).getImm();
1064     TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec);
1065     TmpInst.addOperand(Inst.getOperand(0));
1066     TmpInst.addOperand(Inst.getOperand(1));
1067     TmpInst.addOperand(MCOperand::createImm(0));
1068     TmpInst.addOperand(MCOperand::createImm(63 - N));
1069     Inst = TmpInst;
1070     break;
1071   }
1072   case PPC::CLRLSLDI:
1073   case PPC::CLRLSLDI_rec: {
1074     MCInst TmpInst;
1075     int64_t B = Inst.getOperand(2).getImm();
1076     int64_t N = Inst.getOperand(3).getImm();
1077     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec);
1078     TmpInst.addOperand(Inst.getOperand(0));
1079     TmpInst.addOperand(Inst.getOperand(1));
1080     TmpInst.addOperand(MCOperand::createImm(N));
1081     TmpInst.addOperand(MCOperand::createImm(B - N));
1082     Inst = TmpInst;
1083     break;
1084   }
1085   case PPC::RLWINMbm:
1086   case PPC::RLWINMbm_rec: {
1087     unsigned MB, ME;
1088     int64_t BM = Inst.getOperand(3).getImm();
1089     if (!isRunOfOnes(BM, MB, ME))
1090       break;
1091 
1092     MCInst TmpInst;
1093     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec);
1094     TmpInst.addOperand(Inst.getOperand(0));
1095     TmpInst.addOperand(Inst.getOperand(1));
1096     TmpInst.addOperand(Inst.getOperand(2));
1097     TmpInst.addOperand(MCOperand::createImm(MB));
1098     TmpInst.addOperand(MCOperand::createImm(ME));
1099     Inst = TmpInst;
1100     break;
1101   }
1102   case PPC::RLWIMIbm:
1103   case PPC::RLWIMIbm_rec: {
1104     unsigned MB, ME;
1105     int64_t BM = Inst.getOperand(3).getImm();
1106     if (!isRunOfOnes(BM, MB, ME))
1107       break;
1108 
1109     MCInst TmpInst;
1110     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec);
1111     TmpInst.addOperand(Inst.getOperand(0));
1112     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1113     TmpInst.addOperand(Inst.getOperand(1));
1114     TmpInst.addOperand(Inst.getOperand(2));
1115     TmpInst.addOperand(MCOperand::createImm(MB));
1116     TmpInst.addOperand(MCOperand::createImm(ME));
1117     Inst = TmpInst;
1118     break;
1119   }
1120   case PPC::RLWNMbm:
1121   case PPC::RLWNMbm_rec: {
1122     unsigned MB, ME;
1123     int64_t BM = Inst.getOperand(3).getImm();
1124     if (!isRunOfOnes(BM, MB, ME))
1125       break;
1126 
1127     MCInst TmpInst;
1128     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec);
1129     TmpInst.addOperand(Inst.getOperand(0));
1130     TmpInst.addOperand(Inst.getOperand(1));
1131     TmpInst.addOperand(Inst.getOperand(2));
1132     TmpInst.addOperand(MCOperand::createImm(MB));
1133     TmpInst.addOperand(MCOperand::createImm(ME));
1134     Inst = TmpInst;
1135     break;
1136   }
1137   case PPC::MFTB: {
1138     if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1139       assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1140       Inst.setOpcode(PPC::MFSPR);
1141     }
1142     break;
1143   }
1144   }
1145 }
1146 
1147 static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
1148                                          unsigned VariantID = 0);
1149 
MatchAndEmitInstruction(SMLoc IDLoc,unsigned & Opcode,OperandVector & Operands,MCStreamer & Out,uint64_t & ErrorInfo,bool MatchingInlineAsm)1150 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1151                                            OperandVector &Operands,
1152                                            MCStreamer &Out, uint64_t &ErrorInfo,
1153                                            bool MatchingInlineAsm) {
1154   MCInst Inst;
1155 
1156   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1157   case Match_Success:
1158     // Post-process instructions (typically extended mnemonics)
1159     ProcessInstruction(Inst, Operands);
1160     Inst.setLoc(IDLoc);
1161     Out.emitInstruction(Inst, getSTI());
1162     return false;
1163   case Match_MissingFeature:
1164     return Error(IDLoc, "instruction use requires an option to be enabled");
1165   case Match_MnemonicFail: {
1166     FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1167     std::string Suggestion = PPCMnemonicSpellCheck(
1168         ((PPCOperand &)*Operands[0]).getToken(), FBS);
1169     return Error(IDLoc, "invalid instruction" + Suggestion,
1170                  ((PPCOperand &)*Operands[0]).getLocRange());
1171   }
1172   case Match_InvalidOperand: {
1173     SMLoc ErrorLoc = IDLoc;
1174     if (ErrorInfo != ~0ULL) {
1175       if (ErrorInfo >= Operands.size())
1176         return Error(IDLoc, "too few operands for instruction");
1177 
1178       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1179       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1180     }
1181 
1182     return Error(ErrorLoc, "invalid operand for instruction");
1183   }
1184   }
1185 
1186   llvm_unreachable("Implement any new match types added!");
1187 }
1188 
MatchRegisterName(unsigned & RegNo,int64_t & IntVal)1189 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) {
1190   if (getParser().getTok().is(AsmToken::Percent))
1191     getParser().Lex(); // Eat the '%'.
1192 
1193   if (!getParser().getTok().is(AsmToken::Identifier))
1194     return true;
1195 
1196   StringRef Name = getParser().getTok().getString();
1197   if (Name.equals_lower("lr")) {
1198     RegNo = isPPC64() ? PPC::LR8 : PPC::LR;
1199     IntVal = 8;
1200   } else if (Name.equals_lower("ctr")) {
1201     RegNo = isPPC64() ? PPC::CTR8 : PPC::CTR;
1202     IntVal = 9;
1203   } else if (Name.equals_lower("vrsave")) {
1204     RegNo = PPC::VRSAVE;
1205     IntVal = 256;
1206   } else if (Name.startswith_lower("r") &&
1207              !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1208     RegNo = isPPC64() ? XRegs[IntVal] : RRegs[IntVal];
1209   } else if (Name.startswith_lower("f") &&
1210              !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1211     RegNo = FRegs[IntVal];
1212   } else if (Name.startswith_lower("vs") &&
1213              !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1214     RegNo = VSRegs[IntVal];
1215   } else if (Name.startswith_lower("v") &&
1216              !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1217     RegNo = VRegs[IntVal];
1218   } else if (Name.startswith_lower("cr") &&
1219              !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1220     RegNo = CRRegs[IntVal];
1221   } else
1222     return true;
1223   getParser().Lex();
1224   return false;
1225 }
1226 
1227 bool PPCAsmParser::
ParseRegister(unsigned & RegNo,SMLoc & StartLoc,SMLoc & EndLoc)1228 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1229   if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success)
1230     return TokError("invalid register name");
1231   return false;
1232 }
1233 
tryParseRegister(unsigned & RegNo,SMLoc & StartLoc,SMLoc & EndLoc)1234 OperandMatchResultTy PPCAsmParser::tryParseRegister(unsigned &RegNo,
1235                                                     SMLoc &StartLoc,
1236                                                     SMLoc &EndLoc) {
1237   const AsmToken &Tok = getParser().getTok();
1238   StartLoc = Tok.getLoc();
1239   EndLoc = Tok.getEndLoc();
1240   RegNo = 0;
1241   int64_t IntVal;
1242   if (MatchRegisterName(RegNo, IntVal))
1243     return MatchOperand_NoMatch;
1244   return MatchOperand_Success;
1245 }
1246 
1247 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1248 /// the expression and check for VK_PPC_LO/HI/HA
1249 /// symbol variants.  If all symbols with modifier use the same
1250 /// variant, return the corresponding PPCMCExpr::VariantKind,
1251 /// and a modified expression using the default symbol variant.
1252 /// Otherwise, return NULL.
1253 const MCExpr *PPCAsmParser::
ExtractModifierFromExpr(const MCExpr * E,PPCMCExpr::VariantKind & Variant)1254 ExtractModifierFromExpr(const MCExpr *E,
1255                         PPCMCExpr::VariantKind &Variant) {
1256   MCContext &Context = getParser().getContext();
1257   Variant = PPCMCExpr::VK_PPC_None;
1258 
1259   switch (E->getKind()) {
1260   case MCExpr::Target:
1261   case MCExpr::Constant:
1262     return nullptr;
1263 
1264   case MCExpr::SymbolRef: {
1265     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1266 
1267     switch (SRE->getKind()) {
1268     case MCSymbolRefExpr::VK_PPC_LO:
1269       Variant = PPCMCExpr::VK_PPC_LO;
1270       break;
1271     case MCSymbolRefExpr::VK_PPC_HI:
1272       Variant = PPCMCExpr::VK_PPC_HI;
1273       break;
1274     case MCSymbolRefExpr::VK_PPC_HA:
1275       Variant = PPCMCExpr::VK_PPC_HA;
1276       break;
1277     case MCSymbolRefExpr::VK_PPC_HIGH:
1278       Variant = PPCMCExpr::VK_PPC_HIGH;
1279       break;
1280     case MCSymbolRefExpr::VK_PPC_HIGHA:
1281       Variant = PPCMCExpr::VK_PPC_HIGHA;
1282       break;
1283     case MCSymbolRefExpr::VK_PPC_HIGHER:
1284       Variant = PPCMCExpr::VK_PPC_HIGHER;
1285       break;
1286     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1287       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1288       break;
1289     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1290       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1291       break;
1292     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1293       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1294       break;
1295     default:
1296       return nullptr;
1297     }
1298 
1299     return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1300   }
1301 
1302   case MCExpr::Unary: {
1303     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1304     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1305     if (!Sub)
1306       return nullptr;
1307     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1308   }
1309 
1310   case MCExpr::Binary: {
1311     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1312     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1313     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1314     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1315 
1316     if (!LHS && !RHS)
1317       return nullptr;
1318 
1319     if (!LHS) LHS = BE->getLHS();
1320     if (!RHS) RHS = BE->getRHS();
1321 
1322     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1323       Variant = RHSVariant;
1324     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1325       Variant = LHSVariant;
1326     else if (LHSVariant == RHSVariant)
1327       Variant = LHSVariant;
1328     else
1329       return nullptr;
1330 
1331     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1332   }
1333   }
1334 
1335   llvm_unreachable("Invalid expression kind!");
1336 }
1337 
1338 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1339 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1340 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1341 /// FIXME: This is a hack.
1342 const MCExpr *PPCAsmParser::
FixupVariantKind(const MCExpr * E)1343 FixupVariantKind(const MCExpr *E) {
1344   MCContext &Context = getParser().getContext();
1345 
1346   switch (E->getKind()) {
1347   case MCExpr::Target:
1348   case MCExpr::Constant:
1349     return E;
1350 
1351   case MCExpr::SymbolRef: {
1352     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1353     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1354 
1355     switch (SRE->getKind()) {
1356     case MCSymbolRefExpr::VK_TLSGD:
1357       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1358       break;
1359     case MCSymbolRefExpr::VK_TLSLD:
1360       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1361       break;
1362     default:
1363       return E;
1364     }
1365     return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1366   }
1367 
1368   case MCExpr::Unary: {
1369     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1370     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1371     if (Sub == UE->getSubExpr())
1372       return E;
1373     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1374   }
1375 
1376   case MCExpr::Binary: {
1377     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1378     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1379     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1380     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1381       return E;
1382     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1383   }
1384   }
1385 
1386   llvm_unreachable("Invalid expression kind!");
1387 }
1388 
1389 /// ParseExpression.  This differs from the default "parseExpression" in that
1390 /// it handles modifiers.
1391 bool PPCAsmParser::
ParseExpression(const MCExpr * & EVal)1392 ParseExpression(const MCExpr *&EVal) {
1393   // (ELF Platforms)
1394   // Handle \code @l/@ha \endcode
1395   if (getParser().parseExpression(EVal))
1396     return true;
1397 
1398   EVal = FixupVariantKind(EVal);
1399 
1400   PPCMCExpr::VariantKind Variant;
1401   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1402   if (E)
1403     EVal = PPCMCExpr::create(Variant, E, getParser().getContext());
1404 
1405   return false;
1406 }
1407 
1408 /// ParseOperand
1409 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1410 /// rNN for MachO.
ParseOperand(OperandVector & Operands)1411 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1412   MCAsmParser &Parser = getParser();
1413   SMLoc S = Parser.getTok().getLoc();
1414   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1415   const MCExpr *EVal;
1416 
1417   // Attempt to parse the next token as an immediate
1418   switch (getLexer().getKind()) {
1419   // Special handling for register names.  These are interpreted
1420   // as immediates corresponding to the register number.
1421   case AsmToken::Percent: {
1422     unsigned RegNo;
1423     int64_t IntVal;
1424     if (MatchRegisterName(RegNo, IntVal))
1425       return Error(S, "invalid register name");
1426 
1427     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1428     return false;
1429   }
1430   case AsmToken::Identifier:
1431   case AsmToken::LParen:
1432   case AsmToken::Plus:
1433   case AsmToken::Minus:
1434   case AsmToken::Integer:
1435   case AsmToken::Dot:
1436   case AsmToken::Dollar:
1437   case AsmToken::Exclaim:
1438   case AsmToken::Tilde:
1439     if (!ParseExpression(EVal))
1440       break;
1441     // Fall-through
1442     LLVM_FALLTHROUGH;
1443   default:
1444     return Error(S, "unknown operand");
1445   }
1446 
1447   // Push the parsed operand into the list of operands
1448   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1449 
1450   // Check whether this is a TLS call expression
1451   bool TLSCall = false;
1452   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1453     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1454 
1455   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1456     const MCExpr *TLSSym;
1457 
1458     Parser.Lex(); // Eat the '('.
1459     S = Parser.getTok().getLoc();
1460     if (ParseExpression(TLSSym))
1461       return Error(S, "invalid TLS call expression");
1462     if (getLexer().isNot(AsmToken::RParen))
1463       return Error(Parser.getTok().getLoc(), "missing ')'");
1464     E = Parser.getTok().getLoc();
1465     Parser.Lex(); // Eat the ')'.
1466 
1467     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1468   }
1469 
1470   // Otherwise, check for D-form memory operands
1471   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1472     Parser.Lex(); // Eat the '('.
1473     S = Parser.getTok().getLoc();
1474 
1475     int64_t IntVal;
1476     switch (getLexer().getKind()) {
1477     case AsmToken::Percent: {
1478       unsigned RegNo;
1479       if (MatchRegisterName(RegNo, IntVal))
1480         return Error(S, "invalid register name");
1481       break;
1482     }
1483     case AsmToken::Integer:
1484       if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1485           IntVal > 31)
1486         return Error(S, "invalid register number");
1487       break;
1488     case AsmToken::Identifier:
1489     default:
1490       return Error(S, "invalid memory operand");
1491     }
1492 
1493     E = Parser.getTok().getLoc();
1494     if (parseToken(AsmToken::RParen, "missing ')'"))
1495       return true;
1496     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1497   }
1498 
1499   return false;
1500 }
1501 
1502 /// Parse an instruction mnemonic followed by its operands.
ParseInstruction(ParseInstructionInfo & Info,StringRef Name,SMLoc NameLoc,OperandVector & Operands)1503 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1504                                     SMLoc NameLoc, OperandVector &Operands) {
1505   // The first operand is the token for the instruction name.
1506   // If the next character is a '+' or '-', we need to add it to the
1507   // instruction name, to match what TableGen is doing.
1508   std::string NewOpcode;
1509   if (parseOptionalToken(AsmToken::Plus)) {
1510     NewOpcode = std::string(Name);
1511     NewOpcode += '+';
1512     Name = NewOpcode;
1513   }
1514   if (parseOptionalToken(AsmToken::Minus)) {
1515     NewOpcode = std::string(Name);
1516     NewOpcode += '-';
1517     Name = NewOpcode;
1518   }
1519   // If the instruction ends in a '.', we need to create a separate
1520   // token for it, to match what TableGen is doing.
1521   size_t Dot = Name.find('.');
1522   StringRef Mnemonic = Name.slice(0, Dot);
1523   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1524     Operands.push_back(
1525         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1526   else
1527     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1528   if (Dot != StringRef::npos) {
1529     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1530     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1531     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1532       Operands.push_back(
1533           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1534     else
1535       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1536   }
1537 
1538   // If there are no more operands then finish
1539   if (parseOptionalToken(AsmToken::EndOfStatement))
1540     return false;
1541 
1542   // Parse the first operand
1543   if (ParseOperand(Operands))
1544     return true;
1545 
1546   while (!parseOptionalToken(AsmToken::EndOfStatement)) {
1547     if (parseToken(AsmToken::Comma) || ParseOperand(Operands))
1548       return true;
1549   }
1550 
1551   // We'll now deal with an unfortunate special case: the syntax for the dcbt
1552   // and dcbtst instructions differs for server vs. embedded cores.
1553   //  The syntax for dcbt is:
1554   //    dcbt ra, rb, th [server]
1555   //    dcbt th, ra, rb [embedded]
1556   //  where th can be omitted when it is 0. dcbtst is the same. We take the
1557   //  server form to be the default, so swap the operands if we're parsing for
1558   //  an embedded core (they'll be swapped again upon printing).
1559   if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1560       Operands.size() == 4 &&
1561       (Name == "dcbt" || Name == "dcbtst")) {
1562     std::swap(Operands[1], Operands[3]);
1563     std::swap(Operands[2], Operands[1]);
1564   }
1565 
1566   return false;
1567 }
1568 
1569 /// ParseDirective parses the PPC specific directives
ParseDirective(AsmToken DirectiveID)1570 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1571   StringRef IDVal = DirectiveID.getIdentifier();
1572   if (IDVal == ".word")
1573     ParseDirectiveWord(2, DirectiveID);
1574   else if (IDVal == ".llong")
1575     ParseDirectiveWord(8, DirectiveID);
1576   else if (IDVal == ".tc")
1577     ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1578   else if (IDVal == ".machine")
1579     ParseDirectiveMachine(DirectiveID.getLoc());
1580   else if (IDVal == ".abiversion")
1581     ParseDirectiveAbiVersion(DirectiveID.getLoc());
1582   else if (IDVal == ".localentry")
1583     ParseDirectiveLocalEntry(DirectiveID.getLoc());
1584   else
1585     return true;
1586   return false;
1587 }
1588 
1589 /// ParseDirectiveWord
1590 ///  ::= .word [ expression (, expression)* ]
ParseDirectiveWord(unsigned Size,AsmToken ID)1591 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) {
1592   auto parseOp = [&]() -> bool {
1593     const MCExpr *Value;
1594     SMLoc ExprLoc = getParser().getTok().getLoc();
1595     if (getParser().parseExpression(Value))
1596       return true;
1597     if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1598       assert(Size <= 8 && "Invalid size");
1599       uint64_t IntValue = MCE->getValue();
1600       if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1601         return Error(ExprLoc, "literal value out of range for '" +
1602                                   ID.getIdentifier() + "' directive");
1603       getStreamer().emitIntValue(IntValue, Size);
1604     } else
1605       getStreamer().emitValue(Value, Size, ExprLoc);
1606     return false;
1607   };
1608 
1609   if (parseMany(parseOp))
1610     return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive");
1611   return false;
1612 }
1613 
1614 /// ParseDirectiveTC
1615 ///  ::= .tc [ symbol (, expression)* ]
ParseDirectiveTC(unsigned Size,AsmToken ID)1616 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) {
1617   MCAsmParser &Parser = getParser();
1618   // Skip TC symbol, which is only used with XCOFF.
1619   while (getLexer().isNot(AsmToken::EndOfStatement)
1620          && getLexer().isNot(AsmToken::Comma))
1621     Parser.Lex();
1622   if (parseToken(AsmToken::Comma))
1623     return addErrorSuffix(" in '.tc' directive");
1624 
1625   // Align to word size.
1626   getParser().getStreamer().emitValueToAlignment(Size);
1627 
1628   // Emit expressions.
1629   return ParseDirectiveWord(Size, ID);
1630 }
1631 
1632 /// ParseDirectiveMachine (ELF platforms)
1633 ///  ::= .machine [ cpu | "push" | "pop" ]
ParseDirectiveMachine(SMLoc L)1634 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1635   MCAsmParser &Parser = getParser();
1636   if (Parser.getTok().isNot(AsmToken::Identifier) &&
1637       Parser.getTok().isNot(AsmToken::String))
1638     return Error(L, "unexpected token in '.machine' directive");
1639 
1640   StringRef CPU = Parser.getTok().getIdentifier();
1641 
1642   // FIXME: Right now, the parser always allows any available
1643   // instruction, so the .machine directive is not useful.
1644   // In the wild, any/push/pop/ppc64/altivec/power[4-9] are seen.
1645 
1646   Parser.Lex();
1647 
1648   if (parseToken(AsmToken::EndOfStatement))
1649     return addErrorSuffix(" in '.machine' directive");
1650 
1651   PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1652       getParser().getStreamer().getTargetStreamer());
1653   if (TStreamer != nullptr)
1654     TStreamer->emitMachine(CPU);
1655 
1656   return false;
1657 }
1658 
1659 /// ParseDirectiveAbiVersion
1660 ///  ::= .abiversion constant-expression
ParseDirectiveAbiVersion(SMLoc L)1661 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1662   int64_t AbiVersion;
1663   if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1664             "expected constant expression") ||
1665       parseToken(AsmToken::EndOfStatement))
1666     return addErrorSuffix(" in '.abiversion' directive");
1667 
1668   PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1669       getParser().getStreamer().getTargetStreamer());
1670   if (TStreamer != nullptr)
1671     TStreamer->emitAbiVersion(AbiVersion);
1672 
1673   return false;
1674 }
1675 
1676 /// ParseDirectiveLocalEntry
1677 ///  ::= .localentry symbol, expression
ParseDirectiveLocalEntry(SMLoc L)1678 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1679   StringRef Name;
1680   if (getParser().parseIdentifier(Name))
1681     return Error(L, "expected identifier in '.localentry' directive");
1682 
1683   MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1684   const MCExpr *Expr;
1685 
1686   if (parseToken(AsmToken::Comma) ||
1687       check(getParser().parseExpression(Expr), L, "expected expression") ||
1688       parseToken(AsmToken::EndOfStatement))
1689     return addErrorSuffix(" in '.localentry' directive");
1690 
1691   PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1692       getParser().getStreamer().getTargetStreamer());
1693   if (TStreamer != nullptr)
1694     TStreamer->emitLocalEntry(Sym, Expr);
1695 
1696   return false;
1697 }
1698 
1699 
1700 
1701 /// Force static initialization.
LLVMInitializePowerPCAsmParser()1702 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmParser() {
1703   RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target());
1704   RegisterMCAsmParser<PPCAsmParser> B(getThePPC32LETarget());
1705   RegisterMCAsmParser<PPCAsmParser> C(getThePPC64Target());
1706   RegisterMCAsmParser<PPCAsmParser> D(getThePPC64LETarget());
1707 }
1708 
1709 #define GET_REGISTER_MATCHER
1710 #define GET_MATCHER_IMPLEMENTATION
1711 #define GET_MNEMONIC_SPELL_CHECKER
1712 #include "PPCGenAsmMatcher.inc"
1713 
1714 // Define this matcher function after the auto-generated include so we
1715 // have the match class enum definitions.
validateTargetOperandClass(MCParsedAsmOperand & AsmOp,unsigned Kind)1716 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1717                                                   unsigned Kind) {
1718   // If the kind is a token for a literal immediate, check if our asm
1719   // operand matches. This is for InstAliases which have a fixed-value
1720   // immediate in the syntax.
1721   int64_t ImmVal;
1722   switch (Kind) {
1723     case MCK_0: ImmVal = 0; break;
1724     case MCK_1: ImmVal = 1; break;
1725     case MCK_2: ImmVal = 2; break;
1726     case MCK_3: ImmVal = 3; break;
1727     case MCK_4: ImmVal = 4; break;
1728     case MCK_5: ImmVal = 5; break;
1729     case MCK_6: ImmVal = 6; break;
1730     case MCK_7: ImmVal = 7; break;
1731     default: return Match_InvalidOperand;
1732   }
1733 
1734   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1735   if (Op.isImm() && Op.getImm() == ImmVal)
1736     return Match_Success;
1737 
1738   return Match_InvalidOperand;
1739 }
1740 
1741 const MCExpr *
applyModifierToExpr(const MCExpr * E,MCSymbolRefExpr::VariantKind Variant,MCContext & Ctx)1742 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1743                                   MCSymbolRefExpr::VariantKind Variant,
1744                                   MCContext &Ctx) {
1745   switch (Variant) {
1746   case MCSymbolRefExpr::VK_PPC_LO:
1747     return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, Ctx);
1748   case MCSymbolRefExpr::VK_PPC_HI:
1749     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, Ctx);
1750   case MCSymbolRefExpr::VK_PPC_HA:
1751     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, Ctx);
1752   case MCSymbolRefExpr::VK_PPC_HIGH:
1753     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, Ctx);
1754   case MCSymbolRefExpr::VK_PPC_HIGHA:
1755     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, Ctx);
1756   case MCSymbolRefExpr::VK_PPC_HIGHER:
1757     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, Ctx);
1758   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1759     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, Ctx);
1760   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1761     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, Ctx);
1762   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1763     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, Ctx);
1764   default:
1765     return nullptr;
1766   }
1767 }
1768