1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/ScopedHashTable.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/RecyclingAllocator.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
29 using namespace llvm;
30
31 #define DEBUG_TYPE "machine-cse"
32
33 STATISTIC(NumCoalesces, "Number of copies coalesced");
34 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
35 STATISTIC(NumPhysCSEs,
36 "Number of physreg referencing common subexpr eliminated");
37 STATISTIC(NumCrossBBCSEs,
38 "Number of cross-MBB physreg referencing CS eliminated");
39 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
40
41 namespace {
42 class MachineCSE : public MachineFunctionPass {
43 const TargetInstrInfo *TII;
44 const TargetRegisterInfo *TRI;
45 AliasAnalysis *AA;
46 MachineDominatorTree *DT;
47 MachineRegisterInfo *MRI;
48 public:
49 static char ID; // Pass identification
MachineCSE()50 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
51 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
52 }
53
54 bool runOnMachineFunction(MachineFunction &MF) override;
55
getAnalysisUsage(AnalysisUsage & AU) const56 void getAnalysisUsage(AnalysisUsage &AU) const override {
57 AU.setPreservesCFG();
58 MachineFunctionPass::getAnalysisUsage(AU);
59 AU.addRequired<AliasAnalysis>();
60 AU.addPreservedID(MachineLoopInfoID);
61 AU.addRequired<MachineDominatorTree>();
62 AU.addPreserved<MachineDominatorTree>();
63 }
64
releaseMemory()65 void releaseMemory() override {
66 ScopeMap.clear();
67 Exps.clear();
68 }
69
70 private:
71 const unsigned LookAheadLimit;
72 typedef RecyclingAllocator<BumpPtrAllocator,
73 ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
74 typedef ScopedHashTable<MachineInstr*, unsigned,
75 MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
76 typedef ScopedHTType::ScopeTy ScopeType;
77 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
78 ScopedHTType VNT;
79 SmallVector<MachineInstr*, 64> Exps;
80 unsigned CurrVN;
81
82 bool PerformTrivialCopyPropagation(MachineInstr *MI,
83 MachineBasicBlock *MBB);
84 bool isPhysDefTriviallyDead(unsigned Reg,
85 MachineBasicBlock::const_iterator I,
86 MachineBasicBlock::const_iterator E) const;
87 bool hasLivePhysRegDefUses(const MachineInstr *MI,
88 const MachineBasicBlock *MBB,
89 SmallSet<unsigned,8> &PhysRefs,
90 SmallVectorImpl<unsigned> &PhysDefs,
91 bool &PhysUseDef) const;
92 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
93 SmallSet<unsigned,8> &PhysRefs,
94 SmallVectorImpl<unsigned> &PhysDefs,
95 bool &NonLocal) const;
96 bool isCSECandidate(MachineInstr *MI);
97 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
98 MachineInstr *CSMI, MachineInstr *MI);
99 void EnterScope(MachineBasicBlock *MBB);
100 void ExitScope(MachineBasicBlock *MBB);
101 bool ProcessBlock(MachineBasicBlock *MBB);
102 void ExitScopeIfDone(MachineDomTreeNode *Node,
103 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
104 bool PerformCSE(MachineDomTreeNode *Node);
105 };
106 } // end anonymous namespace
107
108 char MachineCSE::ID = 0;
109 char &llvm::MachineCSEID = MachineCSE::ID;
110 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
111 "Machine Common Subexpression Elimination", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)112 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
113 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
114 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
115 "Machine Common Subexpression Elimination", false, false)
116
117 /// The source register of a COPY machine instruction can be propagated to all
118 /// its users, and this propagation could increase the probability of finding
119 /// common subexpressions. If the COPY has only one user, the COPY itself can
120 /// be removed.
121 bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
122 MachineBasicBlock *MBB) {
123 bool Changed = false;
124 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
125 MachineOperand &MO = MI->getOperand(i);
126 if (!MO.isReg() || !MO.isUse())
127 continue;
128 unsigned Reg = MO.getReg();
129 if (!TargetRegisterInfo::isVirtualRegister(Reg))
130 continue;
131 bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
132 MachineInstr *DefMI = MRI->getVRegDef(Reg);
133 if (!DefMI->isCopy())
134 continue;
135 unsigned SrcReg = DefMI->getOperand(1).getReg();
136 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
137 continue;
138 if (DefMI->getOperand(0).getSubReg())
139 continue;
140 // FIXME: We should trivially coalesce subregister copies to expose CSE
141 // opportunities on instructions with truncated operands (see
142 // cse-add-with-overflow.ll). This can be done here as follows:
143 // if (SrcSubReg)
144 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
145 // SrcSubReg);
146 // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
147 //
148 // The 2-addr pass has been updated to handle coalesced subregs. However,
149 // some machine-specific code still can't handle it.
150 // To handle it properly we also need a way find a constrained subregister
151 // class given a super-reg class and subreg index.
152 if (DefMI->getOperand(1).getSubReg())
153 continue;
154 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
155 if (!MRI->constrainRegClass(SrcReg, RC))
156 continue;
157 DEBUG(dbgs() << "Coalescing: " << *DefMI);
158 DEBUG(dbgs() << "*** to: " << *MI);
159 // Propagate SrcReg of copies to MI.
160 MO.setReg(SrcReg);
161 MRI->clearKillFlags(SrcReg);
162 // Coalesce single use copies.
163 if (OnlyOneUse) {
164 DefMI->eraseFromParent();
165 ++NumCoalesces;
166 }
167 Changed = true;
168 }
169
170 return Changed;
171 }
172
173 bool
isPhysDefTriviallyDead(unsigned Reg,MachineBasicBlock::const_iterator I,MachineBasicBlock::const_iterator E) const174 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
175 MachineBasicBlock::const_iterator I,
176 MachineBasicBlock::const_iterator E) const {
177 unsigned LookAheadLeft = LookAheadLimit;
178 while (LookAheadLeft) {
179 // Skip over dbg_value's.
180 while (I != E && I->isDebugValue())
181 ++I;
182
183 if (I == E)
184 // Reached end of block, register is obviously dead.
185 return true;
186
187 bool SeenDef = false;
188 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
189 const MachineOperand &MO = I->getOperand(i);
190 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
191 SeenDef = true;
192 if (!MO.isReg() || !MO.getReg())
193 continue;
194 if (!TRI->regsOverlap(MO.getReg(), Reg))
195 continue;
196 if (MO.isUse())
197 // Found a use!
198 return false;
199 SeenDef = true;
200 }
201 if (SeenDef)
202 // See a def of Reg (or an alias) before encountering any use, it's
203 // trivially dead.
204 return true;
205
206 --LookAheadLeft;
207 ++I;
208 }
209 return false;
210 }
211
212 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
213 /// physical registers (except for dead defs of physical registers). It also
214 /// returns the physical register def by reference if it's the only one and the
215 /// instruction does not uses a physical register.
hasLivePhysRegDefUses(const MachineInstr * MI,const MachineBasicBlock * MBB,SmallSet<unsigned,8> & PhysRefs,SmallVectorImpl<unsigned> & PhysDefs,bool & PhysUseDef) const216 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
217 const MachineBasicBlock *MBB,
218 SmallSet<unsigned,8> &PhysRefs,
219 SmallVectorImpl<unsigned> &PhysDefs,
220 bool &PhysUseDef) const{
221 // First, add all uses to PhysRefs.
222 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
223 const MachineOperand &MO = MI->getOperand(i);
224 if (!MO.isReg() || MO.isDef())
225 continue;
226 unsigned Reg = MO.getReg();
227 if (!Reg)
228 continue;
229 if (TargetRegisterInfo::isVirtualRegister(Reg))
230 continue;
231 // Reading constant physregs is ok.
232 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
233 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
234 PhysRefs.insert(*AI);
235 }
236
237 // Next, collect all defs into PhysDefs. If any is already in PhysRefs
238 // (which currently contains only uses), set the PhysUseDef flag.
239 PhysUseDef = false;
240 MachineBasicBlock::const_iterator I = MI; I = std::next(I);
241 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
242 const MachineOperand &MO = MI->getOperand(i);
243 if (!MO.isReg() || !MO.isDef())
244 continue;
245 unsigned Reg = MO.getReg();
246 if (!Reg)
247 continue;
248 if (TargetRegisterInfo::isVirtualRegister(Reg))
249 continue;
250 // Check against PhysRefs even if the def is "dead".
251 if (PhysRefs.count(Reg))
252 PhysUseDef = true;
253 // If the def is dead, it's ok. But the def may not marked "dead". That's
254 // common since this pass is run before livevariables. We can scan
255 // forward a few instructions and check if it is obviously dead.
256 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
257 PhysDefs.push_back(Reg);
258 }
259
260 // Finally, add all defs to PhysRefs as well.
261 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
262 for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
263 PhysRefs.insert(*AI);
264
265 return !PhysRefs.empty();
266 }
267
PhysRegDefsReach(MachineInstr * CSMI,MachineInstr * MI,SmallSet<unsigned,8> & PhysRefs,SmallVectorImpl<unsigned> & PhysDefs,bool & NonLocal) const268 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
269 SmallSet<unsigned,8> &PhysRefs,
270 SmallVectorImpl<unsigned> &PhysDefs,
271 bool &NonLocal) const {
272 // For now conservatively returns false if the common subexpression is
273 // not in the same basic block as the given instruction. The only exception
274 // is if the common subexpression is in the sole predecessor block.
275 const MachineBasicBlock *MBB = MI->getParent();
276 const MachineBasicBlock *CSMBB = CSMI->getParent();
277
278 bool CrossMBB = false;
279 if (CSMBB != MBB) {
280 if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
281 return false;
282
283 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
284 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
285 // Avoid extending live range of physical registers if they are
286 //allocatable or reserved.
287 return false;
288 }
289 CrossMBB = true;
290 }
291 MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);
292 MachineBasicBlock::const_iterator E = MI;
293 MachineBasicBlock::const_iterator EE = CSMBB->end();
294 unsigned LookAheadLeft = LookAheadLimit;
295 while (LookAheadLeft) {
296 // Skip over dbg_value's.
297 while (I != E && I != EE && I->isDebugValue())
298 ++I;
299
300 if (I == EE) {
301 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
302 (void)CrossMBB;
303 CrossMBB = false;
304 NonLocal = true;
305 I = MBB->begin();
306 EE = MBB->end();
307 continue;
308 }
309
310 if (I == E)
311 return true;
312
313 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
314 const MachineOperand &MO = I->getOperand(i);
315 // RegMasks go on instructions like calls that clobber lots of physregs.
316 // Don't attempt to CSE across such an instruction.
317 if (MO.isRegMask())
318 return false;
319 if (!MO.isReg() || !MO.isDef())
320 continue;
321 unsigned MOReg = MO.getReg();
322 if (TargetRegisterInfo::isVirtualRegister(MOReg))
323 continue;
324 if (PhysRefs.count(MOReg))
325 return false;
326 }
327
328 --LookAheadLeft;
329 ++I;
330 }
331
332 return false;
333 }
334
isCSECandidate(MachineInstr * MI)335 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
336 if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||
337 MI->isInlineAsm() || MI->isDebugValue())
338 return false;
339
340 // Ignore copies.
341 if (MI->isCopyLike())
342 return false;
343
344 // Ignore stuff that we obviously can't move.
345 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
346 MI->hasUnmodeledSideEffects())
347 return false;
348
349 if (MI->mayLoad()) {
350 // Okay, this instruction does a load. As a refinement, we allow the target
351 // to decide whether the loaded value is actually a constant. If so, we can
352 // actually use it as a load.
353 if (!MI->isInvariantLoad(AA))
354 // FIXME: we should be able to hoist loads with no other side effects if
355 // there are no other instructions which can change memory in this loop.
356 // This is a trivial form of alias analysis.
357 return false;
358 }
359 return true;
360 }
361
362 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
363 /// common expression that defines Reg.
isProfitableToCSE(unsigned CSReg,unsigned Reg,MachineInstr * CSMI,MachineInstr * MI)364 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
365 MachineInstr *CSMI, MachineInstr *MI) {
366 // FIXME: Heuristics that works around the lack the live range splitting.
367
368 // If CSReg is used at all uses of Reg, CSE should not increase register
369 // pressure of CSReg.
370 bool MayIncreasePressure = true;
371 if (TargetRegisterInfo::isVirtualRegister(CSReg) &&
372 TargetRegisterInfo::isVirtualRegister(Reg)) {
373 MayIncreasePressure = false;
374 SmallPtrSet<MachineInstr*, 8> CSUses;
375 for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
376 CSUses.insert(&MI);
377 }
378 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
379 if (!CSUses.count(&MI)) {
380 MayIncreasePressure = true;
381 break;
382 }
383 }
384 }
385 if (!MayIncreasePressure) return true;
386
387 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
388 // an immediate predecessor. We don't want to increase register pressure and
389 // end up causing other computation to be spilled.
390 if (TII->isAsCheapAsAMove(MI)) {
391 MachineBasicBlock *CSBB = CSMI->getParent();
392 MachineBasicBlock *BB = MI->getParent();
393 if (CSBB != BB && !CSBB->isSuccessor(BB))
394 return false;
395 }
396
397 // Heuristics #2: If the expression doesn't not use a vr and the only use
398 // of the redundant computation are copies, do not cse.
399 bool HasVRegUse = false;
400 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
401 const MachineOperand &MO = MI->getOperand(i);
402 if (MO.isReg() && MO.isUse() &&
403 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
404 HasVRegUse = true;
405 break;
406 }
407 }
408 if (!HasVRegUse) {
409 bool HasNonCopyUse = false;
410 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
411 // Ignore copies.
412 if (!MI.isCopyLike()) {
413 HasNonCopyUse = true;
414 break;
415 }
416 }
417 if (!HasNonCopyUse)
418 return false;
419 }
420
421 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
422 // it unless the defined value is already used in the BB of the new use.
423 bool HasPHI = false;
424 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
425 for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
426 HasPHI |= MI.isPHI();
427 CSBBs.insert(MI.getParent());
428 }
429
430 if (!HasPHI)
431 return true;
432 return CSBBs.count(MI->getParent());
433 }
434
EnterScope(MachineBasicBlock * MBB)435 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
436 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
437 ScopeType *Scope = new ScopeType(VNT);
438 ScopeMap[MBB] = Scope;
439 }
440
ExitScope(MachineBasicBlock * MBB)441 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
442 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
443 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
444 assert(SI != ScopeMap.end());
445 delete SI->second;
446 ScopeMap.erase(SI);
447 }
448
ProcessBlock(MachineBasicBlock * MBB)449 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
450 bool Changed = false;
451
452 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
453 SmallVector<unsigned, 2> ImplicitDefsToUpdate;
454 SmallVector<unsigned, 2> ImplicitDefs;
455 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
456 MachineInstr *MI = &*I;
457 ++I;
458
459 if (!isCSECandidate(MI))
460 continue;
461
462 bool FoundCSE = VNT.count(MI);
463 if (!FoundCSE) {
464 // Using trivial copy propagation to find more CSE opportunities.
465 if (PerformTrivialCopyPropagation(MI, MBB)) {
466 Changed = true;
467
468 // After coalescing MI itself may become a copy.
469 if (MI->isCopyLike())
470 continue;
471
472 // Try again to see if CSE is possible.
473 FoundCSE = VNT.count(MI);
474 }
475 }
476
477 // Commute commutable instructions.
478 bool Commuted = false;
479 if (!FoundCSE && MI->isCommutable()) {
480 MachineInstr *NewMI = TII->commuteInstruction(MI);
481 if (NewMI) {
482 Commuted = true;
483 FoundCSE = VNT.count(NewMI);
484 if (NewMI != MI) {
485 // New instruction. It doesn't need to be kept.
486 NewMI->eraseFromParent();
487 Changed = true;
488 } else if (!FoundCSE)
489 // MI was changed but it didn't help, commute it back!
490 (void)TII->commuteInstruction(MI);
491 }
492 }
493
494 // If the instruction defines physical registers and the values *may* be
495 // used, then it's not safe to replace it with a common subexpression.
496 // It's also not safe if the instruction uses physical registers.
497 bool CrossMBBPhysDef = false;
498 SmallSet<unsigned, 8> PhysRefs;
499 SmallVector<unsigned, 2> PhysDefs;
500 bool PhysUseDef = false;
501 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
502 PhysDefs, PhysUseDef)) {
503 FoundCSE = false;
504
505 // ... Unless the CS is local or is in the sole predecessor block
506 // and it also defines the physical register which is not clobbered
507 // in between and the physical register uses were not clobbered.
508 // This can never be the case if the instruction both uses and
509 // defines the same physical register, which was detected above.
510 if (!PhysUseDef) {
511 unsigned CSVN = VNT.lookup(MI);
512 MachineInstr *CSMI = Exps[CSVN];
513 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
514 FoundCSE = true;
515 }
516 }
517
518 if (!FoundCSE) {
519 VNT.insert(MI, CurrVN++);
520 Exps.push_back(MI);
521 continue;
522 }
523
524 // Found a common subexpression, eliminate it.
525 unsigned CSVN = VNT.lookup(MI);
526 MachineInstr *CSMI = Exps[CSVN];
527 DEBUG(dbgs() << "Examining: " << *MI);
528 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
529
530 // Check if it's profitable to perform this CSE.
531 bool DoCSE = true;
532 unsigned NumDefs = MI->getDesc().getNumDefs() +
533 MI->getDesc().getNumImplicitDefs();
534
535 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
536 MachineOperand &MO = MI->getOperand(i);
537 if (!MO.isReg() || !MO.isDef())
538 continue;
539 unsigned OldReg = MO.getReg();
540 unsigned NewReg = CSMI->getOperand(i).getReg();
541
542 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
543 // we should make sure it is not dead at CSMI.
544 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
545 ImplicitDefsToUpdate.push_back(i);
546
547 // Keep track of implicit defs of CSMI and MI, to clear possibly
548 // made-redundant kill flags.
549 if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
550 ImplicitDefs.push_back(OldReg);
551
552 if (OldReg == NewReg) {
553 --NumDefs;
554 continue;
555 }
556
557 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
558 TargetRegisterInfo::isVirtualRegister(NewReg) &&
559 "Do not CSE physical register defs!");
560
561 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
562 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
563 DoCSE = false;
564 break;
565 }
566
567 // Don't perform CSE if the result of the old instruction cannot exist
568 // within the register class of the new instruction.
569 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
570 if (!MRI->constrainRegClass(NewReg, OldRC)) {
571 DEBUG(dbgs() << "*** Not the same register class, avoid CSE!\n");
572 DoCSE = false;
573 break;
574 }
575
576 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
577 --NumDefs;
578 }
579
580 // Actually perform the elimination.
581 if (DoCSE) {
582 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
583 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
584 MRI->clearKillFlags(CSEPairs[i].second);
585 }
586
587 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
588 // we should make sure it is not dead at CSMI.
589 for (unsigned i = 0, e = ImplicitDefsToUpdate.size(); i != e; ++i)
590 CSMI->getOperand(ImplicitDefsToUpdate[i]).setIsDead(false);
591
592 // Go through implicit defs of CSMI and MI, and clear the kill flags on
593 // their uses in all the instructions between CSMI and MI.
594 // We might have made some of the kill flags redundant, consider:
595 // subs ... %NZCV<imp-def> <- CSMI
596 // csinc ... %NZCV<imp-use,kill> <- this kill flag isn't valid anymore
597 // subs ... %NZCV<imp-def> <- MI, to be eliminated
598 // csinc ... %NZCV<imp-use,kill>
599 // Since we eliminated MI, and reused a register imp-def'd by CSMI
600 // (here %NZCV), that register, if it was killed before MI, should have
601 // that kill flag removed, because it's lifetime was extended.
602 if (CSMI->getParent() == MI->getParent()) {
603 for (MachineBasicBlock::iterator II = CSMI, IE = MI; II != IE; ++II)
604 for (auto ImplicitDef : ImplicitDefs)
605 if (MachineOperand *MO = II->findRegisterUseOperand(
606 ImplicitDef, /*isKill=*/true, TRI))
607 MO->setIsKill(false);
608 } else {
609 // If the instructions aren't in the same BB, bail out and clear the
610 // kill flag on all uses of the imp-def'd register.
611 for (auto ImplicitDef : ImplicitDefs)
612 MRI->clearKillFlags(ImplicitDef);
613 }
614
615 if (CrossMBBPhysDef) {
616 // Add physical register defs now coming in from a predecessor to MBB
617 // livein list.
618 while (!PhysDefs.empty()) {
619 unsigned LiveIn = PhysDefs.pop_back_val();
620 if (!MBB->isLiveIn(LiveIn))
621 MBB->addLiveIn(LiveIn);
622 }
623 ++NumCrossBBCSEs;
624 }
625
626 MI->eraseFromParent();
627 ++NumCSEs;
628 if (!PhysRefs.empty())
629 ++NumPhysCSEs;
630 if (Commuted)
631 ++NumCommutes;
632 Changed = true;
633 } else {
634 VNT.insert(MI, CurrVN++);
635 Exps.push_back(MI);
636 }
637 CSEPairs.clear();
638 ImplicitDefsToUpdate.clear();
639 ImplicitDefs.clear();
640 }
641
642 return Changed;
643 }
644
645 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
646 /// dominator tree node if its a leaf or all of its children are done. Walk
647 /// up the dominator tree to destroy ancestors which are now done.
648 void
ExitScopeIfDone(MachineDomTreeNode * Node,DenseMap<MachineDomTreeNode *,unsigned> & OpenChildren)649 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
650 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
651 if (OpenChildren[Node])
652 return;
653
654 // Pop scope.
655 ExitScope(Node->getBlock());
656
657 // Now traverse upwards to pop ancestors whose offsprings are all done.
658 while (MachineDomTreeNode *Parent = Node->getIDom()) {
659 unsigned Left = --OpenChildren[Parent];
660 if (Left != 0)
661 break;
662 ExitScope(Parent->getBlock());
663 Node = Parent;
664 }
665 }
666
PerformCSE(MachineDomTreeNode * Node)667 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
668 SmallVector<MachineDomTreeNode*, 32> Scopes;
669 SmallVector<MachineDomTreeNode*, 8> WorkList;
670 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
671
672 CurrVN = 0;
673
674 // Perform a DFS walk to determine the order of visit.
675 WorkList.push_back(Node);
676 do {
677 Node = WorkList.pop_back_val();
678 Scopes.push_back(Node);
679 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
680 unsigned NumChildren = Children.size();
681 OpenChildren[Node] = NumChildren;
682 for (unsigned i = 0; i != NumChildren; ++i) {
683 MachineDomTreeNode *Child = Children[i];
684 WorkList.push_back(Child);
685 }
686 } while (!WorkList.empty());
687
688 // Now perform CSE.
689 bool Changed = false;
690 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
691 MachineDomTreeNode *Node = Scopes[i];
692 MachineBasicBlock *MBB = Node->getBlock();
693 EnterScope(MBB);
694 Changed |= ProcessBlock(MBB);
695 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
696 ExitScopeIfDone(Node, OpenChildren);
697 }
698
699 return Changed;
700 }
701
runOnMachineFunction(MachineFunction & MF)702 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
703 if (skipOptnoneFunction(*MF.getFunction()))
704 return false;
705
706 TII = MF.getSubtarget().getInstrInfo();
707 TRI = MF.getSubtarget().getRegisterInfo();
708 MRI = &MF.getRegInfo();
709 AA = &getAnalysis<AliasAnalysis>();
710 DT = &getAnalysis<MachineDominatorTree>();
711 return PerformCSE(DT->getRootNode());
712 }
713