1 //===-- XtensaMCTargetDesc.h - Xtensa Target Descriptions -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6 // See https://llvm.org/LICENSE.txt for license information. 7 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 // This file provides Xtensa specific target descriptions. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAMCTARGETDESC_H 16 #define LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAMCTARGETDESC_H 17 #include "llvm/Support/DataTypes.h" 18 #include <memory> 19 20 namespace llvm { 21 22 class MCAsmBackend; 23 class MCCodeEmitter; 24 class MCContext; 25 class MCInstrInfo; 26 class MCObjectTargetWriter; 27 class MCObjectWriter; 28 class MCRegisterInfo; 29 class MCSubtargetInfo; 30 class MCTargetOptions; 31 class MachineInstr; 32 class StringRef; 33 class Target; 34 class raw_ostream; 35 36 extern Target TheXtensaTarget; 37 38 MCCodeEmitter *createXtensaMCCodeEmitter(const MCInstrInfo &MCII, 39 MCContext &Ctx); 40 41 MCAsmBackend *createXtensaMCAsmBackend(const Target &T, 42 const MCSubtargetInfo &STI, 43 const MCRegisterInfo &MRI, 44 const MCTargetOptions &Options); 45 std::unique_ptr<MCObjectTargetWriter> 46 createXtensaObjectWriter(uint8_t OSABI, bool IsLittleEndian); 47 48 namespace Xtensa { 49 // Check address offset for load/store instructions. 50 // The offset should be multiple of scale. 51 bool isValidAddrOffset(int Scale, int64_t OffsetVal); 52 53 // Check address offset for load/store instructions. 54 bool isValidAddrOffsetForOpcode(unsigned Opcode, int64_t Offset); 55 } // namespace Xtensa 56 } // end namespace llvm 57 58 // Defines symbolic names for Xtensa registers. 59 // This defines a mapping from register name to register number. 60 #define GET_REGINFO_ENUM 61 #include "XtensaGenRegisterInfo.inc" 62 63 // Defines symbolic names for the Xtensa instructions. 64 #define GET_INSTRINFO_ENUM 65 #include "XtensaGenInstrInfo.inc" 66 67 #define GET_SUBTARGETINFO_ENUM 68 #include "XtensaGenSubtargetInfo.inc" 69 70 #endif // LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAMCTARGETDESC_H 71