xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=GCN %s
3
4# FIXME: Need to deal with constant bus restriction
5# ---
6# name: mbcnt_lo_ss
7# legalized: true
8# regBankSelected: true
9
10# body: |
11#   bb.0:
12#     liveins: $sgpr0, $sgpr1
13#     %0:sgpr(s32) = COPY $sgpr0
14#     %1:sgpr(s32) = COPY $sgpr1
15#     %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
16#     S_ENDPGM 0, implicit %2
17# ...
18
19---
20name: mbcnt_lo_sv
21legalized: true
22regBankSelected: true
23
24body: |
25  bb.0:
26    liveins: $sgpr0, $vgpr0
27    ; GCN-LABEL: name: mbcnt_lo_sv
28    ; GCN: liveins: $sgpr0, $vgpr0
29    ; GCN-NEXT: {{  $}}
30    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
31    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
32    ; GCN-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
33    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
34    %0:sgpr(s32) = COPY $sgpr0
35    %1:vgpr(s32) = COPY $vgpr0
36    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
37    S_ENDPGM 0, implicit %2
38...
39
40---
41name: smin_s32_vs
42legalized: true
43regBankSelected: true
44
45body: |
46  bb.0:
47    liveins: $sgpr0, $vgpr0
48    ; GCN-LABEL: name: smin_s32_vs
49    ; GCN: liveins: $sgpr0, $vgpr0
50    ; GCN-NEXT: {{  $}}
51    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
52    ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
53    ; GCN-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
54    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
55    %0:vgpr(s32) = COPY $vgpr0
56    %1:sgpr(s32) = COPY $sgpr0
57    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
58    S_ENDPGM 0, implicit %2
59...
60
61---
62name: smin_s32_vv
63legalized: true
64regBankSelected: true
65
66body: |
67  bb.0:
68    liveins: $vgpr0, $vgpr1
69    ; GCN-LABEL: name: smin_s32_vv
70    ; GCN: liveins: $vgpr0, $vgpr1
71    ; GCN-NEXT: {{  $}}
72    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
73    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
74    ; GCN-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
75    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
76    %0:vgpr(s32) = COPY $vgpr0
77    %1:vgpr(s32) = COPY $vgpr1
78    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
79    S_ENDPGM 0, implicit %2
80...
81