1 //===-- EmulateInstructionARM64.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "EmulateInstructionARM64.h"
10
11 #include "lldb/Core/Address.h"
12 #include "lldb/Core/PluginManager.h"
13 #include "lldb/Symbol/UnwindPlan.h"
14 #include "lldb/Utility/ArchSpec.h"
15 #include "lldb/Utility/ConstString.h"
16 #include "lldb/Utility/RegisterValue.h"
17 #include "lldb/Utility/Stream.h"
18
19 #include "llvm/Support/CheckedArithmetic.h"
20
21 #include "Plugins/Process/Utility/ARMDefines.h"
22 #include "Plugins/Process/Utility/ARMUtils.h"
23 #include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
24
25 #include <cstdlib>
26 #include <optional>
27
28 #define GPR_OFFSET(idx) ((idx)*8)
29 #define GPR_OFFSET_NAME(reg) 0
30 #define FPU_OFFSET(idx) ((idx)*16)
31 #define FPU_OFFSET_NAME(reg) 0
32 #define EXC_OFFSET_NAME(reg) 0
33 #define DBG_OFFSET_NAME(reg) 0
34 #define DBG_OFFSET_NAME(reg) 0
35 #define DEFINE_DBG(re, y) \
36 "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \
37 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
38 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM}, \
39 nullptr, nullptr
40
41 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
42
43 #include "Plugins/Process/Utility/RegisterInfos_arm64.h"
44
45 #include "llvm/ADT/STLExtras.h"
46 #include "llvm/Support/MathExtras.h"
47
48 #include "Plugins/Process/Utility/InstructionUtils.h"
49
50 using namespace lldb;
51 using namespace lldb_private;
52
LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionARM64,InstructionARM64)53 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionARM64, InstructionARM64)
54
55 static std::optional<RegisterInfo> LLDBTableGetRegisterInfo(uint32_t reg_num) {
56 if (reg_num >= std::size(g_register_infos_arm64_le))
57 return {};
58 return g_register_infos_arm64_le[reg_num];
59 }
60
61 #define No_VFP 0
62 #define VFPv1 (1u << 1)
63 #define VFPv2 (1u << 2)
64 #define VFPv3 (1u << 3)
65 #define AdvancedSIMD (1u << 4)
66
67 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
68 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
69 #define VFPv2v3 (VFPv2 | VFPv3)
70
71 #define UInt(x) ((uint64_t)x)
72 #define SInt(x) ((int64_t)x)
73 #define bit bool
74 #define boolean bool
75 #define integer int64_t
76
IsZero(uint64_t x)77 static inline bool IsZero(uint64_t x) { return x == 0; }
78
NOT(uint64_t x)79 static inline uint64_t NOT(uint64_t x) { return ~x; }
80
81 // LSL()
82 // =====
83
LSL(uint64_t x,integer shift)84 static inline uint64_t LSL(uint64_t x, integer shift) {
85 if (shift == 0)
86 return x;
87 return x << shift;
88 }
89
90 // ConstrainUnpredictable()
91 // ========================
92
93 EmulateInstructionARM64::ConstraintType
ConstrainUnpredictable(EmulateInstructionARM64::Unpredictable which)94 ConstrainUnpredictable(EmulateInstructionARM64::Unpredictable which) {
95 EmulateInstructionARM64::ConstraintType result =
96 EmulateInstructionARM64::Constraint_UNKNOWN;
97 switch (which) {
98 case EmulateInstructionARM64::Unpredictable_WBOVERLAP:
99 case EmulateInstructionARM64::Unpredictable_LDPOVERLAP:
100 // TODO: don't know what to really do here? Pseudo code says:
101 // set result to one of above Constraint behaviours or UNDEFINED
102 break;
103 }
104 return result;
105 }
106
107 //
108 // EmulateInstructionARM implementation
109 //
110
Initialize()111 void EmulateInstructionARM64::Initialize() {
112 PluginManager::RegisterPlugin(GetPluginNameStatic(),
113 GetPluginDescriptionStatic(), CreateInstance);
114 }
115
Terminate()116 void EmulateInstructionARM64::Terminate() {
117 PluginManager::UnregisterPlugin(CreateInstance);
118 }
119
GetPluginDescriptionStatic()120 llvm::StringRef EmulateInstructionARM64::GetPluginDescriptionStatic() {
121 return "Emulate instructions for the ARM64 architecture.";
122 }
123
124 EmulateInstruction *
CreateInstance(const ArchSpec & arch,InstructionType inst_type)125 EmulateInstructionARM64::CreateInstance(const ArchSpec &arch,
126 InstructionType inst_type) {
127 if (EmulateInstructionARM64::SupportsEmulatingInstructionsOfTypeStatic(
128 inst_type)) {
129 if (arch.GetTriple().getArch() == llvm::Triple::aarch64 ||
130 arch.GetTriple().getArch() == llvm::Triple::aarch64_32) {
131 return new EmulateInstructionARM64(arch);
132 }
133 }
134
135 return nullptr;
136 }
137
SetTargetTriple(const ArchSpec & arch)138 bool EmulateInstructionARM64::SetTargetTriple(const ArchSpec &arch) {
139 if (arch.GetTriple().getArch() == llvm::Triple::arm)
140 return true;
141 else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
142 return true;
143
144 return false;
145 }
146
147 std::optional<RegisterInfo>
GetRegisterInfo(RegisterKind reg_kind,uint32_t reg_num)148 EmulateInstructionARM64::GetRegisterInfo(RegisterKind reg_kind,
149 uint32_t reg_num) {
150 if (reg_kind == eRegisterKindGeneric) {
151 switch (reg_num) {
152 case LLDB_REGNUM_GENERIC_PC:
153 reg_kind = eRegisterKindLLDB;
154 reg_num = gpr_pc_arm64;
155 break;
156 case LLDB_REGNUM_GENERIC_SP:
157 reg_kind = eRegisterKindLLDB;
158 reg_num = gpr_sp_arm64;
159 break;
160 case LLDB_REGNUM_GENERIC_FP:
161 reg_kind = eRegisterKindLLDB;
162 reg_num = gpr_fp_arm64;
163 break;
164 case LLDB_REGNUM_GENERIC_RA:
165 reg_kind = eRegisterKindLLDB;
166 reg_num = gpr_lr_arm64;
167 break;
168 case LLDB_REGNUM_GENERIC_FLAGS:
169 reg_kind = eRegisterKindLLDB;
170 reg_num = gpr_cpsr_arm64;
171 break;
172
173 default:
174 return {};
175 }
176 }
177
178 if (reg_kind == eRegisterKindLLDB)
179 return LLDBTableGetRegisterInfo(reg_num);
180 return {};
181 }
182
183 EmulateInstructionARM64::Opcode *
GetOpcodeForInstruction(const uint32_t opcode)184 EmulateInstructionARM64::GetOpcodeForInstruction(const uint32_t opcode) {
185 static EmulateInstructionARM64::Opcode g_opcodes[] = {
186 // Prologue instructions
187
188 // push register(s)
189 {0xff000000, 0xd1000000, No_VFP,
190 &EmulateInstructionARM64::EmulateADDSUBImm,
191 "SUB <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"},
192 {0xff000000, 0xf1000000, No_VFP,
193 &EmulateInstructionARM64::EmulateADDSUBImm,
194 "SUBS <Xd>, <Xn|SP>, #<imm> {, <shift>}"},
195 {0xff000000, 0x91000000, No_VFP,
196 &EmulateInstructionARM64::EmulateADDSUBImm,
197 "ADD <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"},
198 {0xff000000, 0xb1000000, No_VFP,
199 &EmulateInstructionARM64::EmulateADDSUBImm,
200 "ADDS <Xd>, <Xn|SP>, #<imm> {, <shift>}"},
201
202 {0xff000000, 0x51000000, No_VFP,
203 &EmulateInstructionARM64::EmulateADDSUBImm,
204 "SUB <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"},
205 {0xff000000, 0x71000000, No_VFP,
206 &EmulateInstructionARM64::EmulateADDSUBImm,
207 "SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"},
208 {0xff000000, 0x11000000, No_VFP,
209 &EmulateInstructionARM64::EmulateADDSUBImm,
210 "ADD <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"},
211 {0xff000000, 0x31000000, No_VFP,
212 &EmulateInstructionARM64::EmulateADDSUBImm,
213 "ADDS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"},
214
215 {0xffc00000, 0x29000000, No_VFP,
216 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
217 "STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"},
218 {0xffc00000, 0xa9000000, No_VFP,
219 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
220 "STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"},
221 {0xffc00000, 0x2d000000, No_VFP,
222 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
223 "STP <St>, <St2>, [<Xn|SP>{, #<imm>}]"},
224 {0xffc00000, 0x6d000000, No_VFP,
225 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
226 "STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"},
227 {0xffc00000, 0xad000000, No_VFP,
228 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
229 "STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"},
230
231 {0xffc00000, 0x29800000, No_VFP,
232 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
233 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
234 {0xffc00000, 0xa9800000, No_VFP,
235 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
236 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
237 {0xffc00000, 0x2d800000, No_VFP,
238 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
239 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"},
240 {0xffc00000, 0x6d800000, No_VFP,
241 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
242 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
243 {0xffc00000, 0xad800000, No_VFP,
244 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
245 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
246
247 {0xffc00000, 0x28800000, No_VFP,
248 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
249 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
250 {0xffc00000, 0xa8800000, No_VFP,
251 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
252 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
253 {0xffc00000, 0x2c800000, No_VFP,
254 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
255 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"},
256 {0xffc00000, 0x6c800000, No_VFP,
257 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
258 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
259 {0xffc00000, 0xac800000, No_VFP,
260 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
261 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
262
263 {0xffc00000, 0x29400000, No_VFP,
264 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
265 "LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"},
266 {0xffc00000, 0xa9400000, No_VFP,
267 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
268 "LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"},
269 {0xffc00000, 0x2d400000, No_VFP,
270 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
271 "LDP <St>, <St2>, [<Xn|SP>{, #<imm>}]"},
272 {0xffc00000, 0x6d400000, No_VFP,
273 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
274 "LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"},
275 {0xffc00000, 0xad400000, No_VFP,
276 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
277 "LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"},
278
279 {0xffc00000, 0x29c00000, No_VFP,
280 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
281 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
282 {0xffc00000, 0xa9c00000, No_VFP,
283 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
284 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
285 {0xffc00000, 0x2dc00000, No_VFP,
286 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
287 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"},
288 {0xffc00000, 0x6dc00000, No_VFP,
289 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
290 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
291 {0xffc00000, 0xadc00000, No_VFP,
292 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
293 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
294
295 {0xffc00000, 0x28c00000, No_VFP,
296 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
297 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
298 {0xffc00000, 0xa8c00000, No_VFP,
299 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
300 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
301 {0xffc00000, 0x2cc00000, No_VFP,
302 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
303 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"},
304 {0xffc00000, 0x6cc00000, No_VFP,
305 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
306 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
307 {0xffc00000, 0xacc00000, No_VFP,
308 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
309 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
310
311 {0xffe00c00, 0xb8000400, No_VFP,
312 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
313 "STR <Wt>, [<Xn|SP>], #<simm>"},
314 {0xffe00c00, 0xf8000400, No_VFP,
315 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
316 "STR <Xt>, [<Xn|SP>], #<simm>"},
317 {0xffe00c00, 0xb8000c00, No_VFP,
318 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
319 "STR <Wt>, [<Xn|SP>, #<simm>]!"},
320 {0xffe00c00, 0xf8000c00, No_VFP,
321 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
322 "STR <Xt>, [<Xn|SP>, #<simm>]!"},
323 {0xffc00000, 0xb9000000, No_VFP,
324 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
325 "STR <Wt>, [<Xn|SP>{, #<pimm>}]"},
326 {0xffc00000, 0xf9000000, No_VFP,
327 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
328 "STR <Xt>, [<Xn|SP>{, #<pimm>}]"},
329
330 {0xffe00c00, 0xb8400400, No_VFP,
331 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
332 "LDR <Wt>, [<Xn|SP>], #<simm>"},
333 {0xffe00c00, 0xf8400400, No_VFP,
334 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
335 "LDR <Xt>, [<Xn|SP>], #<simm>"},
336 {0xffe00c00, 0xb8400c00, No_VFP,
337 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
338 "LDR <Wt>, [<Xn|SP>, #<simm>]!"},
339 {0xffe00c00, 0xf8400c00, No_VFP,
340 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
341 "LDR <Xt>, [<Xn|SP>, #<simm>]!"},
342 {0xffc00000, 0xb9400000, No_VFP,
343 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
344 "LDR <Wt>, [<Xn|SP>{, #<pimm>}]"},
345 {0xffc00000, 0xf9400000, No_VFP,
346 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
347 "LDR <Xt>, [<Xn|SP>{, #<pimm>}]"},
348
349 {0xfc000000, 0x14000000, No_VFP, &EmulateInstructionARM64::EmulateB,
350 "B <label>"},
351 {0xff000010, 0x54000000, No_VFP, &EmulateInstructionARM64::EmulateBcond,
352 "B.<cond> <label>"},
353 {0x7f000000, 0x34000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ,
354 "CBZ <Wt>, <label>"},
355 {0x7f000000, 0x35000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ,
356 "CBNZ <Wt>, <label>"},
357 {0x7f000000, 0x36000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ,
358 "TBZ <R><t>, #<imm>, <label>"},
359 {0x7f000000, 0x37000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ,
360 "TBNZ <R><t>, #<imm>, <label>"},
361
362 };
363 static const size_t k_num_arm_opcodes = std::size(g_opcodes);
364
365 for (size_t i = 0; i < k_num_arm_opcodes; ++i) {
366 if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value)
367 return &g_opcodes[i];
368 }
369 return nullptr;
370 }
371
ReadInstruction()372 bool EmulateInstructionARM64::ReadInstruction() {
373 bool success = false;
374 m_addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC,
375 LLDB_INVALID_ADDRESS, &success);
376 if (success) {
377 Context read_inst_context;
378 read_inst_context.type = eContextReadOpcode;
379 read_inst_context.SetNoArgs();
380 m_opcode.SetOpcode32(
381 ReadMemoryUnsigned(read_inst_context, m_addr, 4, 0, &success),
382 GetByteOrder());
383 }
384 if (!success)
385 m_addr = LLDB_INVALID_ADDRESS;
386 return success;
387 }
388
EvaluateInstruction(uint32_t evaluate_options)389 bool EmulateInstructionARM64::EvaluateInstruction(uint32_t evaluate_options) {
390 const uint32_t opcode = m_opcode.GetOpcode32();
391 Opcode *opcode_data = GetOpcodeForInstruction(opcode);
392 if (opcode_data == nullptr)
393 return false;
394
395 const bool auto_advance_pc =
396 evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
397 m_ignore_conditions =
398 evaluate_options & eEmulateInstructionOptionIgnoreConditions;
399
400 bool success = false;
401
402 // Only return false if we are unable to read the CPSR if we care about
403 // conditions
404 if (!success && !m_ignore_conditions)
405 return false;
406
407 uint32_t orig_pc_value = 0;
408 if (auto_advance_pc) {
409 orig_pc_value =
410 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success);
411 if (!success)
412 return false;
413 }
414
415 // Call the Emulate... function.
416 success = (this->*opcode_data->callback)(opcode);
417 if (!success)
418 return false;
419
420 if (auto_advance_pc) {
421 uint32_t new_pc_value =
422 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success);
423 if (!success)
424 return false;
425
426 if (new_pc_value == orig_pc_value) {
427 EmulateInstruction::Context context;
428 context.type = eContextAdvancePC;
429 context.SetNoArgs();
430 if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_pc_arm64,
431 orig_pc_value + 4))
432 return false;
433 }
434 }
435 return true;
436 }
437
CreateFunctionEntryUnwind(UnwindPlan & unwind_plan)438 bool EmulateInstructionARM64::CreateFunctionEntryUnwind(
439 UnwindPlan &unwind_plan) {
440 unwind_plan.Clear();
441 unwind_plan.SetRegisterKind(eRegisterKindLLDB);
442
443 UnwindPlan::RowSP row(new UnwindPlan::Row);
444
445 // Our previous Call Frame Address is the stack pointer
446 row->GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_arm64, 0);
447
448 unwind_plan.AppendRow(row);
449 unwind_plan.SetSourceName("EmulateInstructionARM64");
450 unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
451 unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes);
452 unwind_plan.SetUnwindPlanForSignalTrap(eLazyBoolNo);
453 unwind_plan.SetReturnAddressRegister(gpr_lr_arm64);
454 return true;
455 }
456
GetFramePointerRegisterNumber() const457 uint32_t EmulateInstructionARM64::GetFramePointerRegisterNumber() const {
458 if (m_arch.GetTriple().isAndroid())
459 return LLDB_INVALID_REGNUM; // Don't use frame pointer on android
460
461 return gpr_fp_arm64;
462 }
463
UsingAArch32()464 bool EmulateInstructionARM64::UsingAArch32() {
465 bool aarch32 = m_opcode_pstate.RW == 1;
466 // if !HaveAnyAArch32() then assert !aarch32;
467 // if HighestELUsingAArch32() then assert aarch32;
468 return aarch32;
469 }
470
BranchTo(const Context & context,uint32_t N,addr_t target)471 bool EmulateInstructionARM64::BranchTo(const Context &context, uint32_t N,
472 addr_t target) {
473 #if 0
474 // Set program counter to a new address, with a branch reason hint for
475 // possible use by hardware fetching the next instruction.
476 BranchTo(bits(N) target, BranchType branch_type)
477 Hint_Branch(branch_type);
478 if N == 32 then
479 assert UsingAArch32();
480 _PC = ZeroExtend(target);
481 else
482 assert N == 64 && !UsingAArch32();
483 // Remove the tag bits from a tagged target
484 case PSTATE.EL of
485 when EL0, EL1
486 if target<55> == '1' && TCR_EL1.TBI1 == '1' then
487 target<63:56> = '11111111';
488 if target<55> == '0' && TCR_EL1.TBI0 == '1' then
489 target<63:56> = '00000000';
490 when EL2
491 if TCR_EL2.TBI == '1' then
492 target<63:56> = '00000000';
493 when EL3
494 if TCR_EL3.TBI == '1' then
495 target<63:56> = '00000000';
496 _PC = target<63:0>;
497 return;
498 #endif
499
500 addr_t addr;
501
502 // Hint_Branch(branch_type);
503 if (N == 32) {
504 if (!UsingAArch32())
505 return false;
506 addr = target;
507 } else if (N == 64) {
508 if (UsingAArch32())
509 return false;
510 // TODO: Remove the tag bits from a tagged target
511 addr = target;
512 } else
513 return false;
514
515 return WriteRegisterUnsigned(context, eRegisterKindGeneric,
516 LLDB_REGNUM_GENERIC_PC, addr);
517 }
518
ConditionHolds(const uint32_t cond)519 bool EmulateInstructionARM64::ConditionHolds(const uint32_t cond) {
520 // If we are ignoring conditions, then always return true. this allows us to
521 // iterate over disassembly code and still emulate an instruction even if we
522 // don't have all the right bits set in the CPSR register...
523 if (m_ignore_conditions)
524 return true;
525
526 bool result = false;
527 switch (UnsignedBits(cond, 3, 1)) {
528 case 0:
529 result = (m_opcode_pstate.Z == 1);
530 break;
531 case 1:
532 result = (m_opcode_pstate.C == 1);
533 break;
534 case 2:
535 result = (m_opcode_pstate.N == 1);
536 break;
537 case 3:
538 result = (m_opcode_pstate.V == 1);
539 break;
540 case 4:
541 result = (m_opcode_pstate.C == 1 && m_opcode_pstate.Z == 0);
542 break;
543 case 5:
544 result = (m_opcode_pstate.N == m_opcode_pstate.V);
545 break;
546 case 6:
547 result = (m_opcode_pstate.N == m_opcode_pstate.V && m_opcode_pstate.Z == 0);
548 break;
549 case 7:
550 // Always execute (cond == 0b1110, or the special 0b1111 which gives
551 // opcodes different meanings, but always means execution happens.
552 return true;
553 }
554
555 if (cond & 1)
556 result = !result;
557 return result;
558 }
559
560 uint64_t EmulateInstructionARM64::
AddWithCarry(uint32_t N,uint64_t x,uint64_t y,bit carry_in,EmulateInstructionARM64::ProcState & proc_state)561 AddWithCarry(uint32_t N, uint64_t x, uint64_t y, bit carry_in,
562 EmulateInstructionARM64::ProcState &proc_state) {
563 uint64_t unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in);
564 std::optional<int64_t> signed_sum = llvm::checkedAdd(SInt(x), SInt(y));
565 bool overflow = !signed_sum;
566 if (!overflow)
567 overflow |= !llvm::checkedAdd(*signed_sum, SInt(carry_in));
568 uint64_t result = unsigned_sum;
569 if (N < 64)
570 result = Bits64(result, N - 1, 0);
571 proc_state.N = Bit64(result, N - 1);
572 proc_state.Z = IsZero(result);
573 proc_state.C = UInt(result) != unsigned_sum;
574 proc_state.V = overflow;
575 return result;
576 }
577
EmulateADDSUBImm(const uint32_t opcode)578 bool EmulateInstructionARM64::EmulateADDSUBImm(const uint32_t opcode) {
579 // integer d = UInt(Rd);
580 // integer n = UInt(Rn);
581 // integer datasize = if sf == 1 then 64 else 32;
582 // boolean sub_op = (op == 1);
583 // boolean setflags = (S == 1);
584 // bits(datasize) imm;
585 //
586 // case shift of
587 // when '00' imm = ZeroExtend(imm12, datasize);
588 // when '01' imm = ZeroExtend(imm12 : Zeros(12), datasize);
589 // when '1x' UNDEFINED;
590 //
591 //
592 // bits(datasize) result;
593 // bits(datasize) operand1 = if n == 31 then SP[] else X[n];
594 // bits(datasize) operand2 = imm;
595 // bits(4) nzcv;
596 // bit carry_in;
597 //
598 // if sub_op then
599 // operand2 = NOT(operand2);
600 // carry_in = 1;
601 // else
602 // carry_in = 0;
603 //
604 // (result, nzcv) = AddWithCarry(operand1, operand2, carry_in);
605 //
606 // if setflags then
607 // PSTATE.NZCV = nzcv;
608 //
609 // if d == 31 && !setflags then
610 // SP[] = result;
611 // else
612 // X[d] = result;
613
614 const uint32_t sf = Bit32(opcode, 31);
615 const uint32_t op = Bit32(opcode, 30);
616 const uint32_t S = Bit32(opcode, 29);
617 const uint32_t shift = Bits32(opcode, 23, 22);
618 const uint32_t imm12 = Bits32(opcode, 21, 10);
619 const uint32_t Rn = Bits32(opcode, 9, 5);
620 const uint32_t Rd = Bits32(opcode, 4, 0);
621
622 bool success = false;
623
624 const uint32_t d = UInt(Rd);
625 const uint32_t n = UInt(Rn);
626 const uint32_t datasize = (sf == 1) ? 64 : 32;
627 boolean sub_op = op == 1;
628 boolean setflags = S == 1;
629 uint64_t imm;
630
631 switch (shift) {
632 case 0:
633 imm = imm12;
634 break;
635 case 1:
636 imm = static_cast<uint64_t>(imm12) << 12;
637 break;
638 default:
639 return false; // UNDEFINED;
640 }
641 uint64_t result;
642 uint64_t operand1 =
643 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
644 uint64_t operand2 = imm;
645 bit carry_in;
646
647 if (sub_op) {
648 operand2 = NOT(operand2);
649 carry_in = true;
650 imm = -imm; // For the Register plug offset context below
651 } else {
652 carry_in = false;
653 }
654
655 ProcState proc_state;
656
657 result = AddWithCarry(datasize, operand1, operand2, carry_in, proc_state);
658
659 if (setflags) {
660 m_emulated_pstate.N = proc_state.N;
661 m_emulated_pstate.Z = proc_state.Z;
662 m_emulated_pstate.C = proc_state.C;
663 m_emulated_pstate.V = proc_state.V;
664 }
665
666 Context context;
667 std::optional<RegisterInfo> reg_info_Rn =
668 GetRegisterInfo(eRegisterKindLLDB, n);
669 if (reg_info_Rn)
670 context.SetRegisterPlusOffset(*reg_info_Rn, imm);
671
672 if (n == GetFramePointerRegisterNumber() && d == gpr_sp_arm64 && !setflags) {
673 // 'mov sp, fp' - common epilogue instruction, CFA is now in terms of the
674 // stack pointer, instead of frame pointer.
675 context.type = EmulateInstruction::eContextRestoreStackPointer;
676 } else if ((n == gpr_sp_arm64 || n == GetFramePointerRegisterNumber()) &&
677 d == gpr_sp_arm64 && !setflags) {
678 context.type = EmulateInstruction::eContextAdjustStackPointer;
679 } else if (d == GetFramePointerRegisterNumber() && n == gpr_sp_arm64 &&
680 !setflags) {
681 context.type = EmulateInstruction::eContextSetFramePointer;
682 } else {
683 context.type = EmulateInstruction::eContextImmediate;
684 }
685
686 // If setflags && d == gpr_sp_arm64 then d = WZR/XZR. See CMN, CMP
687 if (!setflags || d != gpr_sp_arm64)
688 WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_x0_arm64 + d, result);
689
690 return false;
691 }
692
693 template <EmulateInstructionARM64::AddrMode a_mode>
EmulateLDPSTP(const uint32_t opcode)694 bool EmulateInstructionARM64::EmulateLDPSTP(const uint32_t opcode) {
695 uint32_t opc = Bits32(opcode, 31, 30);
696 uint32_t V = Bit32(opcode, 26);
697 uint32_t L = Bit32(opcode, 22);
698 uint32_t imm7 = Bits32(opcode, 21, 15);
699 uint32_t Rt2 = Bits32(opcode, 14, 10);
700 uint32_t Rn = Bits32(opcode, 9, 5);
701 uint32_t Rt = Bits32(opcode, 4, 0);
702
703 integer n = UInt(Rn);
704 integer t = UInt(Rt);
705 integer t2 = UInt(Rt2);
706 uint64_t idx;
707
708 MemOp memop = L == 1 ? MemOp_LOAD : MemOp_STORE;
709 boolean vector = (V == 1);
710 // AccType acctype = AccType_NORMAL;
711 boolean is_signed = false;
712 boolean wback = a_mode != AddrMode_OFF;
713 boolean wb_unknown = false;
714 boolean rt_unknown = false;
715 integer scale;
716 integer size;
717
718 if (opc == 3)
719 return false; // UNDEFINED
720
721 if (vector) {
722 scale = 2 + UInt(opc);
723 } else {
724 scale = (opc & 2) ? 3 : 2;
725 is_signed = (opc & 1) != 0;
726 if (is_signed && memop == MemOp_STORE)
727 return false; // UNDEFINED
728 }
729
730 if (!vector && wback && ((t == n) || (t2 == n))) {
731 switch (ConstrainUnpredictable(Unpredictable_WBOVERLAP)) {
732 case Constraint_UNKNOWN:
733 wb_unknown = true; // writeback is UNKNOWN
734 break;
735
736 case Constraint_SUPPRESSWB:
737 wback = false; // writeback is suppressed
738 break;
739
740 case Constraint_NOP:
741 memop = MemOp_NOP; // do nothing
742 wback = false;
743 break;
744
745 case Constraint_NONE:
746 break;
747 }
748 }
749
750 if (memop == MemOp_LOAD && t == t2) {
751 switch (ConstrainUnpredictable(Unpredictable_LDPOVERLAP)) {
752 case Constraint_UNKNOWN:
753 rt_unknown = true; // result is UNKNOWN
754 break;
755
756 case Constraint_NOP:
757 memop = MemOp_NOP; // do nothing
758 wback = false;
759 break;
760
761 default:
762 break;
763 }
764 }
765
766 idx = LSL(llvm::SignExtend64<7>(imm7), scale);
767 size = (integer)1 << scale;
768 uint64_t datasize = size * 8;
769 uint64_t address;
770 uint64_t wb_address;
771
772 std::optional<RegisterInfo> reg_info_base =
773 GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n);
774 if (!reg_info_base)
775 return false;
776
777 std::optional<RegisterInfo> reg_info_Rt;
778 std::optional<RegisterInfo> reg_info_Rt2;
779
780 if (vector) {
781 reg_info_Rt = GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t);
782 reg_info_Rt2 = GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t2);
783 } else {
784 reg_info_Rt = GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t);
785 reg_info_Rt2 = GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t2);
786 }
787
788 if (!reg_info_Rt || !reg_info_Rt2)
789 return false;
790
791 bool success = false;
792 if (n == 31) {
793 // CheckSPAlignment();
794 address =
795 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success);
796 } else
797 address =
798 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
799
800 wb_address = address + idx;
801 if (a_mode != AddrMode_POST)
802 address = wb_address;
803
804 Context context_t;
805 Context context_t2;
806
807 uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
808 Status error;
809
810 switch (memop) {
811 case MemOp_STORE: {
812 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is
813 // based off of the sp
814 // or fp register
815 {
816 context_t.type = eContextPushRegisterOnStack;
817 context_t2.type = eContextPushRegisterOnStack;
818 } else {
819 context_t.type = eContextRegisterStore;
820 context_t2.type = eContextRegisterStore;
821 }
822 context_t.SetRegisterToRegisterPlusOffset(*reg_info_Rt, *reg_info_base, 0);
823 context_t2.SetRegisterToRegisterPlusOffset(*reg_info_Rt2, *reg_info_base,
824 size);
825
826 std::optional<RegisterValue> data_Rt = ReadRegister(*reg_info_Rt);
827 if (!data_Rt)
828 return false;
829
830 if (data_Rt->GetAsMemoryData(*reg_info_Rt, buffer, reg_info_Rt->byte_size,
831 eByteOrderLittle, error) == 0)
832 return false;
833
834 if (!WriteMemory(context_t, address + 0, buffer, reg_info_Rt->byte_size))
835 return false;
836
837 std::optional<RegisterValue> data_Rt2 = ReadRegister(*reg_info_Rt2);
838 if (!data_Rt2)
839 return false;
840
841 if (data_Rt2->GetAsMemoryData(*reg_info_Rt2, buffer,
842 reg_info_Rt2->byte_size, eByteOrderLittle,
843 error) == 0)
844 return false;
845
846 if (!WriteMemory(context_t2, address + size, buffer,
847 reg_info_Rt2->byte_size))
848 return false;
849 } break;
850
851 case MemOp_LOAD: {
852 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this load is
853 // based off of the sp
854 // or fp register
855 {
856 context_t.type = eContextPopRegisterOffStack;
857 context_t2.type = eContextPopRegisterOffStack;
858 } else {
859 context_t.type = eContextRegisterLoad;
860 context_t2.type = eContextRegisterLoad;
861 }
862 context_t.SetAddress(address);
863 context_t2.SetAddress(address + size);
864
865 if (rt_unknown)
866 memset(buffer, 'U', reg_info_Rt->byte_size);
867 else {
868 if (!ReadMemory(context_t, address, buffer, reg_info_Rt->byte_size))
869 return false;
870 }
871
872 RegisterValue data_Rt;
873 if (data_Rt.SetFromMemoryData(*reg_info_Rt, buffer, reg_info_Rt->byte_size,
874 eByteOrderLittle, error) == 0)
875 return false;
876
877 if (!vector && is_signed && !data_Rt.SignExtend(datasize))
878 return false;
879
880 if (!WriteRegister(context_t, *reg_info_Rt, data_Rt))
881 return false;
882
883 if (!rt_unknown) {
884 if (!ReadMemory(context_t2, address + size, buffer,
885 reg_info_Rt2->byte_size))
886 return false;
887 }
888
889 RegisterValue data_Rt2;
890 if (data_Rt2.SetFromMemoryData(*reg_info_Rt2, buffer,
891 reg_info_Rt2->byte_size, eByteOrderLittle,
892 error) == 0)
893 return false;
894
895 if (!vector && is_signed && !data_Rt2.SignExtend(datasize))
896 return false;
897
898 if (!WriteRegister(context_t2, *reg_info_Rt2, data_Rt2))
899 return false;
900 } break;
901
902 default:
903 break;
904 }
905
906 if (wback) {
907 if (wb_unknown)
908 wb_address = LLDB_INVALID_ADDRESS;
909 Context context;
910 context.SetImmediateSigned(idx);
911 if (n == 31)
912 context.type = eContextAdjustStackPointer;
913 else
914 context.type = eContextAdjustBaseRegister;
915 WriteRegisterUnsigned(context, *reg_info_base, wb_address);
916 }
917 return true;
918 }
919
920 template <EmulateInstructionARM64::AddrMode a_mode>
EmulateLDRSTRImm(const uint32_t opcode)921 bool EmulateInstructionARM64::EmulateLDRSTRImm(const uint32_t opcode) {
922 uint32_t size = Bits32(opcode, 31, 30);
923 uint32_t opc = Bits32(opcode, 23, 22);
924 uint32_t n = Bits32(opcode, 9, 5);
925 uint32_t t = Bits32(opcode, 4, 0);
926
927 bool wback;
928 bool postindex;
929 uint64_t offset;
930
931 switch (a_mode) {
932 case AddrMode_POST:
933 wback = true;
934 postindex = true;
935 offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12));
936 break;
937 case AddrMode_PRE:
938 wback = true;
939 postindex = false;
940 offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12));
941 break;
942 case AddrMode_OFF:
943 wback = false;
944 postindex = false;
945 offset = LSL(Bits32(opcode, 21, 10), size);
946 break;
947 }
948
949 MemOp memop;
950
951 if (Bit32(opc, 1) == 0) {
952 memop = Bit32(opc, 0) == 1 ? MemOp_LOAD : MemOp_STORE;
953 } else {
954 memop = MemOp_LOAD;
955 if (size == 2 && Bit32(opc, 0) == 1)
956 return false;
957 }
958
959 Status error;
960 bool success = false;
961 uint64_t address;
962 uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
963
964 if (n == 31)
965 address =
966 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success);
967 else
968 address =
969 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
970
971 if (!success)
972 return false;
973
974 if (!postindex)
975 address += offset;
976
977 std::optional<RegisterInfo> reg_info_base =
978 GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n);
979 if (!reg_info_base)
980 return false;
981
982 std::optional<RegisterInfo> reg_info_Rt =
983 GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t);
984 if (!reg_info_Rt)
985 return false;
986
987 Context context;
988 switch (memop) {
989 case MemOp_STORE: {
990 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is
991 // based off of the sp
992 // or fp register
993 context.type = eContextPushRegisterOnStack;
994 else
995 context.type = eContextRegisterStore;
996 context.SetRegisterToRegisterPlusOffset(*reg_info_Rt, *reg_info_base,
997 postindex ? 0 : offset);
998
999 std::optional<RegisterValue> data_Rt = ReadRegister(*reg_info_Rt);
1000 if (!data_Rt)
1001 return false;
1002
1003 if (data_Rt->GetAsMemoryData(*reg_info_Rt, buffer, reg_info_Rt->byte_size,
1004 eByteOrderLittle, error) == 0)
1005 return false;
1006
1007 if (!WriteMemory(context, address, buffer, reg_info_Rt->byte_size))
1008 return false;
1009 } break;
1010
1011 case MemOp_LOAD: {
1012 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is
1013 // based off of the sp
1014 // or fp register
1015 context.type = eContextPopRegisterOffStack;
1016 else
1017 context.type = eContextRegisterLoad;
1018 context.SetAddress(address);
1019
1020 if (!ReadMemory(context, address, buffer, reg_info_Rt->byte_size))
1021 return false;
1022
1023 RegisterValue data_Rt;
1024 if (data_Rt.SetFromMemoryData(*reg_info_Rt, buffer, reg_info_Rt->byte_size,
1025 eByteOrderLittle, error) == 0)
1026 return false;
1027
1028 if (!WriteRegister(context, *reg_info_Rt, data_Rt))
1029 return false;
1030 } break;
1031 default:
1032 return false;
1033 }
1034
1035 if (wback) {
1036 if (postindex)
1037 address += offset;
1038
1039 if (n == 31)
1040 context.type = eContextAdjustStackPointer;
1041 else
1042 context.type = eContextAdjustBaseRegister;
1043 context.SetImmediateSigned(offset);
1044
1045 if (!WriteRegisterUnsigned(context, *reg_info_base, address))
1046 return false;
1047 }
1048 return true;
1049 }
1050
EmulateB(const uint32_t opcode)1051 bool EmulateInstructionARM64::EmulateB(const uint32_t opcode) {
1052 #if 0
1053 // ARM64 pseudo code...
1054 if branch_type == BranchType_CALL then X[30] = PC[] + 4;
1055 BranchTo(PC[] + offset, branch_type);
1056 #endif
1057
1058 bool success = false;
1059
1060 EmulateInstruction::Context context;
1061 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1062 const uint64_t pc = ReadRegisterUnsigned(eRegisterKindGeneric,
1063 LLDB_REGNUM_GENERIC_PC, 0, &success);
1064 if (!success)
1065 return false;
1066
1067 int64_t offset = llvm::SignExtend64<28>(Bits32(opcode, 25, 0) << 2);
1068 BranchType branch_type = Bit32(opcode, 31) ? BranchType_CALL : BranchType_JMP;
1069 addr_t target = pc + offset;
1070 context.SetImmediateSigned(offset);
1071
1072 switch (branch_type) {
1073 case BranchType_CALL: {
1074 addr_t x30 = pc + 4;
1075 if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_lr_arm64, x30))
1076 return false;
1077 } break;
1078 case BranchType_JMP:
1079 break;
1080 default:
1081 return false;
1082 }
1083
1084 return BranchTo(context, 64, target);
1085 }
1086
EmulateBcond(const uint32_t opcode)1087 bool EmulateInstructionARM64::EmulateBcond(const uint32_t opcode) {
1088 #if 0
1089 // ARM64 pseudo code...
1090 bits(64) offset = SignExtend(imm19:'00', 64);
1091 bits(4) condition = cond;
1092 if ConditionHolds(condition) then
1093 BranchTo(PC[] + offset, BranchType_JMP);
1094 #endif
1095
1096 if (ConditionHolds(Bits32(opcode, 3, 0))) {
1097 bool success = false;
1098
1099 const uint64_t pc = ReadRegisterUnsigned(
1100 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
1101 if (!success)
1102 return false;
1103
1104 int64_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2);
1105 addr_t target = pc + offset;
1106
1107 EmulateInstruction::Context context;
1108 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1109 context.SetImmediateSigned(offset);
1110 if (!BranchTo(context, 64, target))
1111 return false;
1112 }
1113 return true;
1114 }
1115
EmulateCBZ(const uint32_t opcode)1116 bool EmulateInstructionARM64::EmulateCBZ(const uint32_t opcode) {
1117 #if 0
1118 integer t = UInt(Rt);
1119 integer datasize = if sf == '1' then 64 else 32;
1120 boolean iszero = (op == '0');
1121 bits(64) offset = SignExtend(imm19:'00', 64);
1122
1123 bits(datasize) operand1 = X[t];
1124 if IsZero(operand1) == iszero then
1125 BranchTo(PC[] + offset, BranchType_JMP);
1126 #endif
1127
1128 bool success = false;
1129
1130 uint32_t t = Bits32(opcode, 4, 0);
1131 bool is_zero = Bit32(opcode, 24) == 0;
1132 int32_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2);
1133
1134 const uint64_t operand =
1135 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success);
1136 if (!success)
1137 return false;
1138
1139 if (m_ignore_conditions || ((operand == 0) == is_zero)) {
1140 const uint64_t pc = ReadRegisterUnsigned(
1141 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
1142 if (!success)
1143 return false;
1144
1145 EmulateInstruction::Context context;
1146 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1147 context.SetImmediateSigned(offset);
1148 if (!BranchTo(context, 64, pc + offset))
1149 return false;
1150 }
1151 return true;
1152 }
1153
EmulateTBZ(const uint32_t opcode)1154 bool EmulateInstructionARM64::EmulateTBZ(const uint32_t opcode) {
1155 #if 0
1156 integer t = UInt(Rt);
1157 integer datasize = if b5 == '1' then 64 else 32;
1158 integer bit_pos = UInt(b5:b40);
1159 bit bit_val = op;
1160 bits(64) offset = SignExtend(imm14:'00', 64);
1161 #endif
1162
1163 bool success = false;
1164
1165 uint32_t t = Bits32(opcode, 4, 0);
1166 uint32_t bit_pos = (Bit32(opcode, 31) << 6) | (Bits32(opcode, 23, 19));
1167 uint32_t bit_val = Bit32(opcode, 24);
1168 int64_t offset = llvm::SignExtend64<16>(Bits32(opcode, 18, 5) << 2);
1169
1170 const uint64_t operand =
1171 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success);
1172 if (!success)
1173 return false;
1174
1175 if (m_ignore_conditions || Bit32(operand, bit_pos) == bit_val) {
1176 const uint64_t pc = ReadRegisterUnsigned(
1177 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
1178 if (!success)
1179 return false;
1180
1181 EmulateInstruction::Context context;
1182 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1183 context.SetImmediateSigned(offset);
1184 if (!BranchTo(context, 64, pc + offset))
1185 return false;
1186 }
1187 return true;
1188 }
1189