1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the Machinelegalizer class for ARM.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12
13 #include "ARMLegalizerInfo.h"
14 #include "ARMCallLowering.h"
15 #include "ARMSubtarget.h"
16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
18 #include "llvm/CodeGen/LowLevelType.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetOpcodes.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/IR/Type.h"
24
25 using namespace llvm;
26 using namespace LegalizeActions;
27
28 /// FIXME: The following static functions are SizeChangeStrategy functions
29 /// that are meant to temporarily mimic the behaviour of the old legalization
30 /// based on doubling/halving non-legal types as closely as possible. This is
31 /// not entirly possible as only legalizing the types that are exactly a power
32 /// of 2 times the size of the legal types would require specifying all those
33 /// sizes explicitly.
34 /// In practice, not specifying those isn't a problem, and the below functions
35 /// should disappear quickly as we add support for legalizing non-power-of-2
36 /// sized types further.
addAndInterleaveWithUnsupported(LegacyLegalizerInfo::SizeAndActionsVec & result,const LegacyLegalizerInfo::SizeAndActionsVec & v)37 static void addAndInterleaveWithUnsupported(
38 LegacyLegalizerInfo::SizeAndActionsVec &result,
39 const LegacyLegalizerInfo::SizeAndActionsVec &v) {
40 for (unsigned i = 0; i < v.size(); ++i) {
41 result.push_back(v[i]);
42 if (i + 1 < v[i].first && i + 1 < v.size() &&
43 v[i + 1].first != v[i].first + 1)
44 result.push_back({v[i].first + 1, LegacyLegalizeActions::Unsupported});
45 }
46 }
47
48 static LegacyLegalizerInfo::SizeAndActionsVec
widen_8_16(const LegacyLegalizerInfo::SizeAndActionsVec & v)49 widen_8_16(const LegacyLegalizerInfo::SizeAndActionsVec &v) {
50 assert(v.size() >= 1);
51 assert(v[0].first > 17);
52 LegacyLegalizerInfo::SizeAndActionsVec result = {
53 {1, LegacyLegalizeActions::Unsupported},
54 {8, LegacyLegalizeActions::WidenScalar},
55 {9, LegacyLegalizeActions::Unsupported},
56 {16, LegacyLegalizeActions::WidenScalar},
57 {17, LegacyLegalizeActions::Unsupported}};
58 addAndInterleaveWithUnsupported(result, v);
59 auto Largest = result.back().first;
60 result.push_back({Largest + 1, LegacyLegalizeActions::Unsupported});
61 return result;
62 }
63
AEABI(const ARMSubtarget & ST)64 static bool AEABI(const ARMSubtarget &ST) {
65 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
66 }
67
ARMLegalizerInfo(const ARMSubtarget & ST)68 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
69 using namespace TargetOpcode;
70
71 const LLT p0 = LLT::pointer(0, 32);
72
73 const LLT s1 = LLT::scalar(1);
74 const LLT s8 = LLT::scalar(8);
75 const LLT s16 = LLT::scalar(16);
76 const LLT s32 = LLT::scalar(32);
77 const LLT s64 = LLT::scalar(64);
78
79 auto &LegacyInfo = getLegacyLegalizerInfo();
80 if (ST.isThumb1Only()) {
81 // Thumb1 is not supported yet.
82 LegacyInfo.computeTables();
83 verify(*ST.getInstrInfo());
84 return;
85 }
86
87 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
88 .legalForCartesianProduct({s8, s16, s32}, {s1, s8, s16});
89
90 getActionDefinitionsBuilder(G_SEXT_INREG).lower();
91
92 getActionDefinitionsBuilder({G_MUL, G_AND, G_OR, G_XOR})
93 .legalFor({s32})
94 .clampScalar(0, s32, s32);
95
96 if (ST.hasNEON())
97 getActionDefinitionsBuilder({G_ADD, G_SUB})
98 .legalFor({s32, s64})
99 .minScalar(0, s32);
100 else
101 getActionDefinitionsBuilder({G_ADD, G_SUB})
102 .legalFor({s32})
103 .minScalar(0, s32);
104
105 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
106 .legalFor({{s32, s32}})
107 .minScalar(0, s32)
108 .clampScalar(1, s32, s32);
109
110 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) ||
111 (ST.isThumb() && ST.hasDivideInThumbMode());
112 if (HasHWDivide)
113 getActionDefinitionsBuilder({G_SDIV, G_UDIV})
114 .legalFor({s32})
115 .clampScalar(0, s32, s32);
116 else
117 getActionDefinitionsBuilder({G_SDIV, G_UDIV})
118 .libcallFor({s32})
119 .clampScalar(0, s32, s32);
120
121 for (unsigned Op : {G_SREM, G_UREM}) {
122 LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16);
123 if (HasHWDivide)
124 LegacyInfo.setAction({Op, s32}, LegacyLegalizeActions::Lower);
125 else if (AEABI(ST))
126 LegacyInfo.setAction({Op, s32}, LegacyLegalizeActions::Custom);
127 else
128 LegacyInfo.setAction({Op, s32}, LegacyLegalizeActions::Libcall);
129 }
130
131 getActionDefinitionsBuilder(G_INTTOPTR)
132 .legalFor({{p0, s32}})
133 .minScalar(1, s32);
134 getActionDefinitionsBuilder(G_PTRTOINT)
135 .legalFor({{s32, p0}})
136 .minScalar(0, s32);
137
138 getActionDefinitionsBuilder(G_CONSTANT)
139 .legalFor({s32, p0})
140 .clampScalar(0, s32, s32);
141
142 getActionDefinitionsBuilder(G_ICMP)
143 .legalForCartesianProduct({s1}, {s32, p0})
144 .minScalar(1, s32);
145
146 getActionDefinitionsBuilder(G_SELECT)
147 .legalForCartesianProduct({s32, p0}, {s1})
148 .minScalar(0, s32);
149
150 // We're keeping these builders around because we'll want to add support for
151 // floating point to them.
152 auto &LoadStoreBuilder = getActionDefinitionsBuilder({G_LOAD, G_STORE})
153 .legalForTypesWithMemDesc({{s8, p0, s8, 8},
154 {s16, p0, s16, 8},
155 {s32, p0, s32, 8},
156 {p0, p0, p0, 8}})
157 .unsupportedIfMemSizeNotPow2();
158
159 getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
160 getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
161
162 auto &PhiBuilder =
163 getActionDefinitionsBuilder(G_PHI)
164 .legalFor({s32, p0})
165 .minScalar(0, s32);
166
167 getActionDefinitionsBuilder(G_PTR_ADD)
168 .legalFor({{p0, s32}})
169 .minScalar(1, s32);
170
171 getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
172
173 if (!ST.useSoftFloat() && ST.hasVFP2Base()) {
174 getActionDefinitionsBuilder(
175 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
176 .legalFor({s32, s64});
177
178 LoadStoreBuilder
179 .legalForTypesWithMemDesc({{s64, p0, s64, 32}})
180 .maxScalar(0, s32);
181 PhiBuilder.legalFor({s64});
182
183 getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1},
184 {s32, s64});
185
186 getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}});
187 getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}});
188
189 getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}});
190 getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}});
191
192 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
193 .legalForCartesianProduct({s32}, {s32, s64});
194 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
195 .legalForCartesianProduct({s32, s64}, {s32});
196 } else {
197 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
198 .libcallFor({s32, s64});
199
200 LoadStoreBuilder.maxScalar(0, s32);
201
202 for (auto Ty : {s32, s64})
203 LegacyInfo.setAction({G_FNEG, Ty}, LegacyLegalizeActions::Lower);
204
205 getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64});
206
207 getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1},
208 {s32, s64});
209
210 if (AEABI(ST))
211 setFCmpLibcallsAEABI();
212 else
213 setFCmpLibcallsGNU();
214
215 getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}});
216 getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}});
217
218 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
219 .libcallForCartesianProduct({s32}, {s32, s64});
220 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
221 .libcallForCartesianProduct({s32, s64}, {s32});
222 }
223
224 // Just expand whatever loads and stores are left.
225 LoadStoreBuilder.lower();
226
227 if (!ST.useSoftFloat() && ST.hasVFP4Base())
228 getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64});
229 else
230 getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64});
231
232 getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
233
234 if (ST.hasV5TOps()) {
235 getActionDefinitionsBuilder(G_CTLZ)
236 .legalFor({s32, s32})
237 .clampScalar(1, s32, s32)
238 .clampScalar(0, s32, s32);
239 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
240 .lowerFor({s32, s32})
241 .clampScalar(1, s32, s32)
242 .clampScalar(0, s32, s32);
243 } else {
244 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
245 .libcallFor({s32, s32})
246 .clampScalar(1, s32, s32)
247 .clampScalar(0, s32, s32);
248 getActionDefinitionsBuilder(G_CTLZ)
249 .lowerFor({s32, s32})
250 .clampScalar(1, s32, s32)
251 .clampScalar(0, s32, s32);
252 }
253
254 LegacyInfo.computeTables();
255 verify(*ST.getInstrInfo());
256 }
257
setFCmpLibcallsAEABI()258 void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
259 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
260 // default-initialized.
261 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
262 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
263 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
264 FCmp32Libcalls[CmpInst::FCMP_OGE] = {
265 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
266 FCmp32Libcalls[CmpInst::FCMP_OGT] = {
267 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
268 FCmp32Libcalls[CmpInst::FCMP_OLE] = {
269 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
270 FCmp32Libcalls[CmpInst::FCMP_OLT] = {
271 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
272 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F32, CmpInst::ICMP_EQ}};
273 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
274 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
275 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
276 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
277 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
278 FCmp32Libcalls[CmpInst::FCMP_UNO] = {
279 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
280 FCmp32Libcalls[CmpInst::FCMP_ONE] = {
281 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
282 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
283 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
284 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
285 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
286
287 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
288 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
289 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
290 FCmp64Libcalls[CmpInst::FCMP_OGE] = {
291 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
292 FCmp64Libcalls[CmpInst::FCMP_OGT] = {
293 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
294 FCmp64Libcalls[CmpInst::FCMP_OLE] = {
295 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
296 FCmp64Libcalls[CmpInst::FCMP_OLT] = {
297 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
298 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F64, CmpInst::ICMP_EQ}};
299 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
300 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
301 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
302 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
303 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
304 FCmp64Libcalls[CmpInst::FCMP_UNO] = {
305 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
306 FCmp64Libcalls[CmpInst::FCMP_ONE] = {
307 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
308 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
309 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
310 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
311 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
312 }
313
setFCmpLibcallsGNU()314 void ARMLegalizerInfo::setFCmpLibcallsGNU() {
315 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
316 // default-initialized.
317 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
318 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
319 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
320 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
321 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
322 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
323 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F32, CmpInst::ICMP_EQ}};
324 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
325 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
326 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
327 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
328 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
329 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
330 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
331 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
332 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
333 {RTLIB::UO_F32, CmpInst::ICMP_NE}};
334
335 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
336 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
337 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
338 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
339 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
340 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
341 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F64, CmpInst::ICMP_EQ}};
342 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
343 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
344 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
345 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
346 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
347 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
348 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
349 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
350 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
351 {RTLIB::UO_F64, CmpInst::ICMP_NE}};
352 }
353
354 ARMLegalizerInfo::FCmpLibcallsList
getFCmpLibcalls(CmpInst::Predicate Predicate,unsigned Size) const355 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
356 unsigned Size) const {
357 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
358 if (Size == 32)
359 return FCmp32Libcalls[Predicate];
360 if (Size == 64)
361 return FCmp64Libcalls[Predicate];
362 llvm_unreachable("Unsupported size for FCmp predicate");
363 }
364
legalizeCustom(LegalizerHelper & Helper,MachineInstr & MI) const365 bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
366 MachineInstr &MI) const {
367 using namespace TargetOpcode;
368
369 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
370 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
371 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
372
373 switch (MI.getOpcode()) {
374 default:
375 return false;
376 case G_SREM:
377 case G_UREM: {
378 Register OriginalResult = MI.getOperand(0).getReg();
379 auto Size = MRI.getType(OriginalResult).getSizeInBits();
380 if (Size != 32)
381 return false;
382
383 auto Libcall =
384 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
385
386 // Our divmod libcalls return a struct containing the quotient and the
387 // remainder. Create a new, unused register for the quotient and use the
388 // destination of the original instruction for the remainder.
389 Type *ArgTy = Type::getInt32Ty(Ctx);
390 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
391 Register RetRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
392 OriginalResult};
393 auto Status = createLibcall(MIRBuilder, Libcall, {RetRegs, RetTy, 0},
394 {{MI.getOperand(1).getReg(), ArgTy, 0},
395 {MI.getOperand(2).getReg(), ArgTy, 0}});
396 if (Status != LegalizerHelper::Legalized)
397 return false;
398 break;
399 }
400 case G_FCMP: {
401 assert(MRI.getType(MI.getOperand(2).getReg()) ==
402 MRI.getType(MI.getOperand(3).getReg()) &&
403 "Mismatched operands for G_FCMP");
404 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
405
406 auto OriginalResult = MI.getOperand(0).getReg();
407 auto Predicate =
408 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
409 auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
410
411 if (Libcalls.empty()) {
412 assert((Predicate == CmpInst::FCMP_TRUE ||
413 Predicate == CmpInst::FCMP_FALSE) &&
414 "Predicate needs libcalls, but none specified");
415 MIRBuilder.buildConstant(OriginalResult,
416 Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
417 MI.eraseFromParent();
418 return true;
419 }
420
421 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
422 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
423 auto *RetTy = Type::getInt32Ty(Ctx);
424
425 SmallVector<Register, 2> Results;
426 for (auto Libcall : Libcalls) {
427 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
428 auto Status = createLibcall(MIRBuilder, Libcall.LibcallID,
429 {LibcallResult, RetTy, 0},
430 {{MI.getOperand(2).getReg(), ArgTy, 0},
431 {MI.getOperand(3).getReg(), ArgTy, 0}});
432
433 if (Status != LegalizerHelper::Legalized)
434 return false;
435
436 auto ProcessedResult =
437 Libcalls.size() == 1
438 ? OriginalResult
439 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
440
441 // We have a result, but we need to transform it into a proper 1-bit 0 or
442 // 1, taking into account the different peculiarities of the values
443 // returned by the comparison functions.
444 CmpInst::Predicate ResultPred = Libcall.Predicate;
445 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
446 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
447 // to keep the types consistent.
448 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
449 } else {
450 // We need to compare against 0.
451 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
452 auto Zero = MIRBuilder.buildConstant(LLT::scalar(32), 0);
453 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
454 }
455 Results.push_back(ProcessedResult);
456 }
457
458 if (Results.size() != 1) {
459 assert(Results.size() == 2 && "Unexpected number of results");
460 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
461 }
462 break;
463 }
464 case G_FCONSTANT: {
465 // Convert to integer constants, while preserving the binary representation.
466 auto AsInteger =
467 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt();
468 MIRBuilder.buildConstant(MI.getOperand(0),
469 *ConstantInt::get(Ctx, AsInteger));
470 break;
471 }
472 }
473
474 MI.eraseFromParent();
475 return true;
476 }
477