1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides AArch64 specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H 15 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H 16 17 #include "llvm/Support/DataTypes.h" 18 #include <string> 19 20 namespace llvm { 21 class formatted_raw_ostream; 22 class MCAsmBackend; 23 class MCCodeEmitter; 24 class MCContext; 25 class MCInstrInfo; 26 class MCInstPrinter; 27 class MCRegisterInfo; 28 class MCObjectWriter; 29 class MCStreamer; 30 class MCSubtargetInfo; 31 class StringRef; 32 class Target; 33 class raw_ostream; 34 35 extern Target TheAArch64leTarget; 36 extern Target TheAArch64beTarget; 37 extern Target TheARM64Target; 38 39 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII, 40 const MCRegisterInfo &MRI, 41 const MCSubtargetInfo &STI, 42 MCContext &Ctx); 43 MCAsmBackend *createAArch64leAsmBackend(const Target &T, 44 const MCRegisterInfo &MRI, StringRef TT, 45 StringRef CPU); 46 MCAsmBackend *createAArch64beAsmBackend(const Target &T, 47 const MCRegisterInfo &MRI, StringRef TT, 48 StringRef CPU); 49 50 MCObjectWriter *createAArch64ELFObjectWriter(raw_ostream &OS, uint8_t OSABI, 51 bool IsLittleEndian); 52 53 MCObjectWriter *createAArch64MachObjectWriter(raw_ostream &OS, uint32_t CPUType, 54 uint32_t CPUSubtype); 55 56 MCStreamer * 57 createAArch64MCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, 58 bool isVerboseAsm, bool useDwarfDirectory, 59 MCInstPrinter *InstPrint, MCCodeEmitter *CE, 60 MCAsmBackend *TAB, bool ShowInst); 61 } // End llvm namespace 62 63 // Defines symbolic names for AArch64 registers. This defines a mapping from 64 // register name to register number. 65 // 66 #define GET_REGINFO_ENUM 67 #include "AArch64GenRegisterInfo.inc" 68 69 // Defines symbolic names for the AArch64 instructions. 70 // 71 #define GET_INSTRINFO_ENUM 72 #include "AArch64GenInstrInfo.inc" 73 74 #define GET_SUBTARGETINFO_ENUM 75 #include "AArch64GenSubtargetInfo.inc" 76 77 #endif 78