1 //=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // The Cortex-A15 processor employs a tracking scheme in its register renaming
11 // in order to process each instruction's micro-ops speculatively and
12 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
13 // instructions to read and write 32-bit S-registers. Each S-register
14 // corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
15 //
16 // There are several instruction patterns which can be used to provide this
17 // capability which can provide higher performance than other, potentially more
18 // direct patterns, specifically around when one micro-op reads a D-register
19 // operand that has recently been written as one or more S-register results.
20 //
21 // This file defines a pre-regalloc pass which looks for SPR producers which
22 // are going to be used by a DPR (or QPR) consumers and creates the more
23 // optimized access pattern.
24 //
25 //===----------------------------------------------------------------------===//
26
27 #include "ARM.h"
28 #include "ARMBaseInstrInfo.h"
29 #include "ARMBaseRegisterInfo.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
38 #include <map>
39 #include <set>
40
41 using namespace llvm;
42
43 #define DEBUG_TYPE "a15-sd-optimizer"
44
45 namespace {
46 struct A15SDOptimizer : public MachineFunctionPass {
47 static char ID;
A15SDOptimizer__anon9e89f2a90111::A15SDOptimizer48 A15SDOptimizer() : MachineFunctionPass(ID) {}
49
50 bool runOnMachineFunction(MachineFunction &Fn) override;
51
getPassName__anon9e89f2a90111::A15SDOptimizer52 const char *getPassName() const override {
53 return "ARM A15 S->D optimizer";
54 }
55
56 private:
57 const ARMBaseInstrInfo *TII;
58 const TargetRegisterInfo *TRI;
59 MachineRegisterInfo *MRI;
60
61 bool runOnInstruction(MachineInstr *MI);
62
63 //
64 // Instruction builder helpers
65 //
66 unsigned createDupLane(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator InsertBefore,
68 DebugLoc DL,
69 unsigned Reg, unsigned Lane,
70 bool QPR=false);
71
72 unsigned createExtractSubreg(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator InsertBefore,
74 DebugLoc DL,
75 unsigned DReg, unsigned Lane,
76 const TargetRegisterClass *TRC);
77
78 unsigned createVExt(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator InsertBefore,
80 DebugLoc DL,
81 unsigned Ssub0, unsigned Ssub1);
82
83 unsigned createRegSequence(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator InsertBefore,
85 DebugLoc DL,
86 unsigned Reg1, unsigned Reg2);
87
88 unsigned createInsertSubreg(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator InsertBefore,
90 DebugLoc DL, unsigned DReg, unsigned Lane,
91 unsigned ToInsert);
92
93 unsigned createImplicitDef(MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator InsertBefore,
95 DebugLoc DL);
96
97 //
98 // Various property checkers
99 //
100 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
101 bool hasPartialWrite(MachineInstr *MI);
102 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
103 unsigned getDPRLaneFromSPR(unsigned SReg);
104
105 //
106 // Methods used for getting the definitions of partial registers
107 //
108
109 MachineInstr *elideCopies(MachineInstr *MI);
110 void elideCopiesAndPHIs(MachineInstr *MI,
111 SmallVectorImpl<MachineInstr*> &Outs);
112
113 //
114 // Pattern optimization methods
115 //
116 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
117 unsigned optimizeSDPattern(MachineInstr *MI);
118 unsigned getPrefSPRLane(unsigned SReg);
119
120 //
121 // Sanitizing method - used to make sure if don't leave dead code around.
122 //
123 void eraseInstrWithNoUses(MachineInstr *MI);
124
125 //
126 // A map used to track the changes done by this pass.
127 //
128 std::map<MachineInstr*, unsigned> Replacements;
129 std::set<MachineInstr *> DeadInstr;
130 };
131 char A15SDOptimizer::ID = 0;
132 } // end anonymous namespace
133
134 // Returns true if this is a use of a SPR register.
usesRegClass(MachineOperand & MO,const TargetRegisterClass * TRC)135 bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
136 const TargetRegisterClass *TRC) {
137 if (!MO.isReg())
138 return false;
139 unsigned Reg = MO.getReg();
140
141 if (TargetRegisterInfo::isVirtualRegister(Reg))
142 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
143 else
144 return TRC->contains(Reg);
145 }
146
getDPRLaneFromSPR(unsigned SReg)147 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
148 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
149 &ARM::DPRRegClass);
150 if (DReg != ARM::NoRegister) return ARM::ssub_1;
151 return ARM::ssub_0;
152 }
153
154 // Get the subreg type that is most likely to be coalesced
155 // for an SPR register that will be used in VDUP32d pseudo.
getPrefSPRLane(unsigned SReg)156 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
157 if (!TRI->isVirtualRegister(SReg))
158 return getDPRLaneFromSPR(SReg);
159
160 MachineInstr *MI = MRI->getVRegDef(SReg);
161 if (!MI) return ARM::ssub_0;
162 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
163
164 assert(MO->isReg() && "Non-register operand found!");
165 if (!MO) return ARM::ssub_0;
166
167 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
168 &ARM::SPRRegClass)) {
169 SReg = MI->getOperand(1).getReg();
170 }
171
172 if (TargetRegisterInfo::isVirtualRegister(SReg)) {
173 if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
174 return ARM::ssub_0;
175 }
176 return getDPRLaneFromSPR(SReg);
177 }
178
179 // MI is known to be dead. Figure out what instructions
180 // are also made dead by this and mark them for removal.
eraseInstrWithNoUses(MachineInstr * MI)181 void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
182 SmallVector<MachineInstr *, 8> Front;
183 DeadInstr.insert(MI);
184
185 DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
186 Front.push_back(MI);
187
188 while (Front.size() != 0) {
189 MI = Front.back();
190 Front.pop_back();
191
192 // MI is already known to be dead. We need to see
193 // if other instructions can also be removed.
194 for (unsigned int i = 0; i < MI->getNumOperands(); ++i) {
195 MachineOperand &MO = MI->getOperand(i);
196 if ((!MO.isReg()) || (!MO.isUse()))
197 continue;
198 unsigned Reg = MO.getReg();
199 if (!TRI->isVirtualRegister(Reg))
200 continue;
201 MachineOperand *Op = MI->findRegisterDefOperand(Reg);
202
203 if (!Op)
204 continue;
205
206 MachineInstr *Def = Op->getParent();
207
208 // We don't need to do anything if we have already marked
209 // this instruction as being dead.
210 if (DeadInstr.find(Def) != DeadInstr.end())
211 continue;
212
213 // Check if all the uses of this instruction are marked as
214 // dead. If so, we can also mark this instruction as being
215 // dead.
216 bool IsDead = true;
217 for (unsigned int j = 0; j < Def->getNumOperands(); ++j) {
218 MachineOperand &MODef = Def->getOperand(j);
219 if ((!MODef.isReg()) || (!MODef.isDef()))
220 continue;
221 unsigned DefReg = MODef.getReg();
222 if (!TRI->isVirtualRegister(DefReg)) {
223 IsDead = false;
224 break;
225 }
226 for (MachineRegisterInfo::use_instr_iterator
227 II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end();
228 II != EE; ++II) {
229 // We don't care about self references.
230 if (&*II == Def)
231 continue;
232 if (DeadInstr.find(&*II) == DeadInstr.end()) {
233 IsDead = false;
234 break;
235 }
236 }
237 }
238
239 if (!IsDead) continue;
240
241 DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
242 DeadInstr.insert(Def);
243 }
244 }
245 }
246
247 // Creates the more optimized patterns and generally does all the code
248 // transformations in this pass.
optimizeSDPattern(MachineInstr * MI)249 unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
250 if (MI->isCopy()) {
251 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
252 }
253
254 if (MI->isInsertSubreg()) {
255 unsigned DPRReg = MI->getOperand(1).getReg();
256 unsigned SPRReg = MI->getOperand(2).getReg();
257
258 if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
259 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
260 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
261
262 if (DPRMI && SPRMI) {
263 // See if the first operand of this insert_subreg is IMPLICIT_DEF
264 MachineInstr *ECDef = elideCopies(DPRMI);
265 if (ECDef && ECDef->isImplicitDef()) {
266 // Another corner case - if we're inserting something that is purely
267 // a subreg copy of a DPR, just use that DPR.
268
269 MachineInstr *EC = elideCopies(SPRMI);
270 // Is it a subreg copy of ssub_0?
271 if (EC && EC->isCopy() &&
272 EC->getOperand(1).getSubReg() == ARM::ssub_0) {
273 DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
274
275 // Find the thing we're subreg copying out of - is it of the same
276 // regclass as DPRMI? (i.e. a DPR or QPR).
277 unsigned FullReg = SPRMI->getOperand(1).getReg();
278 const TargetRegisterClass *TRC =
279 MRI->getRegClass(MI->getOperand(1).getReg());
280 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
281 DEBUG(dbgs() << "Subreg copy is compatible - returning ");
282 DEBUG(dbgs() << PrintReg(FullReg) << "\n");
283 eraseInstrWithNoUses(MI);
284 return FullReg;
285 }
286 }
287
288 return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
289 }
290 }
291 }
292 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
293 }
294
295 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
296 &ARM::SPRRegClass)) {
297 // See if all bar one of the operands are IMPLICIT_DEF and insert the
298 // optimizer pattern accordingly.
299 unsigned NumImplicit = 0, NumTotal = 0;
300 unsigned NonImplicitReg = ~0U;
301
302 for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
303 if (!MI->getOperand(I).isReg())
304 continue;
305 ++NumTotal;
306 unsigned OpReg = MI->getOperand(I).getReg();
307
308 if (!TRI->isVirtualRegister(OpReg))
309 break;
310
311 MachineInstr *Def = MRI->getVRegDef(OpReg);
312 if (!Def)
313 break;
314 if (Def->isImplicitDef())
315 ++NumImplicit;
316 else
317 NonImplicitReg = MI->getOperand(I).getReg();
318 }
319
320 if (NumImplicit == NumTotal - 1)
321 return optimizeAllLanesPattern(MI, NonImplicitReg);
322 else
323 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
324 }
325
326 llvm_unreachable("Unhandled update pattern!");
327 }
328
329 // Return true if this MachineInstr inserts a scalar (SPR) value into
330 // a D or Q register.
hasPartialWrite(MachineInstr * MI)331 bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
332 // The only way we can do a partial register update is through a COPY,
333 // INSERT_SUBREG or REG_SEQUENCE.
334 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
335 return true;
336
337 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
338 &ARM::SPRRegClass))
339 return true;
340
341 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
342 return true;
343
344 return false;
345 }
346
347 // Looks through full copies to get the instruction that defines the input
348 // operand for MI.
elideCopies(MachineInstr * MI)349 MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
350 if (!MI->isFullCopy())
351 return MI;
352 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
353 return nullptr;
354 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
355 if (!Def)
356 return nullptr;
357 return elideCopies(Def);
358 }
359
360 // Look through full copies and PHIs to get the set of non-copy MachineInstrs
361 // that can produce MI.
elideCopiesAndPHIs(MachineInstr * MI,SmallVectorImpl<MachineInstr * > & Outs)362 void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
363 SmallVectorImpl<MachineInstr*> &Outs) {
364 // Looking through PHIs may create loops so we need to track what
365 // instructions we have visited before.
366 std::set<MachineInstr *> Reached;
367 SmallVector<MachineInstr *, 8> Front;
368 Front.push_back(MI);
369 while (Front.size() != 0) {
370 MI = Front.back();
371 Front.pop_back();
372
373 // If we have already explored this MachineInstr, ignore it.
374 if (Reached.find(MI) != Reached.end())
375 continue;
376 Reached.insert(MI);
377 if (MI->isPHI()) {
378 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
379 unsigned Reg = MI->getOperand(I).getReg();
380 if (!TRI->isVirtualRegister(Reg)) {
381 continue;
382 }
383 MachineInstr *NewMI = MRI->getVRegDef(Reg);
384 if (!NewMI)
385 continue;
386 Front.push_back(NewMI);
387 }
388 } else if (MI->isFullCopy()) {
389 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
390 continue;
391 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
392 if (!NewMI)
393 continue;
394 Front.push_back(NewMI);
395 } else {
396 DEBUG(dbgs() << "Found partial copy" << *MI <<"\n");
397 Outs.push_back(MI);
398 }
399 }
400 }
401
402 // Return the DPR virtual registers that are read by this machine instruction
403 // (if any).
getReadDPRs(MachineInstr * MI)404 SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
405 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
406 MI->isKill())
407 return SmallVector<unsigned, 8>();
408
409 SmallVector<unsigned, 8> Defs;
410 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
411 MachineOperand &MO = MI->getOperand(i);
412
413 if (!MO.isReg() || !MO.isUse())
414 continue;
415 if (!usesRegClass(MO, &ARM::DPRRegClass) &&
416 !usesRegClass(MO, &ARM::QPRRegClass) &&
417 !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
418 continue;
419
420 Defs.push_back(MO.getReg());
421 }
422 return Defs;
423 }
424
425 // Creates a DPR register from an SPR one by using a VDUP.
426 unsigned
createDupLane(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,DebugLoc DL,unsigned Reg,unsigned Lane,bool QPR)427 A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
428 MachineBasicBlock::iterator InsertBefore,
429 DebugLoc DL,
430 unsigned Reg, unsigned Lane, bool QPR) {
431 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
432 &ARM::DPRRegClass);
433 AddDefaultPred(BuildMI(MBB,
434 InsertBefore,
435 DL,
436 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
437 Out)
438 .addReg(Reg)
439 .addImm(Lane));
440
441 return Out;
442 }
443
444 // Creates a SPR register from a DPR by copying the value in lane 0.
445 unsigned
createExtractSubreg(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,DebugLoc DL,unsigned DReg,unsigned Lane,const TargetRegisterClass * TRC)446 A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB,
447 MachineBasicBlock::iterator InsertBefore,
448 DebugLoc DL,
449 unsigned DReg, unsigned Lane,
450 const TargetRegisterClass *TRC) {
451 unsigned Out = MRI->createVirtualRegister(TRC);
452 BuildMI(MBB,
453 InsertBefore,
454 DL,
455 TII->get(TargetOpcode::COPY), Out)
456 .addReg(DReg, 0, Lane);
457
458 return Out;
459 }
460
461 // Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
462 unsigned
createRegSequence(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,DebugLoc DL,unsigned Reg1,unsigned Reg2)463 A15SDOptimizer::createRegSequence(MachineBasicBlock &MBB,
464 MachineBasicBlock::iterator InsertBefore,
465 DebugLoc DL,
466 unsigned Reg1, unsigned Reg2) {
467 unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
468 BuildMI(MBB,
469 InsertBefore,
470 DL,
471 TII->get(TargetOpcode::REG_SEQUENCE), Out)
472 .addReg(Reg1)
473 .addImm(ARM::dsub_0)
474 .addReg(Reg2)
475 .addImm(ARM::dsub_1);
476 return Out;
477 }
478
479 // Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
480 // and merges them into one DPR register.
481 unsigned
createVExt(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,DebugLoc DL,unsigned Ssub0,unsigned Ssub1)482 A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
483 MachineBasicBlock::iterator InsertBefore,
484 DebugLoc DL,
485 unsigned Ssub0, unsigned Ssub1) {
486 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
487 AddDefaultPred(BuildMI(MBB,
488 InsertBefore,
489 DL,
490 TII->get(ARM::VEXTd32), Out)
491 .addReg(Ssub0)
492 .addReg(Ssub1)
493 .addImm(1));
494 return Out;
495 }
496
497 unsigned
createInsertSubreg(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,DebugLoc DL,unsigned DReg,unsigned Lane,unsigned ToInsert)498 A15SDOptimizer::createInsertSubreg(MachineBasicBlock &MBB,
499 MachineBasicBlock::iterator InsertBefore,
500 DebugLoc DL, unsigned DReg, unsigned Lane,
501 unsigned ToInsert) {
502 unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
503 BuildMI(MBB,
504 InsertBefore,
505 DL,
506 TII->get(TargetOpcode::INSERT_SUBREG), Out)
507 .addReg(DReg)
508 .addReg(ToInsert)
509 .addImm(Lane);
510
511 return Out;
512 }
513
514 unsigned
createImplicitDef(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,DebugLoc DL)515 A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
516 MachineBasicBlock::iterator InsertBefore,
517 DebugLoc DL) {
518 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
519 BuildMI(MBB,
520 InsertBefore,
521 DL,
522 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
523 return Out;
524 }
525
526 // This function inserts instructions in order to optimize interactions between
527 // SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
528 // lanes, and the using VEXT instructions to recompose the result.
529 unsigned
optimizeAllLanesPattern(MachineInstr * MI,unsigned Reg)530 A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
531 MachineBasicBlock::iterator InsertPt(MI);
532 DebugLoc DL = MI->getDebugLoc();
533 MachineBasicBlock &MBB = *MI->getParent();
534 InsertPt++;
535 unsigned Out;
536
537 // DPair has the same length as QPR and also has two DPRs as subreg.
538 // Treat DPair as QPR.
539 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
540 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
541 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
542 ARM::dsub_0, &ARM::DPRRegClass);
543 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
544 ARM::dsub_1, &ARM::DPRRegClass);
545
546 unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
547 unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
548 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
549
550 unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
551 unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
552 Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
553
554 Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
555
556 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
557 unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
558 unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
559 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
560
561 } else {
562 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
563 "Found unexpected regclass!");
564
565 unsigned PrefLane = getPrefSPRLane(Reg);
566 unsigned Lane;
567 switch (PrefLane) {
568 case ARM::ssub_0: Lane = 0; break;
569 case ARM::ssub_1: Lane = 1; break;
570 default: llvm_unreachable("Unknown preferred lane!");
571 }
572
573 // Treat DPair as QPR
574 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
575 usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
576
577 Out = createImplicitDef(MBB, InsertPt, DL);
578 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
579 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
580 eraseInstrWithNoUses(MI);
581 }
582 return Out;
583 }
584
runOnInstruction(MachineInstr * MI)585 bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
586 // We look for instructions that write S registers that are then read as
587 // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
588 // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
589 // merge two SPR values to form a DPR register. In order avoid false
590 // positives we make sure that there is an SPR producer so we look past
591 // COPY and PHI nodes to find it.
592 //
593 // The best code pattern for when an SPR producer is going to be used by a
594 // DPR or QPR consumer depends on whether the other lanes of the
595 // corresponding DPR/QPR are currently defined.
596 //
597 // We can handle these efficiently, depending on the type of
598 // pseudo-instruction that is producing the pattern
599 //
600 // * COPY: * VDUP all lanes and merge the results together
601 // using VEXTs.
602 //
603 // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
604 // lane, and the other lane(s) of the DPR/QPR register
605 // that we are inserting in are undefined, use the
606 // original DPR/QPR value.
607 // * Otherwise, fall back on the same stategy as COPY.
608 //
609 // * REG_SEQUENCE: * If all except one of the input operands are
610 // IMPLICIT_DEFs, insert the VDUP pattern for just the
611 // defined input operand
612 // * Otherwise, fall back on the same stategy as COPY.
613 //
614
615 // First, get all the reads of D-registers done by this instruction.
616 SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
617 bool Modified = false;
618
619 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
620 I != E; ++I) {
621 // Follow the def-use chain for this DPR through COPYs, and also through
622 // PHIs (which are essentially multi-way COPYs). It is because of PHIs that
623 // we can end up with multiple defs of this DPR.
624
625 SmallVector<MachineInstr *, 8> DefSrcs;
626 if (!TRI->isVirtualRegister(*I))
627 continue;
628 MachineInstr *Def = MRI->getVRegDef(*I);
629 if (!Def)
630 continue;
631
632 elideCopiesAndPHIs(Def, DefSrcs);
633
634 for (SmallVectorImpl<MachineInstr *>::iterator II = DefSrcs.begin(),
635 EE = DefSrcs.end(); II != EE; ++II) {
636 MachineInstr *MI = *II;
637
638 // If we've already analyzed and replaced this operand, don't do
639 // anything.
640 if (Replacements.find(MI) != Replacements.end())
641 continue;
642
643 // Now, work out if the instruction causes a SPR->DPR dependency.
644 if (!hasPartialWrite(MI))
645 continue;
646
647 // Collect all the uses of this MI's DPR def for updating later.
648 SmallVector<MachineOperand*, 8> Uses;
649 unsigned DPRDefReg = MI->getOperand(0).getReg();
650 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
651 E = MRI->use_end(); I != E; ++I)
652 Uses.push_back(&*I);
653
654 // We can optimize this.
655 unsigned NewReg = optimizeSDPattern(MI);
656
657 if (NewReg != 0) {
658 Modified = true;
659 for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
660 E = Uses.end(); I != E; ++I) {
661 // Make sure to constrain the register class of the new register to
662 // match what we're replacing. Otherwise we can optimize a DPR_VFP2
663 // reference into a plain DPR, and that will end poorly. NewReg is
664 // always virtual here, so there will always be a matching subclass
665 // to find.
666 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
667
668 DEBUG(dbgs() << "Replacing operand "
669 << **I << " with "
670 << PrintReg(NewReg) << "\n");
671 (*I)->substVirtReg(NewReg, 0, *TRI);
672 }
673 }
674 Replacements[MI] = NewReg;
675 }
676 }
677 return Modified;
678 }
679
runOnMachineFunction(MachineFunction & Fn)680 bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
681 TII = static_cast<const ARMBaseInstrInfo *>(Fn.getSubtarget().getInstrInfo());
682 TRI = Fn.getSubtarget().getRegisterInfo();
683 MRI = &Fn.getRegInfo();
684 bool Modified = false;
685
686 DEBUG(dbgs() << "Running on function " << Fn.getName()<< "\n");
687
688 DeadInstr.clear();
689 Replacements.clear();
690
691 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
692 ++MFI) {
693
694 for (MachineBasicBlock::iterator MI = MFI->begin(), ME = MFI->end();
695 MI != ME;) {
696 Modified |= runOnInstruction(MI++);
697 }
698
699 }
700
701 for (std::set<MachineInstr *>::iterator I = DeadInstr.begin(),
702 E = DeadInstr.end();
703 I != E; ++I) {
704 (*I)->eraseFromParent();
705 }
706
707 return Modified;
708 }
709
createA15SDOptimizerPass()710 FunctionPass *llvm::createA15SDOptimizerPass() {
711 return new A15SDOptimizer();
712 }
713