xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/amdgpu_dmub_dcn21.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: amdgpu_dmub_dcn21.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2019 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: AMD
25  *
26  */
27 
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dmub_dcn21.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $");
30 
31 #include "../inc/dmub_srv.h"
32 #include "dmub_reg.h"
33 #include "dmub_dcn21.h"
34 
35 #include "dcn/dcn_2_1_0_offset.h"
36 #include "dcn/dcn_2_1_0_sh_mask.h"
37 #include "renoir_ip_offset.h"
38 
39 #define BASE_INNER(seg) DMU_BASE__INST0_SEG##seg
40 #define CTX dmub
41 #define REGS dmub->regs
42 
43 /* Registers. */
44 
45 const struct dmub_srv_common_regs dmub_srv_dcn21_regs = {
46 #define DMUB_SR(reg) REG_OFFSET(reg),
47 	{ DMUB_COMMON_REGS() },
48 #undef DMUB_SR
49 
50 #define DMUB_SF(reg, field) FD_MASK(reg, field),
51 	{ DMUB_COMMON_FIELDS() },
52 #undef DMUB_SF
53 
54 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
55 	{ DMUB_COMMON_FIELDS() },
56 #undef DMUB_SF
57 };
58 
59 /* Shared functions. */
60 
dmub_dcn21_is_auto_load_done(struct dmub_srv * dmub)61 bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub)
62 {
63 	return (REG_READ(DMCUB_SCRATCH0) == 3);
64 }
65 
dmub_dcn21_is_phy_init(struct dmub_srv * dmub)66 bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub)
67 {
68 	return REG_READ(DMCUB_SCRATCH10) == 0;
69 }
70