1 /* $NetBSD: amdgpu_hw_translate.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $ */
2
3 /*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_translate.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $");
30
31 #include "dm_services.h"
32
33 /*
34 * Pre-requisites: headers required by header of this unit
35 */
36 #include "include/gpio_types.h"
37
38 /*
39 * Header of this unit
40 */
41
42 #include "hw_translate.h"
43
44 /*
45 * Post-requisites: headers required by this unit
46 */
47
48 #include "dce80/hw_translate_dce80.h"
49 #include "dce110/hw_translate_dce110.h"
50 #include "dce120/hw_translate_dce120.h"
51 #if defined(CONFIG_DRM_AMD_DC_DCN)
52 #include "dcn10/hw_translate_dcn10.h"
53 #endif
54 #include "dcn20/hw_translate_dcn20.h"
55 #include "dcn21/hw_translate_dcn21.h"
56
57 #include "diagnostics/hw_translate_diag.h"
58
59 /*
60 * This unit
61 */
62
dal_hw_translate_init(struct hw_translate * translate,enum dce_version dce_version,enum dce_environment dce_environment)63 bool dal_hw_translate_init(
64 struct hw_translate *translate,
65 enum dce_version dce_version,
66 enum dce_environment dce_environment)
67 {
68 if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
69 dal_hw_translate_diag_fpga_init(translate);
70 return true;
71 }
72
73 switch (dce_version) {
74 case DCE_VERSION_8_0:
75 case DCE_VERSION_8_1:
76 case DCE_VERSION_8_3:
77 dal_hw_translate_dce80_init(translate);
78 return true;
79 case DCE_VERSION_10_0:
80 case DCE_VERSION_11_0:
81 case DCE_VERSION_11_2:
82 case DCE_VERSION_11_22:
83 dal_hw_translate_dce110_init(translate);
84 return true;
85 case DCE_VERSION_12_0:
86 case DCE_VERSION_12_1:
87 dal_hw_translate_dce120_init(translate);
88 return true;
89 #if defined(CONFIG_DRM_AMD_DC_DCN)
90 case DCN_VERSION_1_0:
91 case DCN_VERSION_1_01:
92 dal_hw_translate_dcn10_init(translate);
93 return true;
94
95 case DCN_VERSION_2_0:
96 dal_hw_translate_dcn20_init(translate);
97 return true;
98 case DCN_VERSION_2_1:
99 dal_hw_translate_dcn21_init(translate);
100 return true;
101 #endif
102
103 default:
104 BREAK_TO_DEBUGGER();
105 return false;
106 }
107 }
108