Searched +full:zynqmp +full:- +full:pcap +full:- +full:fpga (Results 1 – 3 of 3) sorted by relevance
1 Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.2 The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the6 - compatible: should contain "xlnx,zynqmp-pcap-fpga"8 Example for full FPGA configuration:10 fpga-region0 {11 compatible = "fpga-region";12 fpga-mgr = <&zynqmp_pcap>;13 #address-cells = <0x1>;14 #size-cells = <0x1>;18 zynqmp_firmware: zynqmp-firmware {[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager10 - Nava kishore Manne <nava.kishore.manne@amd.com>13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.14 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to20 const: xlnx,zynqmp-pcap-fpga23 - compatible[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * dts file for Xilinx ZynqMP5 * (C) Copyright 2014 - 2021, Xilinx, Inc.15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>16 #include <dt-binding[all...]