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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrFoldTables.cpp1 //===-- X86InstrFoldTables.cpp - X86 Instruction Folding Tables -----------===//
9 // This file contains the X86 memory folding tables.
31 // because as new instruction are added into holes in the X86 opcode map they
36 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
37 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
38 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
39 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
40 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
41 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
42 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
[all …]
H A DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
9 // This file contains the X86 implementation of the TargetInstrInfo class.
14 #include "X86.h"
45 #define DEBUG_TYPE "x86-instr-info"
57 " fuse, but the X86 backend currently can't"),
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
81 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
83 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
84 X86::CATCHRET, in X86InstrInfo()
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H A DX86MCInstLower.cpp1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
9 // This file contains code to lower X86 MachineInstrs to their corresponding
330 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
348 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
349 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
350 NewOpcode = X86::CBW; in SimplifyMOVSX()
352 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
353 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
354 NewOpcode = X86::CWDE; in SimplifyMOVSX()
356 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
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H A DX86FloatingPoint.cpp25 #include "X86.h"
52 #define DEBUG_TYPE "x86-codegen"
84 StringRef getPassName() const override { return "X86 FP Stackifier"; } in getPassName()
131 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums"); in calcLiveInMask()
132 if (Reg >= X86::FP0 && Reg <= X86::FP6) { in calcLiveInMask()
133 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
195 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
202 /// getSTReg - Return the X86::ST(i) register which contains the specified
205 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
241 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
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H A DX86AvoidStoreForwardingBlocks.cpp36 #include "X86.h"
55 #define DEBUG_TYPE "x86-avoid-SFB"
58 "x86-disable-avoid-SFB", cl::Hidden,
59 cl::desc("X86: Disable Store Forwarding Blocks fixup."), cl::init(false));
62 "x86-sfb-inspection-limit",
63 cl::desc("X86: Number of instructions backward to "
77 return "X86 Avoid Store Forwarding Blocks"; in getPassName()
134 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
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H A DX86DomainReassignment.cpp15 #include "X86.h"
33 #define DEBUG_TYPE "x86-domain-reassignment"
38 "disable-x86-domain-reassignment", cl::Hidden,
39 cl::desc("X86: Disable Virtual Register Reassignment."), cl::init(false));
45 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
46 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
53 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
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H A DX86ExpandPseudo.cpp15 #include "X86.h"
29 #define DEBUG_TYPE "x86-pseudo"
30 #define X86_EXPAND_PSEUDO_NAME "X86 pseudo instruction expansion pass"
59 return "X86 pseudo instruction expansion pass"; in getPassName()
75 /// Expand X86::VASTART_SAVE_XMM_REGS into set of xmm copying instructions,
106 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11) in INITIALIZE_PASS()
107 .addReg(X86::RIP) in INITIALIZE_PASS()
113 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr)) in INITIALIZE_PASS()
115 .addReg(X86::R11); in INITIALIZE_PASS()
121 if (!MBB->isLiveIn(X86::EFLAGS)) in INITIALIZE_PASS()
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H A DX86InstructionSelector.cpp10 /// X86.
15 #include "X86.h"
50 #define DEBUG_TYPE "X86-isel"
171 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
173 return &X86::GR8RegClass; in getRegClass()
175 return &X86::GR16RegClass; in getRegClass()
177 return &X86::GR32RegClass; in getRegClass()
179 return &X86::GR64RegClass; in getRegClass()
181 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
183 return STI.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass; in getRegClass()
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H A DX86FlagsCopyLowering.cpp18 /// SAHF don't work on all x86 processors and are often quite slow compared to
23 #include "X86.h"
65 #define PASS_KEY "x86-flags-copy-lowering"
76 using CondRegArray = std::array<unsigned, X86::LAST_VALID_COND + 1>;
82 StringRef getPassName() const override { return "X86 EFLAGS copy lowering"; } in getPassName()
102 const DebugLoc &TestLoc, X86::CondCode Cond);
105 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
136 "X86 EFLAGS copy lowering", false, false)
138 "X86 EFLAGS copy lowering", false, false)
175 case X86::MNEMONIC##8##SUFFIX: \ in getMnemonicFromOpcode()
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H A DX86FastISel.cpp1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
9 // This file defines the X86-specific support for the FastISel class. Much
15 #include "X86.h"
170 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
228 X86::AddrIndexReg); in addFullAddress()
234 bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I, in foldX86XALUIntrinsic()
254 X86::CondCode TmpCC; in foldX86XALUIntrinsic()
260 case Intrinsic::umul_with_overflow: TmpCC = X86::COND_O; break; in foldX86XALUIntrinsic()
262 case Intrinsic::usub_with_overflow: TmpCC = X86::COND_B; break; in foldX86XALUIntrinsic()
312 // We only handle legal types. For example, on x86-32 the instruction in isTypeLegal()
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H A DX86RegisterInfo.cpp1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // on X86.
43 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
47 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
50 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
66 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo()
67 FramePtr = Use64BitReg ? X86::RBP : X86::EBP; in X86RegisterInfo()
68 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; in X86RegisterInfo()
71 StackPtr = X86::ESP; in X86RegisterInfo()
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H A DX86TargetTransformInfo.h1 //===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
10 /// X86 target machine. It uses the target's detailed information to
41 X86::Feature64Bit,
44 X86::FeatureNOPL,
45 X86::FeatureCMPXCHG16B,
46 X86::FeatureLAHFSAHF,
49 X86::FeatureFast11ByteNOP,
50 X86::FeatureFast15ByteNOP,
51 X86::FeatureFastBEXTR,
52 X86::FeatureFastHorizontalOps,
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H A DX86EvexToVex.cpp24 #include "X86.h"
56 #define EVEX2VEX_NAME "x86-evex-to-vex-compress"
120 if (Reg >= X86::XMM16 && Reg <= X86::XMM31) in usesExtendedRegister()
124 if (Reg >= X86::YMM16 && Reg <= X86::YMM31) in usesExtendedRegister()
138 assert(!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31) && in usesExtendedRegister()
154 case X86::VALIGNDZ128rri: in performCustomAdjustments()
155 case X86::VALIGNDZ128rmi: in performCustomAdjustments()
156 case X86::VALIGNQZ128rri: in performCustomAdjustments()
157 case X86::VALIGNQZ128rmi: { in performCustomAdjustments()
158 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
9 // This file provides X86 specific target descriptions.
72 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
77 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
87 {codeview::RegisterId::AL, X86::AL}, in initLLVMToSEHAndCVRegMapping()
88 {codeview::RegisterId::CL, X86::CL}, in initLLVMToSEHAndCVRegMapping()
89 {codeview::RegisterId::DL, X86::DL}, in initLLVMToSEHAndCVRegMapping()
90 {codeview::RegisterId::BL, X86::BL}, in initLLVMToSEHAndCVRegMapping()
91 {codeview::RegisterId::AH, X86::AH}, in initLLVMToSEHAndCVRegMapping()
92 {codeview::RegisterId::CH, X86::CH}, in initLLVMToSEHAndCVRegMapping()
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H A DX86InstPrinterCommon.cpp1 //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
111 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; in printVPCOMMnemonic()
112 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; in printVPCOMMnemonic()
113 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; in printVPCOMMnemonic()
114 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; in printVPCOMMnemonic()
115 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; in printVPCOMMnemonic()
116 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; in printVPCOMMnemonic()
117 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; in printVPCOMMnemonic()
118 case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break; in printVPCOMMnemonic()
130 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: in printVPCMPMnemonic()
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H A DX86IntelInstPrinter.cpp46 if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
47 STI.getFeatureBits()[X86::Mode16Bit]) { in printInst()
72 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
73 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
74 case X86::CMPSDrm: case X86::CMPSDrr: in printVecCompareInstr()
75 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: in printVecCompareInstr()
76 case X86::CMPSSrm: case X86::CMPSSrr: in printVecCompareInstr()
77 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: in printVecCompareInstr()
99 case X86::VCMPPDrmi: case X86::VCMPPDrri: in printVecCompareInstr()
100 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: in printVecCompareInstr()
[all …]
H A DX86ATTInstPrinter.cpp57 if (MI->getOpcode() == X86::CALLpcrel32 && in printInst()
58 (STI.getFeatureBits()[X86::Mode64Bit])) { in printInst()
67 else if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
68 STI.getFeatureBits()[X86::Mode16Bit]) { in printInst()
92 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
93 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
94 case X86::CMPSDrm: case X86::CMPSDrr: in printVecCompareInstr()
95 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: in printVecCompareInstr()
96 case X86::CMPSSrm: case X86::CMPSSrr: in printVecCompareInstr()
97 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: in printVecCompareInstr()
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H A DX86BaseInfo.h1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
10 // the X86 target useful for the compiler back-end and the MC libraries.
26 namespace X86 {
78 // X86 specific condition code. These correspond to X86_*_COND in
102 // which can't be represented on x86 with a single condition. These
145 case X86::TEST16i16: in classifyFirstOpcodeInMacroFusion()
146 case X86::TEST16mr: in classifyFirstOpcodeInMacroFusion()
147 case X86::TEST16ri: in classifyFirstOpcodeInMacroFusion()
148 case X86::TEST16rr: in classifyFirstOpcodeInMacroFusion()
149 case X86::TEST32i32: in classifyFirstOpcodeInMacroFusion()
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H A DX86AsmBackend.cpp1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
40 /// A wrapper for holding a mask of the values from X86::AlignBranchBoundaryKind
53 addKind(X86::AlignBranchFused); in operator =()
55 addKind(X86::AlignBranchJcc); in operator =()
57 addKind(X86::AlignBranchJmp); in operator =()
59 addKind(X86::AlignBranchCall); in operator =()
61 addKind(X86::AlignBranchRet); in operator =()
63 addKind(X86::AlignBranchIndirect); in operator =()
66 << " to -x86-align-branch=; each element must be one of: fused, " in operator =()
73 void addKind(X86::AlignBranchBoundaryKind Value) { AlignBranchKind |= Value; } in addKind()
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/netbsd-src/sys/arch/x86/conf/
H A Dfiles.x861 # $NetBSD: files.x86,v 1.126 2023/06/14 01:27:47 rin Exp $
34 file arch/x86/x86/bios32.c bios32 needs-flag
41 file arch/x86/x86/cpu.c cpu & !xenpv
42 file arch/x86/x86/cpu_rng.c cpu | vcpu
50 file arch/x86/acpi/acpi_cpu_md.c acpicpu
54 file arch/x86/x86/coretemp.c coretemp
58 file arch/x86/x86/est.c est
59 file arch/x86/x86/intel_busclock.c est
63 file arch/x86/x86/odcm.c odcm
67 file arch/x86/x86/via_padlock.c padlock
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/netbsd-src/crypto/external/bsd/openssl.old/dist/fuzz/
H A Doids.txt1 OBJ_rsadsi="\x2A\x86\x48\x86\xF7\x0D"
2 OBJ_pkcs="\x2A\x86\x48\x86\xF7\x0D\x01"
3 OBJ_md2="\x2A\x86\x48\x86\xF7\x0D\x02\x02"
4 OBJ_md5="\x2A\x86\x48\x86\xF7\x0D\x02\x05"
5 OBJ_rc4="\x2A\x86\x48\x86\xF7\x0D\x03\x04"
6 OBJ_rsaEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x01"
7 OBJ_md2WithRSAEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x02"
8 OBJ_md5WithRSAEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x04"
9 OBJ_pbeWithMD2AndDES_CBC="\x2A\x86\x48\x86\xF7\x0D\x01\x05\x01"
10 OBJ_pbeWithMD5AndDES_CBC="\x2A\x86\x48\x86\xF7\x0D\x01\x05\x03"
[all …]
/netbsd-src/crypto/external/bsd/openssl/dist/fuzz/
H A Doids.txt10 OBJ_rsadsi="\x2A\x86\x48\x86\xF7\x0D"
11 OBJ_pkcs="\x2A\x86\x48\x86\xF7\x0D\x01"
12 OBJ_md2="\x2A\x86\x48\x86\xF7\x0D\x02\x02"
13 OBJ_md5="\x2A\x86\x48\x86\xF7\x0D\x02\x05"
14 OBJ_rc4="\x2A\x86\x48\x86\xF7\x0D\x03\x04"
15 OBJ_rsaEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x01"
16 OBJ_md2WithRSAEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x02"
17 OBJ_md5WithRSAEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x04"
18 OBJ_pbeWithMD2AndDES_CBC="\x2A\x86\x48\x86\xF7\x0D\x01\x05\x01"
19 OBJ_pbeWithMD5AndDES_CBC="\x2A\x86\x48\x86\xF7\x0D\x01\x05\x03"
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
45 "x86-experimental-lvi-inline-asm-hardening",
127 SwitchMode(X86::Mode32Bit); in MatchInstruction()
132 SwitchMode(X86::Mode16Bit); in MatchInstruction()
1118 X86::CondCode ParseConditionCode(StringRef CCode);
1196 return getSTI().getFeatureBits()[X86::Mode64Bit]; in is64BitMode()
1200 return getSTI().getFeatureBits()[X86::Mode32Bit]; in is32BitMode()
1204 return getSTI().getFeatureBits()[X86::Mode16Bit]; in is16BitMode()
1208 FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit}); in SwitchMode()
1282 !(BaseReg == X86::RIP || BaseReg == X86::EIP || in CheckBaseRegAndIndexRegAndScale()
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/netbsd-src/external/gpl3/binutils.old/dist/ld/
H A DChangeLog-202038 * emulparams/elf_x86_64.sh: Source x86-64-lam.sh.
39 * emulparams/x86-64-lam.sh: New file.
40 * testsuite/ld-x86-64/property-x86-lam-u48-1a.d: Likewise.
41 * testsuite/ld-x86-64/property-x86-lam-u48-1b.d: Likewise.
42 * testsuite/ld-x86-64/property-x86-lam-u48-2.d: Likewise.
43 * testsuite/ld-x86-64/property-x86-lam-u48-3a.d: Likewise.
44 * testsuite/ld-x86-64/property-x86-lam-u48-3b.d: Likewise.
45 * testsuite/ld-x86-64/property-x86-lam-u48-4.d: Likewise.
46 * testsuite/ld-x86-64/property-x86-lam-u48-5.d: Likewise.
47 * testsuite/ld-x86-64/property-x86-lam-u48.s: Likewise.
[all …]
/netbsd-src/external/gpl3/binutils/dist/ld/
H A DChangeLog-202038 * emulparams/elf_x86_64.sh: Source x86-64-lam.sh.
39 * emulparams/x86-64-lam.sh: New file.
40 * testsuite/ld-x86-64/property-x86-lam-u48-1a.d: Likewise.
41 * testsuite/ld-x86-64/property-x86-lam-u48-1b.d: Likewise.
42 * testsuite/ld-x86-64/property-x86-lam-u48-2.d: Likewise.
43 * testsuite/ld-x86-64/property-x86-lam-u48-3a.d: Likewise.
44 * testsuite/ld-x86-64/property-x86-lam-u48-3b.d: Likewise.
45 * testsuite/ld-x86-64/property-x86-lam-u48-4.d: Likewise.
46 * testsuite/ld-x86-64/property-x86-lam-u48-5.d: Likewise.
47 * testsuite/ld-x86-64/property-x86-lam-u48.s: Likewise.
[all …]

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