Home
last modified time | relevance | path

Searched +full:voltage +full:- +full:table (Results 1 – 25 of 156) sorted by relevance

1234567

/freebsd-src/sys/contrib/device-tree/Bindings/regulator/
H A Dpwm-regulator.txt6 Voltage Table: When in this mode, a voltage table (See below) of
7 predefined voltage <=> duty-cycle values must be
9 only operate at the voltages supplied in the table.
10 Intermediary duty-cycle values which would normally
11 allow finer grained voltage selection are ignored and
13 the user if the assumptions made in continuous-voltage
16 Continuous Voltage: This mode uses the regulator's maximum and minimum
18 regulator-{min,max}-microvolt properties to calculate
19 appropriate duty-cycle values. This allows for a much
21 voltage-table mode above. This solution does make an
[all …]
H A Dpwm-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
17 Voltage Table:
18 When in this mode, a voltage table (See below) of predefined voltage <=>
19 duty-cycle values must be provided via DT. Limitations are that the
[all …]
H A Drohm,bd71828-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/rohm,bd71828-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml.
16 The regulator controller is represented as a sub-node of the PMIC node
25 "^LDO[1-7]$":
32 regulator-name:
33 pattern: "^ldo[1-7]$"
[all …]
H A Drohm,bd71847-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/rohm,bd71847-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
15 Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml
21 regulator-boot-on at least for BUCK5. LDO6 is supplied by it and it must
23 voltage monitoring for LDO5/LDO6 can cause PMIC to reset.
30 "^LDO[1-6]$":
37 regulator-name:
[all …]
H A Drohm,bd71837-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/rohm,bd71837-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
15 Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.yaml
21 regulator-boot-on at least for BUCK6 and BUCK7 so that those are not
23 if they are disabled at startup the voltage monitoring for LDO5/LDO6 will
31 "^LDO[1-7]$":
38 regulator-name:
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/power/supply/
H A Dbattery.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
14 In smart batteries, these are typically stored in non-volatile memory
16 no appropriate non-volatile memory, or it is unprogrammed/incorrect.
27 Batteries must be referenced by chargers and/or fuel-gauges using a phandle.
28 The phandle's property should be named "monitored-battery".
32 const: simple-battery
34 device-chemistry:
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-dfll.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
8 oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
9 control module that will automatically adjust the VDD_CPU voltage by
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/opp/
H A Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v
[all...]
H A Dopp.txt2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
22 vol: voltage in microvolt
27 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
30 operating-points = <
[all …]
H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
19 Qualcomm Technologies, Inc. Process Voltage Scaling Tables
20 defines the voltage and frequency value based on the speedbin blown in
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/thermal/
H A Dgeneric-adc-thermal.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/thermal/generic-ad
[all...]
H A Dthermal-generic-adc.txt4 one of ADC channel and sensor resistance is read via voltage across the
5 sensor resistor. The voltage read across the sensor is mapped to
6 temperature using voltage-temperature lookup table.
10 - compatible: Must be "generic-adc-thermal".
11 - #thermal-sensor-cells: Should be 1. See Documentation/devicetree/bindings/thermal/thermal-sen…
15 - temperature-lookup-table: Two dimensional array of Integer; lookup table
18 looked up on the table to get the equivalent
29 #include <dt-bindings/thermal/thermal.h>
35 sampling-frequency = <3300>;
36 #io-channel-cells = <1>;
[all …]
/freebsd-src/sys/x86/cpufreq/
H A Dest.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
52 /* Status/control registers (from the IA-32 System Programming Guide). */
86 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
90 /* Format for storing IDs in our table. */
102 static int strict = -1;
116 * Frequency (MHz) and voltage (mV) settings.
121 * processors with this table method. If ACPI Px states are supported,
125 * Order Number 252612-003, Table 5.
171 /* 130nm 1.30GHz Low Voltage Pentium M */
[all …]
/freebsd-src/sys/net/
H A Dsff8472.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013 George V. Neville-Neil
30 * The following set of constants are from Document SFF-8472
40 * 0-95 Serial ID Defined by SFP MSA
41 * 96-127 Vendor Specific Data
42 * 128-255 Reserved
45 * 0-55 Alarm and Warning Thresholds
46 * 56-95 Cal Constants
47 * 96-119 Real Time Diagnostic Interface
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/sound/
H A Dsgtl5000.txt4 - compatible : "fsl,sgtl5000".
6 - reg : the I2C address of the device
8 - #sound-dai-cells: must be equal to 0
10 - clocks : the clock provider of SYS_MCLK
12 - VDDA-supply : the regulator provider of VDDA
14 - VDDIO-supply: the regulator provider of VDDIO
18 - VDDD-supply : the regulator provider of VDDD
20 - micbias-resistor-k-ohms : the bias resistor to be used in kOhms
26 - micbias-voltage-m-volts : the bias voltage to be used in mVolts
27 The voltage can take values from 1.25V to 3V by 250mV steps
[all …]
H A Dsgtl5000.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
13 - $ref: dai-common.yaml#
22 "#sound-dai-cells":
25 assigned-clock-parents: true
26 assigned-clock-rates: true
27 assigned-clocks: true
31 - description: the clock provider of SYS_MCLK
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/interconnect/
H A Dmediatek,cci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
10 - Jia-Wei Chang <jia-wei.chang@mediatek.com>
11 - Johnson Wang <johnson.wang@mediatek.com>
15 MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
16 hardware. It can also optimize the voltage to reduce the power consumption.
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
[all …]
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
24 line. The power line might be shared among one more sub-blocks. So, we can
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/power/avs/
H A Dqcom,cpr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <nks@flawful.org>
17 temperature, etc. and suggests adjustments to the voltage to save power
23 - enum:
24 - qcom,qcs404-cpr
25 - const: qcom,cpr
36 - description: Reference clock.
38 clock-names:
[all …]
/freebsd-src/sys/arm64/nvidia/tegra210/
H A Dtegra210_cpufreq.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
48 /* CPU voltage table entry */
57 int min_uvolt; /* Min allowed CPU voltage */
58 int max_uvolt; /* Max allowed CPU voltage */
59 int step_uvolt; /* Step of CPU voltage */
61 int speedo_nitems; /* Size of speedo table */
62 struct speedo_entry *speedo_tbl; /* CPU voltage table */
67 int uvolt; /* Requested voltage */
72 {204000000UL, 1007452, -23865, 370},
[all …]
/freebsd-src/sys/arm/nvidia/tegra124/
H A Dtegra124_cpufreq.c1 /*-
49 /* CPU voltage table entry */
58 int min_uvolt; /* Min allowed CPU voltage */
59 int max_uvolt; /* Max allowed CPU voltage */
60 int step_uvolt; /* Step of CPU voltage */
62 int speedo_nitems; /* Size of speedo table */
63 struct speedo_entry *speedo_tbl; /* CPU voltage table */
68 int uvolt; /* Requested voltage */
73 { 204000000ULL, 1112619, -29295, 402},
74 { 306000000ULL, 1150460, -30585, 402},
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/hwmon/
H A Dntc-thermistor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 ---
3 $id: http://devicetree.org/schemas/hwmon/ntc-thermistor.yaml#
4 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Linus Walleij <linus.walleij@linaro.org>
13 vary in resistance in an often non-linear way in relation to temperature.
16 temperature is non-linear, software drivers most often need to use a look
17 up table and interpolation to get from resistance to temperature.
20 pull-up resistor or/and a pull-down resistor and a fixed voltage like this:
22 + e.g. 5V = pull-up voltage (puv)
[all …]
H A Dti,tmp513.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Eri
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/devfreq/
H A Dexynos-bus.txt4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
16 - parent bus device
17 - passive bus device
20 The parent bus device can only change the voltage of shared power line
26 VDD_xxx |--- A block (parent)
27 |--- B block (passive)
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/cpufreq/
H A Dqcom-cpufreq-nvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
14 voltage is dynamically configured by Core Power Reduction (CPR) depending on
20 For old implementation efuses are parsed to select the correct opp table and
21 voltage and CPR is not supported/used.
28 - qcom,apq8064
29 - qcom,apq8096
[all …]

1234567