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/freebsd-src/sys/contrib/device-tree/Bindings/media/
H A Dqcom,msm8916-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,msm8916-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM8916 Venus video encode and decode accelerators
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
13 The Venus IP is a video encode and decode accelerator present
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,msm8916-venus
23 power-domains:
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H A Dqcom,sc7280-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sc7280-venus.yaml#
5 $schema: http://devicetree.org/meta-schema
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H A Dqcom,sc7180-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sc7180-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC7180 Venus video encode and decode accelerators
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
13 The Venus IP is a video encode and decode accelerator present
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,sc7180-venus
23 power-domains:
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H A Dqcom,sm8250-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sm8250-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8250 Venus video encode and decode accelerators
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
13 The Venus IP is a video encode and decode accelerator present
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,sm8250-venus
23 power-domains:
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H A Dqcom,msm8996-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,msm8996-venus.yaml#
5 $schema: http://devicetree.org/meta-schema
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H A Dqcom,sdm660-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sdm660-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM660 Venus video encode and decode accelerators
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
11 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
14 The Venus IP is a video encode and decode accelerator present
18 - $ref: qcom,venus-common.yaml#
22 const: qcom,sdm660-venus
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H A Dmediatek-vcodec.txt1 Mediatek Video Codec
3 Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
7 - compatible : must be one of the following string:
8 "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
9 "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
10 "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
11 "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
12 "mediatek,mt8192-vcodec-enc" for MT8192 encoder.
13 "mediatek,mt8183-vcodec-dec" for MT8183 decoder.
14 "mediatek,mt8195-vcodec-enc" for MT8195 encoder.
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H A Dqcom,sdm845-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sdm845-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM845 Venus video encode and decode accelerators
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
13 The Venus IP is a video encode and decode accelerator present
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,sdm845-venus
23 power-domains:
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H A Dqcom,sdm845-venus-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sdm845-venus-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM845 Venus v2 video encode and decode accelerators
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
13 The Venus IP is a video encode and decode accelerator present
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,sdm845-venus-v2
23 power-domains:
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H A Dallegro.txt1 Device-tree bindings for the Allegro DVT video IP codecs present in the Xilinx
2 ZynqMP SoC. The IP core may either be a H.264/H.265 encoder or H.264/H.265
10 - compatible: value should be one of the following
11 "allegro,al5e-1.1", "allegro,al5e": encoder IP core
12 "allegro,al5d-1.1", "allegro,al5d": decoder IP core
13 - reg: base and length of the memory mapped register region and base and
15 - reg-names: must include "regs" and "sram"
16 - interrupts: shared interrupt from the MCUs to the processing system
17 - clocks: must contain an entry for each entry in clock-names
18 - clock-names: must include "core_clk", "mcu_clk", "m_axi_core_aclk",
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H A Dmediatek,vcodec-encoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-encode
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/freebsd-src/sys/contrib/device-tree/Bindings/display/ti/
H A Dti,omap-dss.txt5 -------------------
12 a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
13 the encoder modules vary.
21 The encoder modules encode the received RGB pixel stream to a video output like
24 Video Ports
25 -----------
27 The DSS Core and the encoders have video port outputs. The structure of the
28 video ports is described in Documentation/devicetree/bindings/graph.txt,
29 and the properties for the ports and endpoints for each encoder are
32 The video ports are used to describe the connections to external hardware, like
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/freebsd-src/sys/contrib/device-tree/Bindings/display/bridge/
H A Drenesas,lvds.txt1 Renesas R-Car LVDS Encoder
4 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
5 Gen2, R-Car Gen3 and RZ/G SoCs.
9 - compatible : Shall contain one of
10 - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
11 - "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders
12 - "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders
13 - "renesas,r8a774b1-lvds" for R8A774B1 (RZ/G2N) compatible LVDS encoders
14 - "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
15 - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
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H A Dlvds-codec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/lvds-codec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
16 LVDS is a physical layer specification defined in ANSI/TIA/EIA-64
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H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This binding describes the MIPI DSI encoder embedded in the Renesas
14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
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H A Dchrontel,ch7033.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Chrontel CH7033 Video Encoder
11 - Lubomir Rintel <lkundrak@v3.sk>
28 Video port for RGB input.
34 dvi-connector binding.
37 - port@0
38 - port@1
41 - compatible
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H A Dti,tfp410.txt1 TFP410 DPI to DVI encoder
5 - compatible: "ti,tfp410"
8 - powerdown-gpios: power-down gpio
9 - reg: I2C address. If and only if present the device node should be placed
11 - ti,deskew: data de-skew in 350ps increments, from -4 to +3, as configured
17 This device has two video ports. Their connections are modeled using the OF
20 - Port 0 is the DPI input port. Its endpoint subnode shall contain a
21 pclk-sample and bus-width property and a remote-endpoint property as specified
23 - If pclk-sample is not defined, pclk-sample = 0 should be assumed for
25 - If bus-width is not defined then bus-width = 24 should be assumed for
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H A Dsil-sii8620.txt4 - compatible: "sil,sii8620"
5 - reg: i2c address of the bridge
6 - cvcc10-supply: Digital Core Supply Voltage (1.0V)
7 - iovcc18-supply: I/O Supply Voltage (1.8V)
8 - interrupts: interrupt specifier of INT pin
9 - reset-gpios: gpio specifier of RESET pin
10 - clocks, clock-names: specification and name of "xtal" clock
11 - video interfaces: Device node can contain video interface port
12 node for HDMI encoder according to [1].
14 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
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H A Drenesas,dsi-csi2-tx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
20 - renesas,r8a779a0-dsi-csi2-tx # for V3U
21 - renesas,r8a779g0-dsi-csi2-tx # for V4H
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H A Dsii9234.txt4 - compatible : "sil,sii9234".
5 - reg : I2C address for TPI interface, use 0x39
6 - avcc33-supply : MHL/USB Switch Supply Voltage (3.3V)
7 - iovcc18-supply : I/O Supply Voltage (1.8V)
8 - avcc12-supply : TMDS Analog Supply Voltage (1.2V)
9 - cvcc12-supply : Digital Core Supply Voltage (1.2V)
10 - interrupts: interrupt specifier of INT pin
11 - reset-gpios: gpio specifier of RESET pin (active low)
12 - video interfaces: Device node can contain two video interface port
13 nodes for HDMI encoder and connector according to [1].
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H A Dtda998x.txt1 Device-Tree bindings for the NXP TDA998x HDMI transmitter
4 - compatible: must be "nxp,tda998x"
6 - reg: I2C address
9 - port: Input port node with endpoint definition, as described
13 - interrupts: interrupt number and trigger type
16 - pinctrl-0: pin control group to be used for
19 - pinctrl-names: must contain a "default" entry.
21 - video-ports: 24 bits value which defines how the video controller
22 output is wired to the TDA998x input - default: <0x230145>
24 - audio-ports: array of 8-bit values, 2 values per one DAI[1].
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/freebsd-src/sys/contrib/device-tree/Bindings/display/
H A Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
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H A Dfaraday,tve200.txt1 * Faraday TV Encoder TVE200
5 - compatible: must be one of:
7 "cortina,gemini-tvc", "faraday,tve200"
9 - reg: base address and size of the control registers block
11 - interrupts: contains an interrupt specifier for the interrupt
14 - clock-names: should contain "PCLK" for the clock line clocking the
15 silicon and "TVE" for the 27MHz clock to the video driver
17 - clocks: contains phandle and clock specifier pairs for the entries
18 in the clock-names property. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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/freebsd-src/sys/contrib/device-tree/Bindings/media/i2c/
H A Dadv7343.txt1 * Analog Devices adv7343 video encoder
3 The ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP
4 package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite
5 (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard
6 definition (SD), enhanced definition (ED), or high definition (HD) video
10 - compatible: Must be "adi,adv7343"
13 - adi,power-mode-sleep-mode: on enable the current consumption is reduced to
16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
19 - ad,adv7343-power-mode-dac: array configuring the power on/off DAC's 1..6,
22 - ad,adv7343-sd-config-dac-out: array configure SD DAC Output's 1 and 2, 0 = OFF
[all …]
H A Dths8200.txt1 * Texas Instruments THS8200 video encoder
3 The ths8200 device is a digital to analog converter used in DVD players, video
4 recorders, set-top boxes.
7 - compatible : value must be "ti,ths8200"

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