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Searched +full:versal +full:- +full:firmware (Results 1 – 8 of 8) sorted by relevance

/freebsd-src/sys/contrib/device-tree/Bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilin
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H A Dxlnx,zynqmp-firmware.txt1 -----------------------------------------------------------------
2 Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
3 -----------------------------------------------------------------
5 The zynqmp-firmware node describes the interface to platform firmware.
6 ZynqMP has an interface to communicate with secure firmware. Firmware
7 driver provides an interface to firmware APIs. Interface APIs can be
14 - compatible: Must contain any of below:
15 "xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
16 "xlnx,versal-firmware" for Versal
17 - method: The method of calling the PM-API firmware layer.
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/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@amd.com>
13 The clock controller is a hardware block of Xilinx versal clock tree. It
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
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/freebsd-src/sys/contrib/device-tree/Bindings/reset/
H A Dxlnx,zynqmp-reset.txt1 --------------------------------------------------------------------------
2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
3 --------------------------------------------------------------------------
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
18 -------
20 -------
22 firmware {
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/freebsd-src/sys/contrib/device-tree/Bindings/fpga/
H A Dxlnx,versal-fpga.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,versal
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/freebsd-src/sys/contrib/device-tree/Bindings/bus/
H A Dxlnx,versal-net-cdx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 detect CDX bus and devices using the firmware.
15 on run-time.
20 are used to configure SMMU and GIC-ITS respectively.
22 iommu-map property is used to define the set of stream ids
26 The msi-map property is used to associate the devices with the
34 - Nipun Gupta <nipun.gupta@amd.com>
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/freebsd-src/sys/contrib/device-tree/Bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 +-------------------------------------+
16 +-------------------------------------+
17 +--------------------------------------------------+
18 TF-A | |
21 +--------------------------+ |
24 +--------------------------------------------------+
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/freebsd-src/share/misc/
H A Dpci_vendors5 # Date: 2024-11-25 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-250
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