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/freebsd-src/contrib/bmake/unit-tests/
H A Dvarmod-hash.mk6 # Test vectors for generating certain hashes. Found by a brute force
9 VECTORS+= 00000000 adjbuqnt
10 VECTORS+= 00000001 beiiyxdp
11 VECTORS+= 00000002 ajriwzqe
12 VECTORS+= 00000004 aimszzcb
13 VECTORS+= 00000008 afffvsgz
14 VECTORS+= 00000010 alkksbun
15 VECTORS+= 00000020 arqeianj
16 VECTORS+= 00000040 acgaltwv
17 VECTORS+= 00000080 addsjxec
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/freebsd-src/crypto/openssl/test/recipes/30-test_evp_data/
H A Devpmd_sha.txt91 # Some of the test vectors from the SHS CAVP for FIPS 180-4
121 # Some of the test vectors from the SHS CAVP for FIPS 180-4
155 # Empty input and \xA3x200 vectors are taken from
157 # Others are pairs of "LongMsg" vectors available at
158 # http://csrc.nist.gov/groups/STM/cavp/secure-hashing.html#test-vectors
265 # Following tests are pairs of *last* "VariableOut" vectors from
266 # http://csrc.nist.gov/groups/STM/cavp/secure-hashing.html#test-vectors
H A Devpciph_aes_common.txt16 Title = AES (from FIPS-197 test vectors)
24 # AES 192 ECB tests (from FIPS-197 test vectors, encrypt)
33 # AES 256 ECB tests (from FIPS-197 test vectors, encrypt)
42 # AES 128 ECB tests (from NIST test vectors, encrypt)
46 # AES 128 ECB tests (from NIST test vectors, decrypt)
50 # AES 192 ECB tests (from NIST test vectors, decrypt)
54 # AES 256 ECB tests (from NIST test vectors, decrypt)
58 # AES 128 CBC tests (from NIST test vectors, encrypt)
62 # AES 192 CBC tests (from NIST test vectors, encrypt)
66 # AES 256 CBC tests (from NIST test vectors, encrypt)
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H A Devpciph_aes_stitched.txt1 Title = AES-128-CBC-HMAC-SHA1 test vectors
33 Title = AES-256-CBC-HMAC-SHA1 test vectors
64 Title = AES-128-CBC-HMAC-SHA256 test vectors
96 Title = AES-256-CBC-HMAC-SHA256 test vectors
H A Devpmac_poly1305.txt84 # test vectors from "The Poly1305-AES message-authentication code"
111 # self-generated vectors exercise "significant" length such that* are handled by different code pat…
191 # test vectors from Google
224 # test vectors from Hanno Bock
256 # test vectors from Andrew Moon - nacl
H A Devpciph_aria.txt14 Title = ARIA test vectors from RFC5794 (and others)
31 # Additional ARIA mode vectors from http://210.104.33.10/ARIA/doc/ARIA-testvector-e.pdf
149 Title = ARIA GCM test vectors from RFC8269
167 Title = ARIA GCM self-generated test vectors
197 Title = ARIA CCM test vectors from IETF draft-ietf-avtcore-aria-srtp-02
H A Devpciph_aes_cts.txt9 # Original test vectors were taken from https://www.ietf.org/rfc/rfc3962.txt for CS3
12 Title = AES CBC Test vectors
38 Title = AES CBC CTS1 Test vectors
150 # Original test vectors were taken from https://www.ietf.org/rfc/rfc3962.txt for CS3
153 Title = AES CBC CTS2 Test vectors
240 Title = AES CBC CTS3 Test vectors
/freebsd-src/sys/contrib/device-tree/Bindings/pci/
H A Daltera-pcie-msi.txt9 "vector_slave": vectors slave port region
13 - num-vectors: number of vectors, range 1 to 32.
26 num-vectors = <32>;
H A Dmediatek-pcie-gen3.yaml16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
37 | | | | | | | | | | | | (MSI vectors)
42 With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43 each set has its own address for MSI message, and supports 32 MSI vectors
/freebsd-src/sys/dev/cxgbe/firmware/
H A Dt5fw_cfg_fpga.txt26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
62 # 8 Ingress Queue/MSI-X Vectors per application function
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
176 # NMSIX = 1088 # available MSI-X Vectors
191 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
199 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
206 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
213 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
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H A Dt6fw_cfg_fpga.txt25 # 4. MSI-X Vectors: 1088.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
188 # NMSIX = 1088 # available MSI-X Vectors
203 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
211 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
218 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
225 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
236 # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
[all …]
H A Dt4fw_cfg_uwire.txt26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
62 # 8 Ingress Queue/MSI-X Vectors per application function
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
159 # NMSIX = 1088 # available MSI-X Vectors
174 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
182 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
189 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
196 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
[all …]
H A Dt6fw_cfg_uwire.txt25 # 4. MSI-X Vectors: 1088.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
211 # NMSIX = 1088 # available MSI-X Vectors
226 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
234 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
241 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
248 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
259 # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
[all …]
H A Dt5fw_cfg_uwire.txt25 # 4. MSI-X Vectors: 1088.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 8 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
194 # NMSIX = 1088 # available MSI-X Vectors
209 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
217 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
224 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
231 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
242 # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
[all …]
/freebsd-src/contrib/llvm-project/clang/lib/Headers/
H A Dfmaintrin.h21 /// Computes a multiply-add of 128-bit vectors of [4 x float].
41 /// Computes a multiply-add of 128-bit vectors of [2 x double].
62 /// low 32 bits of 128-bit vectors of [4 x float].
91 /// low 64 bits of 128-bit vectors of [2 x double].
119 /// Computes a multiply-subtract of 128-bit vectors of [4 x float].
139 /// Computes a multiply-subtract of 128-bit vectors of [2 x double].
160 /// the low 32 bits of 128-bit vectors of [4 x float].
189 /// the low 64 bits of 128-bit vectors of [2 x double].
217 /// Computes a negated multiply-add of 128-bit vectors of [4 x float].
237 /// Computes a negated multiply-add of 128-bit vectors o
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/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmips-gic.txt23 - mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
26 - mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
52 mti,reserved-cpu-vectors = <7>;
53 mti,reserved-ipi-vectors = <40 8>;
H A Dmti,gic.yaml40 mti,reserved-cpu-vectors:
42 Specifies the list of CPU interrupt vectors to which the GIC may not
53 mti,reserved-ipi-vectors:
115 mti,reserved-cpu-vectors = <7>;
116 mti,reserved-ipi-vectors = <40 8>;
/freebsd-src/sys/dev/qat/qat_common/
H A Dadf_isr.c38 u_int *vectors; in adf_enable_msix() local
47 vectors = NULL; in adf_enable_msix()
50 vectors = malloc(num_vectors * sizeof(u_int), in adf_enable_msix()
53 vectors[hw_data->num_banks] = 1; in adf_enable_msix()
65 free(vectors, M_QAT); in adf_enable_msix()
69 if (vectors != NULL) { in adf_enable_msix()
71 pci_remap_msix(info_pci_dev->pci_dev, num_vectors, vectors); in adf_enable_msix()
72 free(vectors, M_QAT); in adf_enable_msix()
/freebsd-src/share/man/man4/
H A Dvmd.464 Limits number of Message Signaled Interrupt (MSI) vectors allowed to each
66 VMD can't distinguish MSI vectors of the same device, so there are no
71 Limits number of Extended Message Signaled Interrupt (MSI-X) vectors
73 VMD has limited number of interrupt vectors to map children interrupts into,
/freebsd-src/sys/dev/ice/
H A Dice_rdma.h72 * @brief Maximum number of MSI-X vectors that will be reserved
74 * Defines the maximum number of MSI-X vectors that an RDMA interface will
75 * have reserved in advance. Does not guarantee that many vectors have
123 * Defines a mapping for MSI-X vectors being requested by the peer RDMA driver
136 * @brief RDMA MSI-X vectors reserved for the peer RDMA driver
138 * Defines the segment of the MSI-X vectors for use by the RDMA driver. These
229 * info about msix vectors
/freebsd-src/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/
H A DFunctionComparator.h132 /// If both types are vectors, then vector with greater bitwidth is
134 /// If both types are vectors with the same bitwidth, then types
141 /// Stage 4: Types are neither vectors, nor pointers. And they differ.
149 /// [NFCT], [FCT, "others"], [FCT, pointers], [FCT, vectors]
165 /// [NFCT], [FCT, "others"], [FCT, pointers], [FCT, vectors]
187 /// The same logic with vectors, arrays and other possible complex types.
199 /// those should be vectors (if TyA is vector), pointers
204 /// Once again, just because we allow it to vectors and pointers only.
206 /// 2.1. All vectors with equal bitwidth to vector A, has equal bitwidth to
213 /// In another words, for pointers and vectors, we ignore top-level type and
[all …]
/freebsd-src/share/man/man9/
H A Duio.961 are used to transfer data between buffers and I/O vectors that might
90 The array of I/O vectors to be processed.
94 The number of I/O vectors present.
125 requires that the buffer and I/O vectors be accessible without
/freebsd-src/sys/dev/iavf/
H A Diavf_vc_iflib.c119 * iavf_map_queues - Map queues to interrupt vectors
122 * Request that the PF map queues to interrupt vectors. Misc causes, including
140 /* How many queue vectors, adminq uses one */ in iavf_map_queues()
141 // XXX: How do we know how many interrupt vectors we have? in iavf_map_queues()
153 /* Queue vectors first */ in iavf_map_queues()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp71 /// sub vectors of type \p T. Returns the sub-vectors in \p DecomposedVectors.
76 /// returns the transposed-vectors in \p TransposedVectors.
104 /// requires a wide-load instruction \p 'I', a group of interleaved-vectors
134 // Currently, lowering is supported for the following vectors: in isSupported()
136 // 1. Store and load of 4-element vectors of 64 bits on AVX. in isSupported()
137 // 2. Store of 16/32-element vectors of 8 bits on AVX. in isSupported()
139 // 1. Load of 16/32-element vectors of 8 bits on AVX. in isSupported()
241 // genShuffleBland - Creates shuffle according to two vectors.This function is
321 // Assuming we start from the following vectors in interleave8bitStride4VF8()
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/freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLowerMatrixIntrinsics.cpp137 // assuming \p Stride elements between start two consecutive vectors.
140 // vectors and \p NumElements must be set to the number of elements in a column
306 /// 2.1. Get column vectors for each argument. If we already lowered the in getNumRows()
307 /// definition of an argument, use the produced column vectors directly.
309 /// a set of column vectors, in getColumnTy()
311 /// yields a set of column vectors containing result matrix. Note that we in getColumnTy()
353 /// Wrapper class representing a matrix as a set of vectors, either in row or in addNumComputeOps()
354 /// column major layout. All vectors must have the same vector type. in addNumComputeOps()
356 SmallVector<Value *, 16> Vectors;
364 MatrixTy(ArrayRef<Value *> Vectors)
252 SmallVector<Value *, 16> Vectors; global() member in __anonf1ff33490111::LowerMatrixIntrinsics::MatrixTy
260 MatrixTy(ArrayRef<Value * > Vectors) MatrixTy() argument
324 iterator_range<SmallVector<Value *, 8>::iterator> vectors() { vectors() function in __anonf1ff33490111::LowerMatrixIntrinsics::MatrixTy
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