| /freebsd-src/sys/contrib/device-tree/Bindings/usb/ |
| H A D | mediatek,mtu3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediate
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| H A D | dwc2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare HS OTG USB 2.0 controller
10 - Ro
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| H A D | mediatek,musb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,musb.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Min Guo <min.guo@mediatek.com>
15 pattern: '^usb@[0-9a-f]+$'
19 - enum:
20 - mediatek,mt8516-musb
21 - mediatek,mt2701-musb
22 - mediatek,mt7623-musb
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| H A D | mediatek,mtu3.txt | 4 - compatible : should be "mediatek,<soc-model>-mtu3", "mediatek,mtu3",
5 soc-model is the name of SoC, such as mt8173, mt2712 etc,
8 - "mediatek,mt8173-mtu3"
9 - reg : specifies physical base address and size of the registers
10 - reg-names: should be "mac" for device IP and "ippc" for IP port control
11 - interrupts : interrupt used by the device IP
12 - power-domains : a phandle to USB power domain node to control USB's
14 - vusb33-supply : regulator of USB avdd3.3v
15 - clocks : a list of phandle + clock-specifier pairs, one for each
16 entry in clock-names
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| H A D | mediatek,musb.txt | 2 -------------------------------------------
5 - compatible : should be one of:
6 "mediatek,mt2701-musb"
8 followed by "mediatek,mtk-musb"
9 - reg : specifies physical base address and size of
11 - interrupts : interrupt used by musb controller
12 - interrupt-names : must be "mc"
13 - phys : PHY specifier for the OTG phy
14 - dr_mode : should be one of "host", "peripheral" or "otg",
15 refer to usb/generic.txt
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| H A D | qcom,wcd939x-usbss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/qco
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| H A D | generic.txt | 1 Generic USB Properties
4 - maximum-speed: tells USB controllers we want to work up to a certain
5 speed. Valid arguments are "super-speed-plus",
6 "super-speed", "high-speed", "full-speed" and
7 "low-speed". In case this isn't passed via DT, USB
10 - dr_mode: tells Dual-Role USB controllers that we want to work on a
13 passed via DT, USB DRD controllers should default to
15 - phy_type: tells USB controllers that we want to configure the core to support
16 a UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is
18 In case this isn't passed via DT, USB controllers should
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| H A D | usb-drd.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/usb-drd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic USB OTG Controller
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
13 otg-rev:
15 Tells usb driver the release number of the OTG and EH supplement with
16 which the device and its descriptors are compliant, in binary-coded
18 features (HNP/SRP/ADP) is enabled. If ADP is required, otg-rev should be
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| H A D | renesas,usb3-peri.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/usb/renesas,usb3-peri.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas USB 3.0 Peripheral controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - items:
16 - enum:
17 - renesas,r8a774a1-usb3-peri # RZ/G2M
18 - renesas,r8a774b1-usb3-peri # RZ/G2N
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| H A D | mediatek,mt6360-tcpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/mediatek,mt6360-tcpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT6360 Type-C Port Switch and Power Delivery controller
10 - ChiYuan Huang <cy_huang@richtek.com>
13 Mediatek MT6360 is a multi-functional device. It integrates charger, ADC, flash, RGB indicators,
14 regulators (BUCKs/LDOs), and TypeC Port Switch with Power Delivery controller.
15 This document only describes MT6360 Type-C Port Switch and Power Delivery controller.
20 - mediatek,mt6360-tcpc
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| H A D | realtek,rtd-dwc3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Realtek DWC3 USB SoC Controller Glue
11 - Stanley Chang <stanley_chang@realtek.com>
14 The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0
15 and USB 3.0 in host or dual-role mode.
20 - enum:
21 - realtek,rtd1295-dwc3
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| H A D | msm-hsusb.txt | 6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
18 USB PHY with optional OTG:
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
25 - regs: Offset and length of the register set in the memory map
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| H A D | ti,tps6598x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,tps6598x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments 6598x Type-C Port Switch and Power Delivery controller
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Texas Instruments 6598x Type-C Port Switch and Power Delivery controller
21 - ti,tps6598x
22 - apple,cd321x
23 - ti,tps25750
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| H A D | gpio-sbu-mux.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/gpi
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| /freebsd-src/sys/contrib/device-tree/Bindings/phy/ |
| H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| H A D | qcom,usb-8x16-phy.txt | 1 Qualcomm's APQ8016/MSM8916 USB transceiver controller
3 - compatible:
6 Definition: Should contain "qcom,usb-8x16-phy".
8 - reg:
10 Value type: <prop-encoded-array>
11 Definition: USB PHY base address and length of the register map
13 - clocks:
15 Value type: <prop-encoded-array>
16 Definition: See clock-bindings.txt section "consumers". List of
20 - clock-names:
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| H A D | phy-stm32-usbphyc.txt | 1 STMicroelectronics STM32 USB HS PHY controller
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
14 |_ PHY port#2 ----| |________________
23 - compatible: must be "st,stm32mp1-usbphyc"
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
26 - #address-cells: number of address cells for phys sub-nodes, must be <1>
27 - #size-cells: number of size cells for phys sub-nodes, must be <0>
30 - assigned-clocks: phandle + clock specifier for the PLL phy clock
31 - assigned-clock-parents: the PLL phy clock parent
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| /freebsd-src/sys/dev/usb/controller/ |
| H A D | ehci_pci.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
39 * and the USB 2.
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| H A D | uhci_pci.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #include <dev/usb/usb_core.h>
67 #include <dev/usb/usb_busdm
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| /freebsd-src/sys/contrib/device-tree/Bindings/extcon/ |
| H A D | extcon-rt8973a.txt | 2 * Richtek RT8973A - Micro USB Switch device
4 The Richtek RT8973A is Micro USB Switch with OVP and I2C interface. The RT8973A
5 is a USB port accessory detector and switch that is optimized to protect low
7 speed USB operation. Also, RT8973A support 'auto-configuration' mode.
8 If auto-configuration mode is enabled, RT8973A would control internal h/w patch
9 for USB D-/D+ switching.
12 - compatible: Should be "richtek,rt8973a-muic"
13 - reg: Specifies the I2C slave address of the MUIC block. It should be 0x14
14 - interrupts: Interrupt specifiers for detection interrupt sources.
19 compatible = "richtek,rt8973a-muic";
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| /freebsd-src/tools/tools/usbtest/ |
| H A D | usbtest.c | 1 /*-
2 * Copyright (c) 2010-2022 Hans Petter Selasky
37 #include <dev/usb/usb_ioctl.h>
79 temp |= (-0x800000); in usb_ts_rand_noise()
107 printf("] - %s:\n\n", title); in usb_ts_show_menu()
144 ptr[size - 1] = 0; in get_string()
151 else if (ptr[size - 1] == '\n') in get_string()
152 ptr[size - 1] = 0; in get_string()
166 return (-1); in get_integer()
168 return (-2); in get_integer()
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| /freebsd-src/sys/contrib/device-tree/Bindings/net/ |
| H A D | marvell,mvusb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell USB to MDIO Controller
10 - Tobias Waldekranz <tobias@waldekranz.com>
14 family of Ethernet switches. It allows you to configure the switch's registers
17 Since the device is connected over USB, there is no strict requirement of
19 the mv88e6xxx driver, you need a device tree node in which to place the switch
23 - $ref: mdio.yaml#
30 description: The USB port number on the host controller
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| /freebsd-src/sys/dev/usb/ |
| H A D | usb_handle_request.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
50 #include <dev/usb/usb.h>
51 #include <dev/usb/usbdi.h>
52 #include <dev/usb/usbdi_util.h>
57 #include <dev/usb/usb_core.h>
58 #include <dev/usb/usb_process.h>
59 #include <dev/usb/usb_busdma.h>
60 #include <dev/usb/usb_transfer.h>
61 #include <dev/usb/usb_device.h>
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