Home
last modified time | relevance | path

Searched +full:usb +full:- +full:controller (Results 1 – 25 of 1033) sorted by relevance

12345678910>>...42

/freebsd-src/sys/dev/usb/controller/
H A Duhci_pci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 /* Universal Host Controller Interface
39 /* The low level controller code for UHCI has been split into
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbd
[all...]
H A Dehci_pci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
38 * http://developer.intel.com/technology/usb/downloa
[all...]
H A Dxhci_pci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2010-2022 Hans Petter Selasky
48 #include <dev/usb/usb.h>
49 #include <dev/usb/usbdi.h>
51 #include <dev/usb/usb_cor
[all...]
H A Dohci_pci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
35 * USB Open Host Controller driver.
37 * OHCI spec: http://www.intel.com/design/usb/ohci11d.pdf
40 /* The low level controller code for OHCI has been split into
64 #include <dev/usb/us
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/phy/
H A Drealtek,usb2phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Realtek DHC SoCs USB 2.0 PHY
11 - Stanley Chang <stanley_chang@realtek.com>
14 Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoCs.
15 The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs
17 controller.
19 RTD1295/RTD1619 SoCs USB
20 The USB architecture includes three XHCI controllers.
[all …]
H A Drealtek,usb3phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Realtek DHC SoCs USB 3.0 PHY
11 - Stanley Chang <stanley_chang@realtek.com>
14 Realtek USB 3.0 PHY support the digital home center (DHC) RTD series SoCs.
15 The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs
17 controller.
19 RTD1295/RTD1619 SoCs USB
20 The USB architecture includes three XHCI controllers.
[all …]
H A Dmarvell,armada-cp110-utmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utm
[all...]
H A Dallwinner,sun8i-h3-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H3 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-h3-usb-phy
20 - allwinner,sun50i-h616-usb-phy
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/usb/
H A Dexynos-usb.txt1 Samsung Exynos SoC USB controller
3 The USB devices interface with USB controllers on Exynos SOCs.
8 - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
9 EHCI controller in host mode.
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupts: interrupt number to the cpu.
13 - clocks: from common clock binding: handle to usb clock.
14 - clock-names: from common clock binding: Shall be "usbhost".
15 - phys: from the *Generic PHY* bindings; array specifying phy(s) used
17 - phy-names: from the *Generic PHY* bindings; array of the names for
[all …]
H A Dam33xx-usb.txt3 - compatible: ti,am33xx-usb
4 - reg: offset and length of the usbss register sets
5 - ti,hwmods : must be "usb_otg_hs"
8 at least a control module node, USB node and a PHY node. The second USB
13 - compatible: ti,am335x-usb-ctrl-module
14 - reg: offset and length of the "USB control registers" in the "Control
15 Module" block. A second offset and length for the USB wake up control
17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
18 the USB wake up control register.
20 USB PHY
[all …]
H A Dmsm-hsusb.txt6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
10 Example EHCI controller device node:
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
18 USB PHY with optional OTG:
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
[all …]
H A Dfsl-usb.txt1 Freescale SOC USB controllers
3 The device node for a USB controller that is part of a Freescale
9 - compatible : Should be "fsl-usb2-mph" for multi port host USB
10 controllers, or "fsl-usb2-dr" for dual role USB controllers
11 or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121.
12 Wherever applicable, the IP version of the USB controller should
13 also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132).
14 - phy_type : For multi port host USB controllers, should be one of
15 "ulpi", or "serial". For dual role USB controllers, should be
17 - reg : Offset and length of the register set for the device
[all …]
H A Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 xHCI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
14 exposed by the Tegra XUSB pad controller.
20 - description: NVIDIA Tegra124
[all …]
H A Ds3c2410-usb.txt1 Samsung S3C2410 and compatible SoC USB controller
6 - compatible: should be "samsung,s3c2410-ohci" for USB host controller
7 - reg: address and length of the controller memory mapped region
8 - interrupts: interrupt number for the USB OHCI controller
9 - clocks: Should reference the bus and host clocks
10 - clock-names: Should contain two strings
11 "usb-bus-host" for the USB bus clock
12 "usb-host" for the USB host clock
17 compatible = "samsung,s3c2410-ohci";
21 clock-names = "usb-bus-host", "usb-host";
H A Dnvidia,tegra124-xusb.txt1 NVIDIA Tegra xHCI controller
4 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
5 the Tegra XUSB pad controller.
8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
[all …]
H A Dnvidia,tegra210-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 xHCI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
14 exposed by the Tegra XUSB pad controller.
18 const: nvidia,tegra210-xusb
[all …]
H A Dnvidia,tegra-xudc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra XUSB device mode controller (XUDC)
10 The Tegra XUDC controller supports both USB 2.0 HighSpeed/FullSpeed and
11 USB 3.0 SuperSpeed protocols.
14 - Nagarjuna Kristam <nkristam@nvidia.com>
15 - JC Kuo <jckuo@nvidia.com>
16 - Thierry Reding <treding@nvidia.com>
[all …]
/freebsd-src/share/man/man4/
H A Dxhci.42 .\" Copyright (c) 2011-2022 Hans Petter Selasky. All rights reserved.
30 .Nd USB eXtensible Host Controller driver
38 .Tn USB
39 eXtensible Host Controller Interface,
41 .Tn USB
43 .Tn USB
48 controller supports
49 .Tn USB
50 connection speeds from 5.0Gbps and above when using USB 3.x
58 subclass 3 (USB) and programming interface 48 (XHCI).
[all …]
H A Dusb.429 .Nm usb
35 .Bd -ragged -offset indent
36 .Cd "device usb"
42 .Bd -literal -offset indent
52 provides machine-independent bus support and drivers for
58 .Bl -tag -width 6n -offset indent
59 .It USB Controller (Bus)
60 .It USB Device
61 .It USB Driver
64 The controller attaches to a physical bus
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/dma/
H A Drenesas,usb-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,usb-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas USB DMA Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 - $ref: dma-controller.yaml#
18 - enum:
19 - renesas,r8a7742-usb-dmac # RZ/G1H
20 - renesas,r8a7743-usb-dmac # RZ/G1M
[all …]
H A Dste-dma40.txt1 * DMA40 DMA Controller
4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
[all …]
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
22 0: SPI controller 0
23 1: SD/MMC controller 0 (unused)
24 2: SD/MMC controller 1 (unused)
[all …]
/freebsd-src/sys/arm/broadcom/bcm2835/
H A Dbcm2838_xhci.c1 /*-
2 * SPDX-License-Identifier: ISC
22 * VIA VL805 controller on the Raspberry Pi 4.
23 * The VL805 is a generic xhci controller. However, in the newer hardware
25 * Instead, the VideoCore GPU must load the firmware into the controller at the
26 * appropriate time. This driver is a shim that pre-loads the firmware before
50 #include <dev/usb/usb.h>
51 #include <dev/usb/usbdi.h>
53 #include <dev/usb/usb_core.h>
54 #include <dev/usb/usb_busdma.h>
[all …]

12345678910>>...42