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/freebsd-src/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,sc8280xp-qmp-ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qm
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H A Dqcom,qmp-ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (UFS)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
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H A Dqcom,msm8996-qmp-ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (UFS, MSM8996)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
17 qcom,sc8280xp-qmp-ufs-phy.yaml.
22 - qcom,msm8996-qmp-ufs-phy
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H A Dqcom,qmp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Vinod Koul <vkoul@kernel.org>
14 QMP phy controller supports physical layer functionality for a number of
15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
20 - qcom,ipq6018-qmp-pcie-phy
21 - qcom,ipq6018-qmp-usb3-phy
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H A Dphy-mtk-ufs.txt1 MediaTek Universal Flash Storage (UFS) M-PHY binding
2 --------------------------------------------------------
4 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
5 Each UFS M-PHY node should have its own node.
7 To bind UFS M-PHY with UFS host controller, the controller node should
8 contain a phandle reference to UFS M-PHY node.
10 Required properties for UFS M-PHY nodes:
11 - compatible : Compatible list, contains the following controller:
12 "mediatek,mt8183-ufsphy" for ufs phy
14 - reg : Address and length of the UFS M-PHY register set.
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H A Dmediatek,ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek Universal Flash Storage (UFS) M-PHY
11 - Stanley Chu <stanley.chu@mediatek.com>
12 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
16 Each UFS M-PHY node should have its own node.
17 To bind UFS M-PHY with UFS host controller, the controller node should
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H A Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsun
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H A Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common PHY and network PCS transmit amplitude property
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
20 contains multiple values for various PHY modes, the
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/freebsd-src/sys/contrib/device-tree/Bindings/ufs/
H A Dufs-qcom.txt1 * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
4 Each UFS PHY node should have its own node.
6 To bind UFS PHY with UFS host controller, the controller node should
7 contain a phandle reference to UFS PHY node.
10 - compatible : compatible list, contains one of the following -
11 "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy,
12 "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
13 "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
15 - reg : should contain PHY register address space (mandatory),
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H A Dsamsung,exynos-ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/samsun
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H A Dufshcd-pltfrm.txt1 * Universal Flash Storage (UFS) Host Controller
3 UFSHC nodes are defined to describe on-chip UFS host controllers.
4 Each UFS controller instance should have its own node.
7 - compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"
10 SoC-specific compatible along with "qcom,ufshc" and
12 "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
13 "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
14 "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
15 "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
16 "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
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H A Dufs-mediatek.txt1 * Mediatek Universal Flash Storage (UFS) Host Controller
3 UFS nodes are defined to describe on-chip UFS hardware macro.
4 Each UFS Host Controller should have its own node.
6 To bind UFS PHY with UFS host controller, the controller node should
7 contain a phandle reference to UFS M-PHY node.
9 Required properties for UFS nodes:
10 - compatible : Compatible list, contains the following controller:
11 "mediatek,mt8183-ufshci" for MediaTek UFS host controller
13 "mediatek,mt8192-ufshci" for MediaTek UFS host controller
15 - reg : Address and length of the UFS register set.
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H A Dcdns,ufshc.txt1 * Cadence Universal Flash Storage (UFS) Controller
3 UFS nodes are defined to describe on-chip UFS host controllers.
4 Each UFS controller instance should have its own node.
5 Please see the ufshcd-pltfrm.txt for a list of all available properties.
8 - compatible : Compatible list, contains one of the following controllers:
9 "cdns,ufshc" - Generic CDNS HCI,
10 "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY
12 "jedec,ufs-2.0"
14 - reg : Address and length of the UFS register set.
15 - interrupts : One interrupt mapping.
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H A Dtc-dwc-g210-pltfrm.txt1 * Universal Flash Storage (UFS) DesignWare Host Controller
3 DWC_UFS nodes are defined to describe on-chip UFS host controllers and MPHY.
4 Each UFS controller instance should have its own node.
7 - compatible : compatible list must contain the PHY type & version:
8 "snps,g210-tc-6.00-20bit"
9 "snps,g210-tc-6.00-40bit"
11 "snps,dwc-ufshcd-1.40a"
13 "jedec,ufs-1.1"
14 "jedec,ufs-2.0"
16 - reg : <registers mapping>
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H A Dqcom,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/qco
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H A Dcdns,ufshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Universal Flash Storage (UFS) Controller
10 - Jan Kotas <jank@cadence.com>
12 # Select only our matches, not all jedec,ufs-2.0
18 - cdns,ufshc
19 - cdns,ufshc-m31-16nm
21 - compatible
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H A Dti,j721e-ufs.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI J721e UFS Host Controller Glue Driver
10 - Vignesh Raghavendra <vigneshr@ti.com>
15 - const: ti,j721e-ufs
19 description: address of TI UFS glue registers
23 description: phandle to the M-PHY clock
25 power-domains:
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/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,gcc-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280x
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H A Dqcom,gcc-sm8350.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm835
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H A Dqcom,sa8775p-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sa8775p-gc
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H A Dqcom,sm8550-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-gc
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H A Dqcom,sm8650-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8650-gc
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H A Dqcom,gcc-sm8450.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm845
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H A Dqcom,sm4450-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm4450-gc
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/freebsd-src/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos7.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
30 arm-pmu {
31 compatible = "arm,cortex-a57-pmu";
36 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
42 compatible = "fixed-clock";
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