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/freebsd-src/sys/contrib/device-tree/Bindings/serial/
H A Dcdns,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/cdns,uart
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H A Dcdns,uart.txt1 Binding for Cadence UART Controller
4 - compatible :
5 Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
7 - reg: Should contain UART controller registers location and length.
8 - interrupts: Should contain UART controller interrupts.
9 - clocks: Must contain phandles to the UART clocks
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk"
12 See ../clocks/clock-bindings.txt for details.
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/freebsd-src/sys/contrib/device-tree/src/xtensa/
H A Dcsp.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 compatible = "cdns,xtensa-xtfpga";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&pic>;
20 #address-cells = <1>;
21 #size-cells = <0>;
23 compatible = "cdns,xtensa-cpu";
29 compatible = "cdns,xtensa-pic";
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/freebsd-src/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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