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4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of19 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a27 description: Synopsys DW uMCTL2 DDR controller v3.80a29 - description: Synopsys DW uMCTL2 DDR controller30 const: snps,dw-umctl2-ddrc36 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"107 compatible = "snps,dw-umctl2-ddrc";