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/freebsd-src/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-xilinx.txt9 - compatible : Should be "xlnx,xps-gpio-1.00.a"
10 - reg : Address and length of the register set for the device
11 - #gpio-cells : Should be two. The first cell is the pin number and the
13 - gpio-controller : Marks the device node as a GPIO controller.
16 - clocks : Input clock specifier. Refer to common clock bindings.
17 - interrupts : Interrupt mapping for GPIO IRQ.
18 - xlnx,all-inputs : if n-th bit is setup, GPIO-n is input
19 - xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1
20 - xlnx,gpio-width : gpio width
21 - xlnx,tri-default : if n-th bit is 1, GPIO-n is in tristate mode
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H A Dxlnx,gpio-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neeli Srinivas <srinivas.neeli@amd.com>
14 to an AXI4-Lite interface. The AXI GPIO can be configured as either
15 a single or a dual-channel device. The width of each channel is
22 - xlnx,xps-gpio-1.00.a
27 "#gpio-cells":
28 const: 2
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBankInfo.cpp1 //===-- RISCVRegisterBankInfo.cpp --------
233 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); getInstrMapping() local
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H A DRISCVInstructionSelector.cpp1 //===-- RISCVInstructionSelector.cpp --------
122 const RISCVRegisterInfo &TRI; global() member in __anon7b0fd19b0111::RISCVInstructionSelector
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h1 //===- MipsOptionRecord.h - Abstraction for storing information -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // MipsOptionRecord - Abstraction for storing arbitrary information in
14 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
17 //===----------------------------------------------------------------------===//
33 virtual ~MipsOptionRecord() = default;
43 ri_cprmask[0] = ri_cprmask[1] = ri_cprmask[2] = ri_cprmask[3] = 0; in MipsRegInfoRecord()
46 const MCRegisterInfo *TRI = Context.getRegisterInfo(); in MipsRegInfoRecord() local
47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
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H A DMipsInstructionSelector.cpp1 //===- MipsInstructionSelector.cpp ---------
62 const MipsRegisterInfo &TRI; global() member in __anon7ebf425c0111::MipsInstructionSelector
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H A DMipsMachineFunction.cpp1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
23 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
33 MipsFunctionInfo::~MipsFunctionInfo() = default;
137 // 0. lui $2, %hi(_gp_disp) in initGlobalBaseReg()
138 // 1. addiu $2, $2, %lo(_gp_disp) in initGlobalBaseReg()
139 // 2. addu $globalbasereg, $2, $t9 in initGlobalBaseReg()
148 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure in initGlobalBaseReg()
149 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu) in initGlobalBaseReg()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp1 //===- AArch64RegisterBankInfo.cpp ---------
46 AArch64RegisterBankInfo(const TargetRegisterInfo & TRI) AArch64RegisterBankInfo() argument
296 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); getInstrAlternativeMappings() local
523 hasFPConstraints(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const hasFPConstraints() argument
561 onlyUsesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const onlyUsesFP() argument
578 onlyDefinesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const onlyDefinesFP() argument
668 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); getInstrMapping() local
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H A DAArch64InstructionSelector.cpp1 //===- AArch64InstructionSelector.cpp ---------
513 const AArch64RegisterInfo &TRI; global() member in __anon4478951f0111::AArch64InstructionSelector
635 getSubRegForClass(const TargetRegisterClass * RC,const TargetRegisterInfo & TRI,unsigned & SubReg) getSubRegForClass() argument
696 const TargetRegisterInfo *TRI = MIB.getMF().getSubtarget().getRegisterInfo(); createTuple() local
755 unsupportedBinOp(const MachineInstr & I,const AArch64RegisterBankInfo & RBI,const MachineRegisterInfo & MRI,const AArch64RegisterInfo & TRI) unsupportedBinOp() argument
934 getRegClassesForCopy(MachineInstr & I,const TargetInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) getRegClassesForCopy() argument
991 selectCopy(MachineInstr & I,const TargetInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) selectCopy() argument
4418 emitAddSub(const std::array<std::array<unsigned,2>,5> & AddrModeAndSizeToOpcode,Register Dst,MachineOperand & LHS,MachineOperand & RHS,MachineIRBuilder & MIRBuilder) const emitAddSub() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp1 //===-- GCNHazardRecognizers.cpp - GCN Hazard Recognizer Impls -------
570 const SIRegisterInfo *TRI = ST.getRegisterInfo(); getWaitStatesSinceDef() local
592 addRegUnits(const SIRegisterInfo & TRI,BitVector & BV,MCRegister Reg) addRegUnits() argument
598 addRegsToSet(const SIRegisterInfo & TRI,iterator_range<MachineInstr::const_mop_iterator> Ops,BitVector & DefSet,BitVector & UseSet) addRegsToSet() argument
740 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkDPPHazards() local
864 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkVALUHazardsHelper() local
893 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkVALUHazards() local
929 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkVALUHazards() local
953 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkVALUHazards() local
1050 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkRWLaneHazards() local
1113 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixVcmpxPermlaneHazards() local
1155 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixVMEMtoScalarWriteHazards() local
1211 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixSMEMtoVectorWriteHazards() local
1286 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixVcmpxExecWARHazard() local
1723 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixWMMAHazards() local
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H A DR600ExpandSpecialInstrs.cpp1 //===- R600ExpandSpecialInstrs.cpp - Expand special instructions ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
25 #define DEBUG_TYPE "r600-expand-special-instrs"
65 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
66 if (OpIdx > -1) { in SetFlagInNewMI()
67 uint64_t Val = OldMI->getOperand(OpIdx).getImm(); in SetFlagInNewMI()
68 TII->setImmOperand(*NewMI, Op, Val); in SetFlagInNewMI()
76 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
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H A DSIMachineFunctionInfo.cpp1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info --------
189 addPrivateSegmentBuffer(const SIRegisterInfo & TRI) addPrivateSegmentBuffer() argument
197 addDispatchPtr(const SIRegisterInfo & TRI) addDispatchPtr() argument
204 addQueuePtr(const SIRegisterInfo & TRI) addQueuePtr() argument
211 addKernargSegmentPtr(const SIRegisterInfo & TRI) addKernargSegmentPtr() argument
219 addDispatchID(const SIRegisterInfo & TRI) addDispatchID() argument
226 addFlatScratchInit(const SIRegisterInfo & TRI) addFlatScratchInit() argument
233 addImplicitBufferPtr(const SIRegisterInfo & TRI) addImplicitBufferPtr() argument
247 addPreloadedKernArg(const SIRegisterInfo & TRI,const TargetRegisterClass * RC,unsigned AllocSizeDWord,int KernArgIdx,int PaddingSGPRs) addPreloadedKernArg() argument
317 const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo(); shiftSpillPhysVGPRsToLowestRange() local
361 const SIRegisterInfo *TRI = ST.getRegisterInfo(); allocatePhysicalVGPRForSGPRSpills() local
464 const SIRegisterInfo *TRI = ST.getRegisterInfo(); allocateVGPRSpillToAGPR() local
552 getScavengeFI(MachineFrameInfo & MFI,const SIRegisterInfo & TRI) getScavengeFI() argument
607 regToString(Register Reg,const TargetRegisterInfo & TRI) regToString() argument
618 convertArgumentInfo(const AMDGPUFunctionArgInfo & ArgInfo,const TargetRegisterInfo & TRI) convertArgumentInfo() argument
670 SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo & MFI,const TargetRegisterInfo & TRI,const llvm::MachineFunction & MF) SIMachineFunctionInfo() argument
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H A DAMDGPURegisterBankInfo.cpp1 //===- AMDGPURegisterBankInfo.cpp ---------
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H A DAMDGPUInstructionSelector.cpp1 //===- AMDGPUInstructionSelector.cpp ---------
3064 computeIndirectRegIndex(MachineRegisterInfo & MRI,const SIRegisterInfo & TRI,const TargetRegisterClass * SuperRC,Register IdxReg,unsigned EltSize,GISelKnownBits & KnownBits) computeIndirectRegIndex() argument
4347 auto Default = std::pair(Root.getReg(), 0); selectFlatOffsetImpl() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp1 //===- PPCRegisterBankInfo.cpp ---------
30 PPCRegisterBankInfo(const TargetRegisterInfo & TRI) PPCRegisterBankInfo() argument
84 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); getInstrMapping() local
290 hasFPConstraints(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const hasFPConstraints() argument
333 onlyUsesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const onlyUsesFP() argument
352 onlyDefinesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const onlyDefinesFP() argument
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H A DPPCInstructionSelector.cpp1 //===- PPCInstructionSelector.cpp ---------
71 const PPCRegisterInfo &TRI; global() member in __anon55b96fb00111::PPCInstructionSelector
131 selectCopy(MachineInstr & I,const TargetInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) selectCopy() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1 //===- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -------===//
5 // SPDX-Licens
125 const TargetRegisterInfo *TRI; global() member
822 forAllMIsUntilDef(MachineInstr & MI,MCPhysReg DefReg,const TargetRegisterInfo * TRI,unsigned Limit,std::function<bool (MachineInstr &,bool)> & Fn) forAllMIsUntilDef() argument
844 updateDefinedRegisters(MachineInstr & MI,LiveRegUnits & Units,const TargetRegisterInfo * TRI) updateDefinedRegisters() argument
1421 canRenameMOP(const MachineOperand & MOP,const TargetRegisterInfo * TRI) canRenameMOP() argument
1455 canRenameUpToDef(MachineInstr & FirstMI,LiveRegUnits & UsedInBetween,SmallPtrSetImpl<const TargetRegisterClass * > & RequiredClasses,const TargetRegisterInfo * TRI) canRenameUpToDef() argument
1561 canRenameUntilSecondLoad(MachineInstr & FirstLoad,MachineInstr & SecondLoad,LiveRegUnits & UsedInBetween,SmallPtrSetImpl<const TargetRegisterClass * > & RequiredClasses,const TargetRegisterInfo * TRI) canRenameUntilSecondLoad() argument
1605 tryToFindRegisterToRename(const MachineFunction & MF,Register Reg,LiveRegUnits & DefinedInBB,LiveRegUnits & UsedInBetween,SmallPtrSetImpl<const TargetRegisterClass * > & RequiredClasses,const TargetRegisterInfo * TRI) tryToFindRegisterToRename() argument
1649 findRenameRegForSameLdStRegPair(std::optional<bool> MaybeCanRename,MachineInstr & FirstMI,MachineInstr & MI,Register Reg,LiveRegUnits & DefinedInBB,LiveRegUnits & UsedInBetween,SmallPtrSetImpl<const TargetRegisterClass * > & RequiredClasses,const TargetRegisterInfo * TRI) findRenameRegForSameLdStRegPair() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp1 //===- DetectDeadLanes.cpp - SubRegister Lane Usage Analysis --*- C++ -*---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
21 /// %2 = REG_SEQUENCE %0, sub0, %1, sub1
22 /// %3 = EXTRACT_SUBREG %2, sub1
26 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "detect-dead-lanes"
42 const TargetRegisterInfo *TRI) in DeadLaneDetector() argument
43 : MRI(MRI), TRI(TRI) { in DeadLaneDetector()
44 unsigned NumVirtRegs = MRI->getNumVirtRegs(); in DeadLaneDetector()
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H A DPrologEpilogInserter.cpp1 //===- PrologEpilogInserter.cpp - Insert Prolog/Epilog code in function ---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===-
224 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); runOnMachineFunction() local
613 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); insertCSRSaves() local
640 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); insertCSRRestores() local
1237 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); insertZeroCallUsedRegs() local
1399 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); replaceFrameIndexDebugInstr() local
1484 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); replaceFrameIndicesBackward() local
1528 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); replaceFrameIndices() local
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H A DTargetInstrInfo.cpp1 //===-- TargetInstrInfo.cpp - Target Instruction Information -------
49 getRegClass(const MCInstrDesc & MCID,unsigned OpNum,const TargetRegisterInfo * TRI,const MachineFunction & MF) const getRegClass() argument
392 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); getStackSlotRange() local
652 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); foldMemoryOperand() local
783 transferImplicitOperands(MachineInstr * MI,const TargetRegisterInfo * TRI) transferImplicitOperands() argument
1065 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); reassociateOps() local
1332 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); isSchedulingBoundary() local
1492 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); describeLoadedValue() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp1 //===- ARMInstructionSelector.cpp ---------
74 const ARMBaseRegisterInfo &TRI; global() member in __anon0997d8aa0111::ARMInstructionSelector
187 guessRegClass(unsigned Reg,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) guessRegClass() argument
212 selectCopy(MachineInstr & I,const TargetInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) selectCopy() argument
234 selectMergeValues(MachineInstrBuilder & MIB,const ARMBaseInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) selectMergeValues() argument
265 selectUnmergeValues(MachineInstrBuilder & MIB,const ARMBaseInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) selectUnmergeValues() argument
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H A DARMBaseInstrInfo.cpp1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information -------
1018 const TargetRegisterInfo *TRI = &getRegisterInfo(); copyPhysReg() local
1119 storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register SrcReg,bool isKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const storeRegToStackSlot() argument
1376 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register DestReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const loadRegFromStackSlot() argument
1667 const TargetRegisterInfo &TRI = getRegisterInfo(); expandMEMCPY() local
1711 const TargetRegisterInfo *TRI = &getRegisterInfo(); expandPostRAPseudo() local
2109 const TargetRegisterInfo *TRI = &getRegisterInfo(); isProfitableToIfCvt() local
2564 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo(); tryFoldSPUpdateIntoPushPop() local
3085 const TargetRegisterInfo *TRI = &getRegisterInfo(); optimizeCompareInstr() local
4129 getBundledDefMI(const TargetRegisterInfo * TRI,const MachineInstr * MI,unsigned Reg,unsigned & DefIdx,unsigned & Dist) getBundledDefMI() argument
4152 getBundledUseMI(const TargetRegisterInfo * TRI,const MachineInstr & MI,unsigned Reg,unsigned & UseIdx,unsigned & Dist) getBundledUseMI() argument
5074 getCorrespondingDRegAndLane(const TargetRegisterInfo * TRI,unsigned SReg,unsigned & Lane) getCorrespondingDRegAndLane() argument
5104 getImplicitSPRUseForDPRUse(const TargetRegisterInfo * TRI,MachineInstr & MI,unsigned DReg,unsigned Lane,unsigned & ImplicitSReg) getImplicitSPRUseForDPRUse() argument
5136 const TargetRegisterInfo *TRI = &getRegisterInfo(); setExecutionDomain() local
5591 registerDefinedBetween(unsigned Reg,MachineBasicBlock::iterator From,MachineBasicBlock::iterator To,const TargetRegisterInfo * TRI) registerDefinedBetween() argument
5599 findCMPToFoldIntoCBZ(MachineInstr * Br,const TargetRegisterInfo * TRI) findCMPToFoldIntoCBZ() argument
5824 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo(); findRegisterToSaveLRTo() local
5845 isLRAvailable(const TargetRegisterInfo & TRI,MachineBasicBlock::reverse_iterator I,MachineBasicBlock::reverse_iterator E) isLRAvailable() argument
5886 const TargetRegisterInfo &TRI = getRegisterInfo(); getOutliningCandidateInfo() local
6282 const TargetRegisterInfo *TRI = &getRegisterInfo(); getOutliningTypeImpl() local
6922 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); tooMuchRegisterPressure() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstructionSelector.cpp1 //===- SPIRVInstructionSelector.cpp ---------
51 const SPIRVRegisterInfo &TRI; global() member in __anon59deba520111::SPIRVInstructionSelector
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp1 //===-- PPCExpandAtomicPseudoInsts.cpp - Expand atomic pseudo instrs. -----===//
5 // SPDX-License-Identifie
33 const PPCRegisterInfo *TRI; global() member in __anon1ab142480111::PPCExpandAtomicPseudo
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp1 //===- X86InstructionSelector.cpp ---------
139 const X86RegisterInfo &TRI; global() member in __anon272fae590111::X86InstructionSelector
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