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/freebsd-src/sys/contrib/device-tree/Bindings/watchdog/
H A Dxlnx,xps-timebase-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
22 - $ref: watchdog.yaml#
27 - xlnx,xps-timebase-wdt-1.01.a
[all …]
H A Dof-xilinx-wdt.txt1 Xilinx AXI/PLB soft-core watchdog Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or
6 "xlnx,xps-timebase-wdt-1.01.a".
7 - reg : Physical base address and size
10 - clocks : Input clock specifier. Refer to common clock
12 - clock-frequency : Frequency of clock in Hz
13 - xlnx,wdt-enable-once : 0 - Watchdog can be restarted
14 1 - Watchdog can be enabled just once
15 - xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,
[all …]
/freebsd-src/sys/contrib/device-tree/src/powerpc/
H A Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
[all …]
H A Dps3.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #size-cells = <2>;
15 #address-cells = <2>;
33 * dtc expects a clock-frequency and timebase-frequency entries, so
38 * threads is with an ibm,ppc-interrupt-server#s entry. We'll put one
43 #size-cells = <0>;
44 #address-cells = <1>;
49 ibm,ppc-interrupt-server#s = <0x0 0x1>;
50 clock-frequency = <0>;
[all …]
H A Dsbc8548-pre.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #address-cells = <1>;
14 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <0x20>; // 32 bytes
33 i-cache-line-size = <0x20>; // 32 bytes
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>; // From uboot
[all …]
H A Dcurrituck.dts11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
[all …]
H A Dgamecube.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2007-2009 The GameCube Linux Team
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 bootargs = "root=/dev/gcnsda2 rootwait udbg-immortal";
28 #address-cells = <1>;
29 #size-cells = <0>;
34 clock-frequency = <486000000>; /* 486MHz */
35 bus-frequency = <162000000>; /* 162MHz core-to-bus 3x */
[all …]
H A Diss4xx.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
20 model = "ibm,iss-4xx";
21 compatible = "ibm,iss-4xx";
22 dcr-parent = <&{/cpus/cpu@0}>;
29 #address-cells = <1>;
30 #size-cells = <0>;
36 clock-frequency = <100000000>; // 100Mhz :-)
37 timebase-frequency = <100000000>;
[all …]
H A Dstorcenter.dts14 /dts-v1/;
19 #address-cells = <1>;
20 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 clock-frequency = <200000000>;
36 timebase-frequency = <25000000>;
37 bus-frequency = <0>; /* from bootwrapper */
38 i-cache-line-size = <32>;
39 d-cache-line-size = <32>;
[all …]
H A Dmedia5200.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 &gpt0 { fsl,has-wdt; };
24 stdout-path = &console;
29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
64 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
68 phy-handle = <&phy0>;
72 phy0: ethernet-phy@0 {
[all …]
/freebsd-src/sys/powerpc/booke/
H A Dplatform_bare.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2008-2012 Semihalf.
75 if (OF_peer(0) == -1) /* Needs device tree to work */ in bare_probe()
98 /* Backward compatibility. See 8-STABLE. */ in bare_timebase_freq()
107 if ((cpus = OF_finddevice("/cpus")) == -1) in bare_timebase_freq()
113 switch (OF_getproplen(child, "timebase-frequency")) { in bare_timebase_freq()
117 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase)); in bare_timebase_freq()
124 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase)); in bare_timebase_freq()
133 if (OF_getprop(child, "bus-frequency", (void *)&freq, in bare_timebase_freq()
[all …]
/freebsd-src/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8641si-pre.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
8 /dts-v1/;
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&mpic>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
[all …]
/freebsd-src/sys/dts/arm/
H A Dannapurna-alpine.dts1 /*-
28 /dts-v1/;
32 #address-cells = <1>;
33 #size-cells = <1>;
40 #address-cells = <1>;
41 #size-cells = <0>;
45 compatible = "arm,cortex-a15";
47 d-cache-line-size = <64>; // 64 bytes
48 i-cache-line-size = <64>; // 64 bytes
49 d-cache-size = <0x8000>; // L1, 32K
[all …]
/freebsd-src/contrib/ntp/scripts/monitoring/
H A Dloopwatch.config.SAMPLE18 # showfreq: yes/no control display of frequency values
27 # showfreg: yes/no control display of linear regression of frequency values
30 # timebase: dynamic/ISO_DATE_TIME point of zero for linear regression
31 # ISO_DATE_TIME: yyyy-mm-dd_hh:mm:ss.ms
37 timebase=dynamic
55 # timescale is labeled with hours relative to timebase
70 # limit display (y-axis) to values not larger than <number>
74 # limit display (y-axis) to values not smaller than <number>
/freebsd-src/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palme
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/freebsd-src/sys/cddl/dev/dtrace/powerpc/
H A Ddtrace_subr.c70 td->t_dtrace_trapframe = frame; in dtrace_invop()
71 for (hdlr = dtrace_invop_hdlr; hdlr != NULL; hdlr = hdlr->dtih_next) in dtrace_invop()
72 if ((rval = hdlr->dtih_func(addr, frame, arg0)) != 0) in dtrace_invop()
74 td->t_dtrace_trapframe = NULL; in dtrace_invop()
84 hdlr->dtih_func = func; in dtrace_invop_add()
85 hdlr->dtih_next = dtrace_invop_hdlr; in dtrace_invop_add()
96 panic("attempt to remove non-existent invop handler"); in dtrace_invop_remove()
98 if (hdlr->dtih_func == func) in dtrace_invop_remove()
102 hdlr = hdlr->dtih_next; in dtrace_invop_remove()
107 dtrace_invop_hdlr = hdlr->dtih_next; in dtrace_invop_remove()
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/timer/
H A Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
[all …]
/freebsd-src/sys/powerpc/mpc85xx/
H A Dplatform_mpc85xx.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2008-2012 Semihalf.
154 if ((cpus = OF_finddevice("/cpus")) != -1) { in mpc85xx_attach()
167 ccsr = -1; in mpc85xx_attach()
168 for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++) in mpc85xx_attach()
170 if (ccsr == -1) { in mpc85xx_attach()
187 if (ccsr == -1) in mpc85xx_attach()
190 OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells)); in mpc85xx_attach()
191 OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells)); in mpc85xx_attach()
[all …]
/freebsd-src/sys/riscv/riscv/
H A Dtimer.c1 /*-
2 * Copyright (c) 2015-2024 Ruslan Bukin <br@bsdpad.com>
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
36 * RISC-V Timer
72 .tc_name = "RISC-V Timecounter",
109 vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME; in riscv_timer_tc_fill_vdso_timehands()
110 bzero(vdso_th->th_res, sizeof(vdso_th->th_re in riscv_timer_tc_fill_vdso_timehands()
[all...]
/freebsd-src/sys/powerpc/powerpc/
H A Dplatform_if.m1 #-
41 * @defgroup PLATFORM platform - KObj methods for PowerPC platform
62 cpuref->cr_hwref = -1;
63 cpuref->cr_cpuid = 0;
110 * so the platform module can install its own high-priority MMU module at
164 * @brief Get the CPU's timebase frequency, in ticks per second.
166 * @param _cpu CPU whose timebase to query
253 * @brief Attempt to synchronize timebase of current CPU with others.
255 * Passed the timebase value on the BSP as of shortly before the call.
/freebsd-src/sys/contrib/device-tree/src/riscv/sifive/
H A Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pwm/pwm.h>
9 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
18 stdout-path = "serial0";
22 timebase-frequency = <RTCCLK_FREQ>;
[all …]
/freebsd-src/sys/powerpc/powermac/
H A Dplatform_powermac.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
139 if (memory == -1) in powermac_mem_regions()
142 /* "reg" has variable #address-cells, but #size-cells is always 1 */ in powermac_mem_regions()
143 OF_getprop(OF_parent(memory), "#address-cells", &physacells, in powermac_mem_regions()
152 /* On 32-bit PPC, ignore regions starting above 4 GB */ in powermac_mem_regions()
154 j--; in powermac_mem_regions()
166 /* "available" always has #address-cells = 1 */ in powermac_mem_regions()
229 int32_t ticks = -1; in powermac_timebase_freq()
231 phandle = cpuref->cr_hwref; in powermac_timebase_freq()
[all …]
/freebsd-src/sys/contrib/device-tree/src/riscv/microchip/
H A Dmicrochip-mpfs-icicle-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
6 #include "microchip-mpfs.dtsi"
8 /* Clock frequency (in Hz) of the rtcclk */
12 model = "Microchip PolarFire-SoC Icicle Kit";
13 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
25 stdout-path = "serial1:115200n8";
29 timebase-frequency = <RTCCLK_FREQ>;
48 clock-frequency = <125000000>;
[all …]
/freebsd-src/sys/contrib/device-tree/src/riscv/kendryte/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/k210-clk.h>
10 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
13 #address-cells = <1>;
14 #size-cells = <1>;
23 * Since this is a non-ratified draft specification, the kernel does not
28 #address-cells = <1>;
29 #size-cells = <0>;
30 timebase-frequency = <7800000>;
36 mmu-type = "none";
[all …]

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