| /freebsd-src/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | nvidia,tegra210-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra210-emc
26 - description: external memory clock
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| /freebsd-src/sys/contrib/device-tree/Bindings/reserved-memory/ |
| H A D | nvidia,tegra210-emc-table.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra210-emc-table.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 EMC Frequency Table
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: On Tegra210, firmware passes a binary representation of the
14 EMC frequency table via a reserved memory region.
17 - $ref: reserved-memory.yaml
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| /freebsd-src/sys/contrib/device-tree/src/arm64/nvidia/ |
| H A D | tegra186.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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| H A D | tegra194.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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| H A D | tegra234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gi
667 emc: external-memory-controller@2c60000 { global() label
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| H A D | tegra210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210
964 emc: external-memory-controller@7001b000 { global() label
[all...] |
| /freebsd-src/sys/contrib/device-tree/Bindings/gpu/host1x/ |
| H A D | nvidia,tegra210-nvdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 NVDEC is the hardware video decoder present on NVIDIA Tegra210
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra210-nvdec
25 - nvidia,tegra186-nvdec
[all …]
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| H A D | nvidia,tegra210-nvenc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 NVENC is the hardware video encoder present on NVIDIA Tegra210
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
[all …]
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| H A D | nvidia,tegra210-nvjpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvjpg@[0-9a-f]*$"
24 - nvidia,tegra210-nvjpg
25 - nvidia,tegra186-nvjpg
[all …]
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| H A D | nvidia,tegra234-nvdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 NVDEC is the hardware video decoder present on NVIDIA Tegra210
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra234-nvdec
32 clock-names:
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| /freebsd-src/sys/contrib/device-tree/Bindings/display/tegra/ |
| H A D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
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| /freebsd-src/sys/contrib/device-tree/Bindings/devfreq/ |
| H A D | nvidia,tegra30-actmon.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
23 - nvidia,tegra30-actmon
24 - nvidia,tegra114-actmon
25 - nvidia,tegra124-actmon
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| /freebsd-src/sys/arm64/nvidia/tegra210/ |
| H A D | tegra210_car.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
51 #include <dt-bindings/clock/tegra210-car.h>
58 {"nvidia,tegra210-car", 1},
293 {"emc", NULL, 0, 1},
321 rv = clknode_div_register(sc->clkdom, clks + i); in init_divs()
334 rv = clknode_gate_register(sc->clkdom, clks + i); in init_gates()
347 rv = clknode_mux_register(sc->clkdom, clks + i); in init_muxes()
361 CLKDEV_READ_4(sc->dev, OSC_CTRL, &val); in init_fixeds()
366 rv = clknode_fixed_register(sc->clkdom, &fixed_osc); in init_fixeds()
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| H A D | tegra210_clk_per.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 #include <dt-bindings/clock/tegra210-car.h>
40 #include <dt-bindings/reset/tegra210-car.h>
308 /* bank L -> 0-31 */
332 /* bank H -> 32-63 */
349 GATE(EMC, "emc", "pc_emc", H(25)),
353 /* bank U -> 64-95 */
378 /* bank V -> 96-127 */
398 /* bank W -> 128-159*/
[all …]
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| H A D | tegra210_clk_pll.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 #include <dt-bindings/clock/tegra210-car.h>
113 /* Post divider <-> register value mapping. */
270 /* PLLM: 880 MHz Clock source for EMC 2x clock */
282 /* PLLMB: 880 MHz Clock source for EMC 2x clock */
603 RD4(sc, sc->base_reg, ®); in pll_enable()
604 if (sc->type != PLL_E) in pll_enable()
607 WR4(sc, sc->base_reg, reg); in pll_enable()
616 RD4(sc, sc->base_reg, ®); in pll_disable()
[all …]
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