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/freebsd-src/sys/dev/clk/starfive/
H A Djh7110_clk_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
24 #include <dev/clk/clk.h>
25 #include <dev/clk/starfive/jh7110_clk.h>
26 #include <dev/clk/starfive/jh7110_clk_pll.h>
27 #include <dev/syscon/syscon.h>
29 #include <dt-bindings/clock/starfive,jh7110-crg.h>
50 sc->dacpd_mask = PLL## id ##_DACPD_MASK; \
51 sc->dsmpd_mask = PLL## id ##_DSMPD_MASK; \
52 sc->fbdiv_mask = PLL## id ##_FBDIV_MASK; \
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dsprd,sc9860-clk.txt2 ------------------------
5 - compatible: should contain the following compatible strings:
6 - "sprd,sc9860-pmu-gate"
7 - "sprd,sc9860-pll"
8 - "sprd,sc9860-ap-clk"
9 - "sprd,sc9860-aon-prediv"
10 - "sprd,sc9860-apahb-gate"
11 - "sprd,sc9860-aon-gate"
12 - "sprd,sc9860-aonsecure-clk"
13 - "sprd,sc9860-agcp-gate"
[all …]
H A Dpistachio-clock.txt6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
25 - reg: Must contain the base address and length of the core clock controller.
[all …]
H A Dsprd,sc9863a-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
16 "#clock-cells":
21 - sprd,sc9863a-ap-clk
22 - sprd,sc9863a-aon-clk
[all …]
/freebsd-src/sys/arm64/rockchip/
H A Drk_usbphy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 #include <dev/clk/clk.h>
43 #include <dev/syscon/syscon.h>
47 #include <dev/syscon/sysco
84 clk_t clk; global() member
87 struct syscon *syscon; global() member
147 clk_t clk; rk_usbphy_init_phy() local
150 struct syscon *syscon; rk_usbphy_init_phy() local
[all...]
H A Drk3399_emmcphy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
46 #include <dev/clk/clk.h>
47 #include <dev/syscon/syscon.h>
102 { "rockchip,rk3399-emmc-phy", 1 },
107 struct syscon *syscon; member
109 clk_t clk; member
112 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask))
150 SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON6, in rk_emmcphy_enable()
156 SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON0, in rk_emmcphy_enable()
[all …]
H A Drk_usb2phy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
46 #include <dev/clk/clk.h>
49 #include <dev/syscon/syscon.h>
83 { "rockchip,rk3399-usb2phy", (uintptr_t)&rk3399_regs },
84 { "rockchip,rk3568-usb2phy", (uintptr_t)&rk3568_regs },
90 struct syscon *grf;
92 clk_t clk; member
132 if (sc->phy_supply) { in rk_usb2phy_enable()
134 error = regulator_enable(sc->phy_supply); in rk_usb2phy_enable()
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schema
[all...]
H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwma
[all...]
/freebsd-src/sys/dev/clk/rockchip/
H A Drk_clk_mux.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
37 #include <dev/clk/clk.h>
38 #include <dev/syscon/syscon.h>
40 #include <dev/clk/rockchip/rk_cru.h>
41 #include <dev/clk/rockchip/rk_clk_mux.h>
59 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
64 static int rk_clk_mux_init(struct clknode *clk, device_t dev);
65 static int rk_clk_mux_set_mux(struct clknode *clk, int idx);
66 static int rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent,
[all …]
H A Drk_clk_composite.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 #include <dev/clk/clk.h>
33 #include <dev/syscon/syscon.h>
35 #include <dev/clk/rockchip/rk_clk_composite.h>
52 struct syscon *grf;
68 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
74 rk_clk_composite_read_4(struct clknode *clk, bus_addr_t addr, uint32_t *val) in rk_clk_composite_read_4() argument
78 sc = clknode_get_softc(clk); in rk_clk_composite_read_4()
79 if (sc->grf) in rk_clk_composite_read_4()
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/mfd/
H A Dcanaan,k210-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysct
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm64/sprd/
H A Dums512.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-paren
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,mmsys.txt9 - compatible: Should be one of:
10 - "mediatek,mt2701-mmsys", "syscon"
11 - "mediatek,mt2712-mmsys", "syscon"
12 - "mediatek,mt6765-mmsys", "syscon"
13 - "mediatek,mt6779-mmsys", "syscon"
14 - "mediatek,mt6797-mmsys", "syscon"
15 - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
16 - "mediatek,mt8167-mmsys", "syscon"
17 - "mediatek,mt8173-mmsys", "syscon"
18 - "mediatek,mt8183-mmsys", "syscon"
[all …]
H A Dmediatek,infracfg.txt9 - compatible: Should be one of:
10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6765-infracfg", "syscon"
13 - "mediatek,mt6779-infracfg_ao", "syscon"
14 - "mediatek,mt6797-infracfg", "syscon"
15 - "mediatek,mt7622-infracfg", "syscon"
16 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
17 - "mediatek,mt7629-infracfg", "syscon"
18 - "mediatek,mt7986-infracfg", "syscon"
[all …]
H A Dmediatek,imgsys.txt8 - compatible: Should be one of:
9 - "mediatek,mt2701-imgsys", "syscon"
10 - "mediatek,mt2712-imgsys", "syscon"
11 - "mediatek,mt6765-imgsys", "syscon"
12 - "mediatek,mt6779-imgsys", "syscon"
13 - "mediatek,mt6797-imgsys", "syscon"
14 - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
15 - "mediatek,mt8167-imgsys", "syscon"
16 - "mediatek,mt8173-imgsys", "syscon"
17 - "mediatek,mt8183-imgsys", "syscon"
[all …]
H A Dmediatek,vdecsys.txt8 - compatible: Should be one of:
9 - "mediatek,mt2701-vdecsys", "syscon"
10 - "mediatek,mt2712-vdecsys", "syscon"
11 - "mediatek,mt6779-vdecsys", "syscon"
12 - "mediatek,mt6797-vdecsys", "syscon"
13 - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
14 - "mediatek,mt8167-vdecsys", "syscon"
15 - "mediatek,mt8173-vdecsys", "syscon"
16 - "mediatek,mt8183-vdecsys", "syscon"
17 - #clock-cells: Must be 1
[all …]
H A Dmediatek,ipu.txt8 - compatible: Should be one of:
9 - "mediatek,mt8183-ipu_conn", "syscon"
10 - "mediatek,mt8183-ipu_adl", "syscon"
11 - "mediatek,mt8183-ipu_core0", "syscon"
12 - "mediatek,mt8183-ipu_core1", "syscon"
13 - #clock-cells: Must be 1
15 The ipu controller uses the common clk binding from
16 Documentation/devicetree/bindings/clock/clock-bindings.txt
17 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
21 ipu_conn: syscon@19000000 {
[all …]
H A Dmediatek,audsys.txt8 - compatible: Should be one of:
9 - "mediatek,mt2701-audsys", "syscon"
10 - "mediatek,mt6765-audsys", "syscon"
11 - "mediatek,mt6779-audio", "syscon"
12 - "mediatek,mt7622-audsys", "syscon"
13 - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
14 - "mediatek,mt8167-audiosys", "syscon"
15 - "mediatek,mt8183-audiosys", "syscon"
16 - "mediatek,mt8192-audsys", "syscon"
17 - "mediatek,mt8516-audsys", "syscon"
[all …]
H A Dmediatek,sgmiisys.txt8 - compatible: Should be:
9 - "mediatek,mt7622-sgmiisys", "syscon"
10 - "mediatek,mt7629-sgmiisys", "syscon"
11 - "mediatek,mt7981-sgmiisys_0", "syscon"
12 - "mediatek,mt7981-sgmiisys_1", "syscon"
13 - "mediatek,mt7986-sgmiisys_0", "syscon"
14 - "mediatek,mt7986-sgmiisys_1", "syscon"
15 - #clock-cells: Must be 1
17 The SGMIISYS controller uses the common clk binding from
18 Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
H A Dmediatek,ethsys.txt8 - compatible: Should be:
9 - "mediatek,mt2701-ethsys", "syscon"
10 - "mediatek,mt7622-ethsys", "syscon"
11 - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
12 - "mediatek,mt7629-ethsys", "syscon"
13 - "mediatek,mt7981-ethsys", "syscon"
14 - "mediatek,mt7986-ethsys", "syscon"
15 - #clock-cells: Must be 1
16 - #reset-cells: Must be 1
18 The ethsys controller uses the common clk binding from
[all …]
H A Dmediatek,mfgcfg.txt8 - compatible: Should be one of:
9 - "mediatek,mt2712-mfgcfg", "syscon"
10 - "mediatek,mt6779-mfgcfg", "syscon"
11 - "mediatek,mt8167-mfgcfg", "syscon"
12 - "mediatek,mt8183-mfgcfg", "syscon"
13 - #clock-cells: Must be 1
15 The mfgcfg controller uses the common clk binding from
16 Documentation/devicetree/bindings/clock/clock-bindings.txt
17 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
21 mfgcfg: syscon@13000000 {
[all …]
H A Dmediatek,vencsys.txt8 - compatible: Should be one of:
9 - "mediatek,mt2712-vencsys", "syscon"
10 - "mediatek,mt6779-vencsys", "syscon"
11 - "mediatek,mt6797-vencsys", "syscon"
12 - "mediatek,mt8173-vencsys", "syscon"
13 - "mediatek,mt8183-vencsys", "syscon"
14 - #clock-cells: Must be 1
16 The vencsys controller uses the common clk binding from
17 Documentation/devicetree/bindings/clock/clock-bindings.txt
18 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/nuvoton/
H A Dnuvoton-common-npcm8xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16 compatible = "simple-bus";
[all …]

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