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/freebsd-src/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
H A Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-ds
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H A Dti,keystone-rproc.txt5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
15 Each DSP Core sub-system is represented as a single DT node, and should also
17 or optional properties that enable the OS running on the host processor (ARM
18 CorePac) to perform the device management of the remote processor and to
19 communicate with the remote processor.
22 --------------------
25 - compatible: Should be one of the following,
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H A Dti,davinci-rproc.txt4 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
5 is used to offload some of the processor-intensive tasks or algorithms, for
8 The processor cores in the sub-system usually contain additional sub-modules
10 controller, a dedicated local power/sleep controller etc. The DSP processor
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H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 R5F processor subsystems
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
[all …]
H A Dmtk,scp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tingha
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/freebsd-src/sys/contrib/device-tree/Bindings/mailbox/
H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
15 external to the various processor subsystems and is connected on an
21 controller within a processor subsystem, and there can be more than one line
22 going to a specific processor's interrupt controller. The interrupt line
35 lines can also be routed to different processor sub-systems on DRA7xx as they
40 to different processor subsystems over a limited number of common interrupt
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H A Domap-mailbox.txt6 various processor subsystems and is connected on an interconnect bus. The
12 within a processor subsystem, and there can be more than one line going to a
13 specific processor's interrupt controller. The interrupt line connections are
25 routed to different processor sub-systems on DRA7xx as they are routed through
29 all these clusters are multiplexed and routed to different processor subsystems
38 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
41 --------------------
42 - compatible: Should be one of the following,
43 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
44 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
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/freebsd-src/contrib/ntp/scripts/ntpsweep/
H A Dntpsweep.in1 #! @PATH_PERL@ -w
34 sub run {
37 (((@_ != 1) && !$opts->{host} && !@{$opts->{'host-list'}}))) {
44 ($opts->{peers}, $opts->{maxlevel}, $opts->{strip});
52 if ($opts->{host}) {
53 push @hosts, $opts->{host};
57 push @hosts, @{$opts->{'host-list'}};
62 Host st offset(s) version system processor
63 --------------------------------+--+---------+-----------+------------+---------
73 sub scan_hosts {
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/freebsd-src/usr.sbin/bsnmpd/modules/snmp_hostres/
H A Dhostres_processor_tbl.c1 /*-
2 * Copyright (c) 2005-2006 The FreeBSD Project
5 * Author: Victor Cruceru <soc-victor@freebsd.org>
50 * for HOST-RESOURCES-MIB's hrProcessorTable.
87 * Returns the CPU usage of a given processor entry.
102 if (e->sample_cnt <= 1) in get_avg_load()
106 if (e->sample_cnt == MAX_CPU_SAMPLES) in get_avg_load()
107 oldest = (e->cur_sample_idx + 1) % MAX_CPU_SAMPLES; in get_avg_load()
113 delta += e->states[e->cur_sample_idx][i]; in get_avg_load()
114 delta -= e->states[oldest][i]; in get_avg_load()
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/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,kpss-gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
10 - Christian Marangi <ansuelsmth@gmail.com>
13 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
15 to the kpss-gcc registers.
20 - enum:
21 - qcom,kpss-gcc-ipq8064
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/freebsd-src/sys/contrib/device-tree/Bindings/bus/
H A Domap-ocp2scp.txt1 * OMAP OCP2SCP - ocp interface to scp interface
4 - compatible : Should be "ti,am437x-ocp2scp" for AM437x processor
5 Should be "ti,omap-ocp2scp" for all others
6 - reg : Address and length of the register set for the device
7 - #address-cells, #size-cells : Must be present if the device has sub-nodes
8 - ranges : the child address space are mapped 1:1 onto the parent address space
9 - ti,hwmods : must be "ocp2scp_usb_phy"
11 Sub-nodes:
12 All the devices connected to ocp2scp are described using sub-node to ocp2scp
15 compatible = "ti,omap-ocp2scp";
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h1 //===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
17 #include "llvm/Config/llvm-config.h"
30 /// Define a kind of processor resource that will be modeled by the scheduler.
39 // cycle after dispatch. This should be used for out-of-order cpus when
46 // in the same cycle. This is for in-order cpus, or the in-order portion of
47 // an out-of-order cpus.
50 // If the resource has sub-units, a pointer to the first element of an array
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/freebsd-src/sys/contrib/device-tree/Bindings/display/
H A Darm,malidp.txt1 ARM Mali-DP
9 - compatible: should be one of
10 "arm,mali-dp500"
11 "arm,mali-dp550"
12 "arm,mali-dp650"
14 - reg: Physical base address and size of the block of registers used by
15 the processor.
16 - interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
18 - interrupt-names: name of the engine inside the processor that will
20 - clocks: A list of phandle + clock-specifier pairs, one for each entry
[all …]
H A Darm,komeda.txt4 - compatible: Should be "arm,mali-d71"
5 - reg: Physical base address and length of the registers in the system
6 - interrupts: the interrupt line number of the device in the system
7 - clocks: A list of phandle + clock-specifier pairs, one for each entry
8 in 'clock-names'
9 - clock-names: A list of clock names. It should contain:
10 - "aclk": for the main processor clock
11 - #address-cells: Must be 1
12 - #size-cells: Must be 0
13 - iommus: configure the stream id to IOMMU, Must be configured if want to
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/freebsd-src/sys/contrib/device-tree/Bindings/mfd/
H A Dzii,rave-sp.txt1 Zodiac Inflight Innovations RAVE Supervisory Processor
3 RAVE Supervisory Processor communicates with SoC over UART. It is
9 - compatible: Should be one of:
10 - "zii,rave-sp-niu"
11 - "zii,rave-sp-mezz"
12 - "zii,rave-sp-esb"
13 - "zii,rave-sp-rdu1"
14 - "zii,rave-sp-rdu2"
16 - current-speed: Should be set to baud rate SP device is using
18 RAVE SP consists of the following sub-devices:
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DResourceManager.h1 //===--------------------- ResourceManager.h --------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// The classes here represent processor resource units and their management
13 //===----------------------------------------------------------------------===//
27 /// Used to notify the internal state of a processor resource.
29 /// A processor resource is available if it is not reserved, and there are
30 /// available slots in the buffer. A processor resource is unavailable if it
31 /// is either reserved, or the associated buffer is full. A processor resource
32 /// with a buffer size of -1 is always available if it is not reserved.
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/freebsd-src/sys/arm/arm/
H A Dexception.S3 /*-
4 * Copyright (c) 1994-1997 Mark Brinicombe.
77 * PUSHFRAME - macro to push a trap frame on the stack in the current mode
81 sub sp, sp, #4; /* Align the stack */ \
82 str lr, [sp, #-4]!; /* Push the return address */ \
83 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
84 stmia sp, {r0-r12}; /* Push the user mode registers */ \
86 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
89 str r0, [sp, #-4]!;
92 * PULLFRAME - macr
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Darm,coresight-dummy-source.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-dumm
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/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmips-gic.txt4 It also supports local (per-processor) interrupts and software-generated
5 interrupts which can be used as IPIs. The GIC also includes a free-running
6 global timer, per-CPU count/compare timers, and a watchdog.
9 - compatible : Should be "mti,gic".
10 - interrupt-controller : Identifies the node as an interrupt controller
11 - #interrupt-cells : Specifies the number of cells needed to encode an
13 - The first cell is the type of interrupt, local or shared.
14 See <include/dt-bindings/interrupt-controller/mips-gic.h>.
15 - The second cell is the GIC interrupt number.
16 - The third cell encodes the interrupt flags.
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/watchdog/
H A Dqcom-wdt.txt1 Qualcomm Krait Processor Sub-system (KPSS) Watchdog
2 ---------------------------------------------------
5 - compatible : shall contain only one of the following:
7 "qcom,kpss-wdt-msm8960"
8 "qcom,kpss-wdt-apq8064"
9 "qcom,kpss-wdt-ipq8064"
10 "qcom,kpss-wdt-ipq4019"
11 "qcom,kpss-timer"
12 "qcom,scss-timer"
13 "qcom,kpss-wdt"
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/freebsd-src/crypto/openssl/crypto/
H A Dx86_64cpuid.pl2 # Copyright 2005-2021 The OpenSSL Project Authors. All Rights Reserved.
18 ( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
19 ( $xlate="${dir}perlasm/x86_64-xlate.pl" and -f $xlate) or
20 die "can't locate x86_64-xlate.pl";
41 .type OPENSSL_atomic_add,\@abi-omnipotent
55 .size OPENSSL_atomic_add,.-OPENSSL_atomic_add
58 .type OPENSSL_rdtsc,\@abi-omnipotent
68 .size OPENSSL_rdtsc,.-OPENSSL_rdtsc
123 movzb %cl,%r10 # number of cores - 1
128 bt \$28,%edx # test hyper-threading bit
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/freebsd-src/sys/contrib/device-tree/Bindings/power/
H A Dqcom,kpss-acc-v2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2
10 - Christian Marangi <ansuelsmth@gmail.com>
17 power-manager for enabling the cpu.
21 const: qcom,kpss-acc-v2
25 - description: Base address and size of the register region
26 - description: Optional base address and size of the alias register region
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/freescale/
H A Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
3 The MSCM IP contains multiple sub modules, this binding describes the second
6 it controls the directed processor interrupts. The module is available in all
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/msm/
H A Dqcom,kpss-gcc.txt1 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
5 - compatible:
9 "qcom,kpss-gcc" should also be included.
10 "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
11 "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
12 "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
13 "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
15 - reg:
17 Value type: <prop-encoded-array>
20 - clocks:
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