sub\-mailbox (full) in projects: freebsd-src

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/freebsd-src/sys/contrib/device-tree/Bindings/mailbox/
H A D	ti,omap-mailbox.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: TI OMAP2+ and K3 Mailbox devices 10 - Suman Anna <s-anna@ti.com> 13 The OMAP Mailbox hardware facilitates communication between different 14 processors using a queued mailbox interrupt mechanism. The IP block is 19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and 35 lines can also be routed to different processor sub-systems on DRA7xx as they [all …]
H A D	omap-mailbox.txt	1 OMAP2+ and K3 Mailbox 4 The OMAP mailbox hardware facilitates communication between different processors 5 using a queued mailbox interrupt mechanism. The IP block is external to the 10 Each mailbox IP block/cluster has a certain number of h/w fifo queues and output 25 routed to different processor sub-systems on DRA7xx as they are routed through 35 Mailbox Device Node: 37 A Mailbox device node is used to represent a Mailbox IP instance/cluster within 38 a SoC. The sub-mailboxes are represented as child nodes of this parent node. 41 -------------------- 42 - compatible: Should be one of the following, [all …]
H A D	mtk-gce.txt	8 CMDQ driver uses mailbox framework for communication. Please refer to 9 mailbox.txt for generic information about mailbox device-tree bindings. 12 - compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce", 13 "mediatek,mt8186-gce", "mediatek,mt8192-gce", "mediatek,mt8195-gce" or 14 "mediatek,mt6779-gce". 15 - reg: Address range of the GCE unit 16 - interrupts: The interrupt signal from the GCE block 17 - clock: Clocks according to the common clock binding 18 - clock-names: Must be "gce" to stand for GCE clock 19 - #mbox-cells: Should be 2. [all …]
/freebsd-src/sys/contrib/device-tree/Bindings/remoteproc/
H A D	ti,omap-remoteproc.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Suman Anna <s-anna@ti.com> 13 The OMAP family of SoCs usually have one or more slave processor sub-systems 14 that are used to offload some of the processor-intensive tasks, or to manage 17 The processor cores in the sub-system are usually behind an IOMMU, and may 18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2 21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor [all …]
H A D	ti,k3-dsp-rproc.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-ds [all...]`
H A D	ti,k3-r5f-rproc.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Suman Anna <s-anna@ti.com> 13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F 20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode 21 called "Single-CPU" mode, where only Core0 is used, but with ability to use 27 Each Dual-Core R5F sub-system is represented as a single DTS node 40 - ti,am62-r5fss [all …]
H A D	qcom,sc7280-mss-pil.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-mss-pil.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sibi Sankar <quic_sibis@quicinc.com> 19 - qcom,sc7280-mss-pil 23 - description: MSS QDSP6 registers 24 - description: RMB registers 26 reg-names: 28 - const: qdsp6 [all …]`
H A D	qcom,sc7180-mss-pil.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-mss-pil.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sibi Sankar <quic_sibis@quicinc.com> 19 - qcom,sc7180-mss-pil 23 - description: MSS QDSP6 registers 24 - description: RMB registers 26 reg-names: 28 - const: qdsp6 [all …]`
/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A D	arm,scmi.txt	2 ---------------------------------------------------------- 17 - compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports 18 - mboxes: List of phandle and mailbox channel specifiers. It should contain 22 - shmem : List of phandle pointing to the shared memory(SHM) area as per 23 generic mailbox client binding. 24 - #address-cells : should be '1' if the device has sub-nodes, maps to 25 protocol identifier for a given sub-node. 26 - #size-cells : should be '0' as 'reg' property doesn't have any size 28 - arm,smc-id : SMC id required when using smc or hvc transports 32 - mbox-names: shall be "tx" or "rx" depending on mboxes entries. [all …]
H A D	arm,scpi.txt	2 ---------------------------------------------------------- 10 - compatible : should be 12 * "arm,scpi-pre-1.0" : For implementations complying to all 14 - mboxes: List of phandle and mailbox channel specifiers 17 - shmem : List of phandle pointing to the shared memory(SHM) area between the 18 processors using these mailboxes for IPC, one for each mailbox 22 See Documentation/devicetree/bindings/mailbox/mailbox.txt 23 for more details about the generic mailbox controller and 27 ------------------------------------------------------------ 34 - compatible : should be "arm,scpi-clocks" [all …]
/freebsd-src/sys/contrib/device-tree/Bindings/power/reset/
H A D	xlnx,zynqmp-power.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Michal Simek <michal.simek@amd.com> 13 The zynqmp-power node describes the power management configurations. 18 const: xlnx,zynqmp-power 25 Standard property to specify a Mailbox. Each value of 27 mailbox controller device node and an args specifier 28 that will be the phandle to the intended sub-mailbox [all …]
H A D	xlnx,zynqmp-power.txt	1 -------------------------------------------------------------------- 3 -------------------------------------------------------------------- 4 The zynqmp-power node describes the power management configurations. 8 - compatible: Must contain: "xlnx,zynqmp-power" 9 - interrupts: Interrupt specifier 12 - mbox-names : Name given to channels seen in the 'mboxes' property. 13 "tx" - Mailbox corresponding to transmit path 14 "rx" - Mailbox corresponding to receive path 15 - mboxes : Standard property to specify a Mailbox. Each value of 17 mailbox controller device node and an args specifier [all …]
/freebsd-src/sys/contrib/device-tree/Bindings/firmware/
H A D	arm,scpi.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Sudeep Holla <sudeep.holla@arm.com> 33 - const: arm,scpi # SCPI v1.0 and above 34 - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0 35 - items: 36 - enum: 37 - amlogic,meson-gxbb-scpi 38 - const: arm,scpi-pre-1.0 [all …]`
H A D	arm,scmi.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Sudee [all...]`
/freebsd-src/sys/contrib/device-tree/Bindings/arm/keystone/
H A D	ti,sci.txt	1 Texas Instruments System Control Interface (TI-SCI) Message Protocol 2 -------------------------------------------------------------------- 16 TI-SCI controller Device Node: 19 The TI-SCI node describes the Texas Instrument's System Controller entity node. 23 relationship between the TI-SCI parent node to the child node. 26 ------------------- 27 - compatible: should be "ti,k2g-sci" for TI 66AK2G SoC 28 should be "ti,am654-sci" for for TI AM654 SoC 29 - mbox-names: 30 "rx" - Mailbox corresponding to receive path [all …]
/freebsd-src/usr.sbin/bhyve/amd64/
H A D	pci_gvt-d-opregion.h	7 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> 8 SPDX-License-Identifier: BSD-2-Clause-Patent 14 …* <https://github.com/tianocore/edk2-platforms/blob/82979ab1ca44101e0b92a9c4bda1dfe64a8249f6/Silic… 32 Sub-structures define the different parts of the OpRegion followed by the 41 /// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to 60 /// OpRegion Mailbox 1 - Public ACPI Methods 88 uint8_t rm12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero 92 /// OpRegion Mailbox 2 - Software SCI Interface 99 uint8_t rm21[0xF4]; ///< Offset 0x20C - 0x2FF Reserved Must be zero 103 /// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support [all …]
/freebsd-src/crypto/openssl/doc/man3/
H A D	X509_check_host.pod	5 X509_check_host, X509_check_email, X509_check_ip, X509_check_ip_asc - X.509 certificate matching 30 and they match only in the left-most label; but they may match 37 domain names must be given in A-label form. The B<namelen> argument 41 valid for any sub-domain of B<name>, (see also 51 email B<address>. The mailbox syntax of RFC 822 is supported, 53 characters. The mailbox syntax of RFC 6531 is supported for 56 is made to convert from A-label to U-label before comparison. 68 X509_check_ip_asc() is similar, except that the NUL-terminated 118 values which start with ".", that would otherwise match any sub-domain 119 in the peer certificate, to only match direct child sub-domains. [all …]
/freebsd-src/secure/lib/libcrypto/man/man3/
H A D	X509_check_host.3	18 .\" Set up some character translations and predefined strings. \(-- will 24 .tr \(W- 27 . ds -- \(W- 29 . if (\n(.H=4u)&(1m=24u) .ds -- \(W\h'-12u'\(W\h'-12u'-\" diablo 10 pitch 30 . if (\n(.H=4u)&(1m=20u) .ds -- \(W\h'-12u'\(W\h'-8u'-\" diablo 12 pitch 37 . ds -- \\|\(em\\| 71 .\" Fear. Run. Save yourself. No user-serviceable parts. 81 . ds #H ((1u-(\\\\n(.fu%2u)).13m) 97 . ds ' \\k:\h'-(\\n(.wu8/10-\(#H)'\'\h"\|\\n:u" 98 . ds ` \\k:\h'-(\\n(.wu8/10-\(#H)'\`\h'\|\\n:u' [all …]
/freebsd-src/sys/contrib/device-tree/Bindings/usb/
H A D	omap-usb.txt	4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb" 5 - ti,hwmods : must be "usb_otg_hs" 6 - multipoint : Should be "1" indicating the musb controller supports 7 multipoint. This is a MUSB configuration-specific setting. 8 - num-eps : Specifies the number of endpoints. This is also a 9 MUSB configuration-specific setting. Should be set to "16" 10 - ram-bits : Specifies the ram address size. Should be set to "12" 11 - interface-type : This is a board specific setting to describe the type of 14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2" 16 - power : Should be "50". This signifies the controller can supply up to [all …]
/freebsd-src/share/syscons/keymaps/
H A D	us.iso.macbook.kbd	`1 # by Willian Theesfeld Jr <wtheesfeld@mailbox.org> 5 # ------------------------------------------------------------------ 18 012 '-' '_' us us '-' '_' us us O 50 044 'z' 'Z' sub sub 'z' 'Z' sub sub C 80 074 fkey52 '-' '-' '-' '-' '-' '-' '-' N`
/freebsd-src/share/vt/keymaps/
H A D	us.macbook.kbd	`1 # by Willian Theesfeld Jr <wtheesfeld@mailbox.org> 5 # ------------------------------------------------------------------ 18 012 '-' '_' us us '-' '_' us us O 50 044 'z' 'Z' sub sub 'z' 'Z' sub sub C 80 074 fkey52 '-' '-' '-' '-' '-' '-' '-' N`
/freebsd-src/sys/contrib/device-tree/Bindings/arm/freescale/
H A D	fsl,scu.txt	2 -------------------------------------------------------------------- 4 The System Controller Firmware (SCFW) is a low-level system function 5 which runs on a dedicated Cortex-M core to provide power, clock, and 9 The AP communicates with the SC using a multi-ported MU module found 22 ------------------- 23 - compatible: should be "fsl,imx-scu". 24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3", 27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for 50 See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml 51 for detailed mailbox binding. [all …]
/freebsd-src/sys/contrib/dev/athk/ath10k/
H A D	targaddrs.h	1 /* SPDX-License-Identifier: ISC / 3 Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2016 Qualcomm Atheros, Inc. 36 * Pointer to application-defined area, if any. 50 * General-purpose flag bits, similar to SOC_OPTION_* flags. 103 u32 hi_num_bpatch_streams; /* 0x70 -- unused / 124 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high 143 /* 0xbc - [31:0]: idle timeout in ms / 150 / If non-zero, override values sent to Host in WMI_READY event. / 177 / Interconnect-specific state */ [all …]
/freebsd-src/sys/contrib/dev/rtw89/
H A D	core.h	`1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / 2 / Copyright(c) 2019-2020 Realtek Corporation 50 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 107 RTW89_CH_6G_BAND_IDX6, /* Ultra-high / 108 RTW89_CH_6G_BAND_IDX7, / Ultra-high / 256 RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 3451 u8 mailbox; global() member 3592 RTW89_FW_VER_CODE(major,minor,sub,idx) global() argument 3730 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; global() member [all...]`
/freebsd-src/contrib/sendmail/src/
H A D	parseaddr.c	2 * Copyright (c) 1998-2006 Proofpoint, Inc. and its suppliers. 4 * Copyright (c) 1983, 1995-1997 Eric P. Allman. All rights reserved. 16 SM_RCSID("@(#)$Id: parseaddr.c,v 8.407 2013-11-22 20:51:56 ca Exp $") 32 PARSEADDR -- Parse an address 43 of 'berkeley' -- to be transmitted over the arpanet. 46 addr -- the address to parse. [i] 47 a -- a pointer to the address descriptor buffer. 49 flags -- describe detail for parsing. See RF_ definitions 51 delim -- the character to terminate the address, passed 53 ** delimptr -- if non-NULL, set to the location of the [all …]

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